From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Bin Meng" <bmeng.cn@gmail.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:SD (Secure Card)" <qemu-block@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v3 0/3] Introduce a new Write Protected pin inverted property
Date: Thu, 14 Nov 2024 17:48:36 +0800 [thread overview]
Message-ID: <20241114094839.4128404-1-jamin_lin@aspeedtech.com> (raw)
change from v1:
1. Support RTC for AST2700.
2. Support SDHCI write protected pin inverted for AST2500 and AST2600.
3. Introduce Capabilities Register 2 for SD slot 0 and 1.
4. Support create flash devices via command line for AST1030.
change from v2:
replace wp-invert with wp-inverted and fix review issues.
change from v3:
1. add reviewer suggestion about wp_inverted comment
2. AST2500 EVB does not need to set wp-inverted property of sdhci model
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dts#L110
Jamin Lin (3):
hw/sd/sdhci: Fix coding style
hw/sd/sdhci: Introduce a new Write Protected pin inverted property
hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB
hw/arm/aspeed.c | 7 +++++
hw/sd/sdhci.c | 70 ++++++++++++++++++++++++++++-------------
include/hw/arm/aspeed.h | 1 +
include/hw/sd/sdhci.h | 5 +++
4 files changed, 61 insertions(+), 22 deletions(-)
--
2.34.1
next reply other threads:[~2024-11-14 9:49 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-14 9:48 Jamin Lin via [this message]
2024-11-14 9:48 ` [PATCH v3 1/3] hw/sd/sdhci: Fix coding style Jamin Lin via
2025-01-07 19:28 ` Philippe Mathieu-Daudé
2024-11-14 9:48 ` [PATCH v3 2/3] hw/sd/sdhci: Introduce a new Write Protected pin inverted property Jamin Lin via
2025-01-07 19:29 ` Philippe Mathieu-Daudé
2025-01-21 10:38 ` Cédric Le Goater
2025-01-22 2:04 ` Jamin Lin
2024-11-14 9:48 ` [PATCH v3 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB Jamin Lin via
2025-01-07 19:29 ` Philippe Mathieu-Daudé
2024-11-27 9:44 ` [PATCH v3 0/3] Introduce a new Write Protected pin inverted property Cédric Le Goater
2024-11-27 11:23 ` Philippe Mathieu-Daudé
2024-11-27 11:26 ` Cédric Le Goater
2024-11-28 11:06 ` Peter Maydell
2025-01-07 17:54 ` Cédric Le Goater
2025-01-07 22:36 ` Peter Maydell
2025-01-08 9:11 ` Cédric Le Goater
2024-11-28 5:37 ` Jamin Lin
2025-01-07 18:16 ` Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241114094839.4128404-1-jamin_lin@aspeedtech.com \
--to=qemu-devel@nongnu.org \
--cc=andrew@codeconstruct.com.au \
--cc=bmeng.cn@gmail.com \
--cc=clg@kaod.org \
--cc=jamin_lin@aspeedtech.com \
--cc=joel@jms.id.au \
--cc=leetroy@gmail.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-block@nongnu.org \
--cc=steven_lee@aspeedtech.com \
--cc=troy_lee@aspeedtech.com \
--cc=yunlin.tang@aspeedtech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).