From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Bin Meng" <bmeng.cn@gmail.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:SD (Secure Card)" <qemu-block@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v3 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB
Date: Thu, 14 Nov 2024 17:48:39 +0800 [thread overview]
Message-ID: <20241114094839.4128404-4-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20241114094839.4128404-1-jamin_lin@aspeedtech.com>
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24).
According to the design of AST2600 EVB, the Write Protected pin is active
high by default. To support it, introduces a new "sdhci_wp_inverted"
property in ASPEED MACHINE State and set it true for AST2600 EVB
and set "wp_inverted" property true of sdhci-generic model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
---
hw/arm/aspeed.c | 7 +++++++
include/hw/arm/aspeed.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 6ca145362c..a58b7160cd 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -413,6 +413,12 @@ static void aspeed_machine_init(MachineState *machine)
OBJECT(get_system_memory()), &error_abort);
object_property_set_link(OBJECT(bmc->soc), "dram",
OBJECT(machine->ram), &error_abort);
+ if (amc->sdhci_wp_inverted) {
+ for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
+ object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]),
+ "wp-inverted", true, &error_abort);
+ }
+ }
if (machine->kernel_filename) {
/*
* When booting with a -kernel command line there is no u-boot
@@ -1419,6 +1425,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
amc->num_cs = 1;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
ASPEED_MAC3_ON;
+ amc->sdhci_wp_inverted = true;
amc->i2c_init = ast2600_evb_i2c_init;
mc->default_ram_size = 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index cbeacb214c..9cae45a1c9 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -39,6 +39,7 @@ struct AspeedMachineClass {
uint32_t macs_mask;
void (*i2c_init)(AspeedMachineState *bmc);
uint32_t uart_default;
+ bool sdhci_wp_inverted;
};
--
2.34.1
next prev parent reply other threads:[~2024-11-14 9:50 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-14 9:48 [PATCH v3 0/3] Introduce a new Write Protected pin inverted property Jamin Lin via
2024-11-14 9:48 ` [PATCH v3 1/3] hw/sd/sdhci: Fix coding style Jamin Lin via
2025-01-07 19:28 ` Philippe Mathieu-Daudé
2024-11-14 9:48 ` [PATCH v3 2/3] hw/sd/sdhci: Introduce a new Write Protected pin inverted property Jamin Lin via
2025-01-07 19:29 ` Philippe Mathieu-Daudé
2025-01-21 10:38 ` Cédric Le Goater
2025-01-22 2:04 ` Jamin Lin
2024-11-14 9:48 ` Jamin Lin via [this message]
2025-01-07 19:29 ` [PATCH v3 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB Philippe Mathieu-Daudé
2024-11-27 9:44 ` [PATCH v3 0/3] Introduce a new Write Protected pin inverted property Cédric Le Goater
2024-11-27 11:23 ` Philippe Mathieu-Daudé
2024-11-27 11:26 ` Cédric Le Goater
2024-11-28 11:06 ` Peter Maydell
2025-01-07 17:54 ` Cédric Le Goater
2025-01-07 22:36 ` Peter Maydell
2025-01-08 9:11 ` Cédric Le Goater
2024-11-28 5:37 ` Jamin Lin
2025-01-07 18:16 ` Cédric Le Goater
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