From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
qemu-arm@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
"Thomas Huth" <thuth@redhat.com>, "Anton Johansson" <anjo@rev.ng>,
"Bernhard Beschow" <shentey@gmail.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Gustavo Romero" <gustavo.romero@linaro.org>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Edgar E . Iglesias" <edgar.iglesias@amd.com>
Subject: [PATCH RESEND v2 18/19] hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container'
Date: Thu, 14 Nov 2024 22:00:09 +0100 [thread overview]
Message-ID: <20241114210010.34502-19-philmd@linaro.org> (raw)
In-Reply-To: <20241114210010.34502-1-philmd@linaro.org>
Having all its address range mapped by subregions,
s->mmio MemoryRegion effectively became a container.
Rename it as 'container' for clarity.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/net/xilinx_ethlite.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 0d445653b2..5f1ff7b712 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -86,7 +86,7 @@ struct XlnxXpsEthLite
{
SysBusDevice parent_obj;
- MemoryRegion mmio;
+ MemoryRegion container;
qemu_irq irq;
NICState *nic;
NICConf conf;
@@ -301,7 +301,7 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
{
XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
- memory_region_init(&s->mmio, OBJECT(dev),
+ memory_region_init(&s->container, OBJECT(dev),
"xlnx.xps-ethernetlite", 0x2000);
object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio,
@@ -309,31 +309,31 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio");
qdev_prop_set_uint64(DEVICE(&s->mdio), "size", 4 * 4);
sysbus_realize(SYS_BUS_DEVICE(&s->mdio), &error_fatal);
- memory_region_add_subregion(&s->mmio, A_MDIO_BASE,
+ memory_region_add_subregion(&s->container, A_MDIO_BASE,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0));
for (unsigned i = 0; i < 2; i++) {
memory_region_init_ram(&s->port[i].txbuf, OBJECT(dev),
i ? "ethlite.tx[1]buf" : "ethlite.tx[0]buf",
BUFSZ_MAX, &error_abort);
- memory_region_add_subregion(&s->mmio, 0x0800 * i, &s->port[i].txbuf);
+ memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf);
memory_region_init_io(&s->port[i].txio, OBJECT(dev),
ð_porttx_ops, s,
i ? "ethlite.tx[1]io" : "ethlite.tx[0]io",
4 * TX_MAX);
- memory_region_add_subregion(&s->mmio, i ? A_TX_BASE1 : A_TX_BASE0,
+ memory_region_add_subregion(&s->container, i ? A_TX_BASE1 : A_TX_BASE0,
&s->port[i].txio);
memory_region_init_ram(&s->port[i].rxbuf, OBJECT(dev),
i ? "ethlite.rx[1]buf" : "ethlite.rx[0]buf",
BUFSZ_MAX, &error_abort);
- memory_region_add_subregion(&s->mmio, 0x1000 + 0x0800 * i,
+ memory_region_add_subregion(&s->container, 0x1000 + 0x0800 * i,
&s->port[i].rxbuf);
memory_region_init_io(&s->port[i].rxio, OBJECT(dev),
ð_portrx_ops, s,
i ? "ethlite.rx[1]io" : "ethlite.rx[0]io",
4 * RX_MAX);
- memory_region_add_subregion(&s->mmio, i ? A_RX_BASE1 : A_RX_BASE0,
+ memory_region_add_subregion(&s->container, i ? A_RX_BASE1 : A_RX_BASE0,
&s->port[i].rxio);
}
@@ -349,7 +349,7 @@ static void xilinx_ethlite_init(Object *obj)
XlnxXpsEthLite *s = XILINX_ETHLITE(obj);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
- sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
}
static Property xilinx_ethlite_properties[] = {
--
2.45.2
next prev parent reply other threads:[~2024-11-14 21:05 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-14 20:59 [PATCH RESEND v2 00/19] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 01/19] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 02/19] hw/net/xilinx_ethlite: Convert some debug logs to trace events Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 03/19] hw/net/xilinx_ethlite: Remove unuseful debug logs Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 04/19] hw/net/xilinx_ethlite: Update QOM style Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 05/19] hw/net/xilinx_ethlite: Correct maximum RX buffer size Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 06/19] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented) Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 07/19] hw/net/xilinx_ethlite: Rename rxbuf -> port_index Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 08/19] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 09/19] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 10/19] hw/net/xilinx_ethlite: Access TX_GIE register for each port Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 11/19] hw/net/xilinx_ethlite: Access TX_LEN " Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 12/19] hw/net/xilinx_ethlite: Access TX_CTRL " Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 13/19] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 14/19] hw/net/xilinx_ethlite: Map TX_LEN " Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 15/19] hw/net/xilinx_ethlite: Map TX_GIE " Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 16/19] hw/net/xilinx_ethlite: Map TX_CTRL " Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 17/19] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region Philippe Mathieu-Daudé
2024-11-14 21:00 ` Philippe Mathieu-Daudé [this message]
2024-11-14 21:00 ` [PATCH RESEND v2 19/19] hw/net/xilinx_ethlite: Map RESERVED I/O as unimplemented Philippe Mathieu-Daudé
2024-11-15 10:33 ` Alex Bennée
2025-01-12 18:17 ` [PATCH RESEND v2 00/19] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Philippe Mathieu-Daudé
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