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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	qemu-arm@nongnu.org,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Thomas Huth" <thuth@redhat.com>, "Anton Johansson" <anjo@rev.ng>,
	"Bernhard Beschow" <shentey@gmail.com>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Gustavo Romero" <gustavo.romero@linaro.org>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Jason Wang" <jasowang@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Edgar E . Iglesias" <edgar.iglesias@amd.com>
Subject: [PATCH RESEND v2 06/19] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented)
Date: Thu, 14 Nov 2024 21:59:57 +0100	[thread overview]
Message-ID: <20241114210010.34502-7-philmd@linaro.org> (raw)
In-Reply-To: <20241114210010.34502-1-philmd@linaro.org>

Rather than handling the MDIO registers as RAM, map them
as unimplemented I/O within the device MR.

The memory flat view becomes:

  (qemu) info mtree -f
  FlatView #0
   Root memory region: system
    0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
    00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio
    00000000810007f4-0000000081001fff (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f4

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
---
 hw/net/xilinx_ethlite.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 0df962cd22..8de3131408 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -28,15 +28,18 @@
 #include "qemu/osdep.h"
 #include "qemu/module.h"
 #include "qom/object.h"
+#include "qapi/error.h"
 #include "exec/tswap.h"
 #include "hw/sysbus.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
+#include "hw/misc/unimp.h"
 #include "net/net.h"
 #include "trace.h"
 
 #define R_TX_BUF0     0
 #define BUFSZ_MAX      0x07e4
+#define A_MDIO_BASE    0x07e4
 #define R_TX_LEN0     (0x07f4 / 4)
 #define R_TX_GIE0     (0x07f8 / 4)
 #define R_TX_CTRL0    (0x07fc / 4)
@@ -73,6 +76,7 @@ struct XlnxXpsEthLite
     unsigned int txbuf;
     unsigned int rxbuf;
 
+    UnimplementedDeviceState mdio;
     uint32_t regs[R_MAX];
 };
 
@@ -233,6 +237,14 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
 {
     XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
 
+    object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio,
+                            TYPE_UNIMPLEMENTED_DEVICE);
+    qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio");
+    qdev_prop_set_uint64(DEVICE(&s->mdio), "size", 4 * 4);
+    sysbus_realize(SYS_BUS_DEVICE(&s->mdio), &error_fatal);
+    memory_region_add_subregion(&s->mmio, A_MDIO_BASE,
+                           sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0));
+
     qemu_macaddr_default_if_unset(&s->conf.macaddr);
     s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
                           object_get_typename(OBJECT(dev)), dev->id,
-- 
2.45.2



  parent reply	other threads:[~2024-11-14 21:03 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-14 20:59 [PATCH RESEND v2 00/19] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 01/19] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 02/19] hw/net/xilinx_ethlite: Convert some debug logs to trace events Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 03/19] hw/net/xilinx_ethlite: Remove unuseful debug logs Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 04/19] hw/net/xilinx_ethlite: Update QOM style Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 05/19] hw/net/xilinx_ethlite: Correct maximum RX buffer size Philippe Mathieu-Daudé
2024-11-14 20:59 ` Philippe Mathieu-Daudé [this message]
2024-11-14 20:59 ` [PATCH RESEND v2 07/19] hw/net/xilinx_ethlite: Rename rxbuf -> port_index Philippe Mathieu-Daudé
2024-11-14 20:59 ` [PATCH RESEND v2 08/19] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 09/19] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 10/19] hw/net/xilinx_ethlite: Access TX_GIE register for each port Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 11/19] hw/net/xilinx_ethlite: Access TX_LEN " Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 12/19] hw/net/xilinx_ethlite: Access TX_CTRL " Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 13/19] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 14/19] hw/net/xilinx_ethlite: Map TX_LEN " Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 15/19] hw/net/xilinx_ethlite: Map TX_GIE " Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 16/19] hw/net/xilinx_ethlite: Map TX_CTRL " Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 17/19] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 18/19] hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container' Philippe Mathieu-Daudé
2024-11-14 21:00 ` [PATCH RESEND v2 19/19] hw/net/xilinx_ethlite: Map RESERVED I/O as unimplemented Philippe Mathieu-Daudé
2024-11-15 10:33   ` Alex Bennée
2025-01-12 18:17 ` [PATCH RESEND v2 00/19] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Philippe Mathieu-Daudé

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