* [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0
@ 2024-11-21 6:12 baturo.alexey
2024-11-21 6:12 ` [PATCH v2 1/7] target/riscv: Remove obsolete pointer masking extension code baturo.alexey
` (7 more replies)
0 siblings, 8 replies; 13+ messages in thread
From: baturo.alexey @ 2024-11-21 6:12 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, dbarboza, liwei1518,
alistair23, frank.chang, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Hi,
I've rebased this patch series and addressed Richard's and Daniel's comments.
Thanks
*** BLURB HERE ***
[v0]:
As Pointer Masking is finally ratified, these patches intend to update the existing code to the final version.
These patches have been submitted previously and I tried to address all the suggestions, but I'd suggest to review them from the clean slate and then finally push them to the repo.
Thanks.
Alexey Baturo (7):
target/riscv: Remove obsolete pointer masking extension code.
target/riscv: Add new CSR fields for S{sn,mn,m}pm extensions as part
of Zjpm v1.0
target/riscv: Add helper functions to calculate current number of
masked bits for pointer masking
target/riscv: Add pointer masking tb flags
target/riscv: Update address modify functions to take into account
pointer masking
target/riscv: Apply pointer masking for virtualized memory accesses
target/riscv: Enable updates for pointer masking variables and thus
enable pointer masking extension
target/riscv/cpu.c | 19 +-
target/riscv/cpu.h | 51 ++--
target/riscv/cpu_bits.h | 91 +-----
target/riscv/cpu_cfg.h | 3 +
target/riscv/cpu_helper.c | 124 +++++---
target/riscv/csr.c | 357 ++----------------------
target/riscv/insn_trans/trans_rvh.c.inc | 11 +
target/riscv/machine.c | 17 +-
target/riscv/pmp.c | 14 +-
target/riscv/pmp.h | 1 +
target/riscv/tcg/tcg-cpu.c | 5 +-
target/riscv/translate.c | 51 ++--
target/riscv/vector_helper.c | 18 +-
13 files changed, 224 insertions(+), 538 deletions(-)
--
2.39.5
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH v2 1/7] target/riscv: Remove obsolete pointer masking extension code. 2024-11-21 6:12 [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 baturo.alexey @ 2024-11-21 6:12 ` baturo.alexey 2024-11-25 4:01 ` Alistair Francis 2024-11-21 6:12 ` [PATCH v2 2/7] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 baturo.alexey ` (6 subsequent siblings) 7 siblings, 1 reply; 13+ messages in thread From: baturo.alexey @ 2024-11-21 6:12 UTC (permalink / raw) Cc: baturo.alexey, richard.henderson, zhiwei_liu, dbarboza, liwei1518, alistair23, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv From: Alexey Baturo <baturo.alexey@gmail.com> Zjpm extension is finally ratified. And it's much simplier compared to the experimental one. The newer version doesn't allow to specify custom mask or base for pointer masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> --- target/riscv/cpu.c | 13 +- target/riscv/cpu.h | 33 +--- target/riscv/cpu_bits.h | 87 ---------- target/riscv/cpu_helper.c | 52 ------ target/riscv/csr.c | 326 ----------------------------------- target/riscv/machine.c | 17 +- target/riscv/tcg/tcg-cpu.c | 5 +- target/riscv/translate.c | 28 +-- target/riscv/vector_helper.c | 2 +- 9 files changed, 19 insertions(+), 544 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b5..4e80dcd2e6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -42,7 +42,7 @@ /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH"; const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV, - RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0}; + RVC, RVS, RVU, RVH, RVG, RVB, 0}; /* * From vector_helper.c @@ -793,13 +793,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) CSR_MSCRATCH, CSR_SSCRATCH, CSR_SATP, - CSR_MMTE, - CSR_UPMBASE, - CSR_UPMMASK, - CSR_SPMBASE, - CSR_SPMMASK, - CSR_MPMBASE, - CSR_MPMMASK, }; for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { @@ -985,8 +978,6 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) } i++; } - /* mmte is supposed to have pm.current hardwired to 1 */ - env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); /* * Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor @@ -1018,7 +1009,6 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) env->ssp = 0; env->xl = riscv_cpu_mxl(env); - riscv_cpu_update_mask(env); cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); @@ -1406,7 +1396,6 @@ static const MISAExtInfo misa_ext_info_arr[] = { MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"), MISA_EXT_INFO(RVU, "u", "User-level instructions"), MISA_EXT_INFO(RVH, "h", "Hypervisor"), - MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), MISA_EXT_INFO(RVV, "v", "Vector operations"), MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)") diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..e11264231d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -71,7 +71,6 @@ typedef struct CPUArchState CPURISCVState; #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') -#define RVJ RV('J') #define RVG RV('G') #define RVB RV('B') @@ -451,24 +450,11 @@ struct CPUArchState { /* True if in debugger mode. */ bool debugger; - /* - * CSRs for PointerMasking extension - */ - target_ulong mmte; - target_ulong mpmmask; - target_ulong mpmbase; - target_ulong spmmask; - target_ulong spmbase; - target_ulong upmmask; - target_ulong upmbase; - uint64_t mstateen[SMSTATEEN_MAX_COUNT]; uint64_t hstateen[SMSTATEEN_MAX_COUNT]; uint64_t sstateen[SMSTATEEN_MAX_COUNT]; uint64_t henvcfg; #endif - target_ulong cur_pmmask; - target_ulong cur_pmbase; /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ @@ -624,19 +610,19 @@ FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) -FIELD(TB_FLAGS, VTA, 20, 1) -FIELD(TB_FLAGS, VMA, 21, 1) +FIELD(TB_FLAGS, VTA, 18, 1) +FIELD(TB_FLAGS, VMA, 19, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 22, 1) +FIELD(TB_FLAGS, ITRIGGER, 20, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) -FIELD(TB_FLAGS, PRIV, 24, 2) -FIELD(TB_FLAGS, AXL, 26, 2) +FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) +FIELD(TB_FLAGS, PRIV, 22, 2) +FIELD(TB_FLAGS, AXL, 24, 2) /* zicfilp needs a TB flag to track indirect branches */ -FIELD(TB_FLAGS, FCFI_ENABLED, 28, 1) -FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 29, 1) +FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1) +FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1) /* zicfiss needs a TB flag so that correct TB is located based on tb flags */ -FIELD(TB_FLAGS, BCFI_ENABLED, 30, 1) +FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) @@ -772,7 +758,6 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); -void riscv_cpu_update_mask(CPURISCVState *env); bool riscv_cpu_is_32bit(RISCVCPU *cpu); RISCVException riscv_csrr(CPURISCVState *env, int csrno, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 385a2c67c2..2a6aff63ed 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -497,37 +497,6 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f -/* - * User PointerMasking registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_UMTE 0x4c0 -#define CSR_UPMMASK 0x4c1 -#define CSR_UPMBASE 0x4c2 - -/* - * Machine PointerMasking registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_MMTE 0x3c0 -#define CSR_MPMMASK 0x3c1 -#define CSR_MPMBASE 0x3c2 - -/* - * Supervisor PointerMaster registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_SMTE 0x1c0 -#define CSR_SPMMASK 0x1c1 -#define CSR_SPMBASE 0x1c2 - -/* - * Hypervisor PointerMaster registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_VSMTE 0x2c0 -#define CSR_VSPMMASK 0x2c1 -#define CSR_VSPMBASE 0x2c2 #define CSR_SCOUNTOVF 0xda0 /* Crypto Extension */ @@ -758,11 +727,6 @@ typedef enum RISCVException { #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) -/* General PointerMasking CSR bits */ -#define PM_ENABLE 0x00000001ULL -#define PM_CURRENT 0x00000002ULL -#define PM_INSN 0x00000004ULL - /* Execution environment configuration bits */ #define MENVCFG_FIOM BIT(0) #define MENVCFG_LPE BIT(2) /* zicfilp */ @@ -801,57 +765,6 @@ typedef enum RISCVException { #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE -/* Offsets for every pair of control bits per each priv level */ -#define XS_OFFSET 0ULL -#define U_OFFSET 2ULL -#define S_OFFSET 5ULL -#define M_OFFSET 8ULL - -#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET) -#define U_PM_ENABLE (PM_ENABLE << U_OFFSET) -#define U_PM_CURRENT (PM_CURRENT << U_OFFSET) -#define U_PM_INSN (PM_INSN << U_OFFSET) -#define S_PM_ENABLE (PM_ENABLE << S_OFFSET) -#define S_PM_CURRENT (PM_CURRENT << S_OFFSET) -#define S_PM_INSN (PM_INSN << S_OFFSET) -#define M_PM_ENABLE (PM_ENABLE << M_OFFSET) -#define M_PM_CURRENT (PM_CURRENT << M_OFFSET) -#define M_PM_INSN (PM_INSN << M_OFFSET) - -/* mmte CSR bits */ -#define MMTE_PM_XS_BITS PM_XS_BITS -#define MMTE_U_PM_ENABLE U_PM_ENABLE -#define MMTE_U_PM_CURRENT U_PM_CURRENT -#define MMTE_U_PM_INSN U_PM_INSN -#define MMTE_S_PM_ENABLE S_PM_ENABLE -#define MMTE_S_PM_CURRENT S_PM_CURRENT -#define MMTE_S_PM_INSN S_PM_INSN -#define MMTE_M_PM_ENABLE M_PM_ENABLE -#define MMTE_M_PM_CURRENT M_PM_CURRENT -#define MMTE_M_PM_INSN M_PM_INSN -#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \ - MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \ - MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \ - MMTE_PM_XS_BITS) - -/* (v)smte CSR bits */ -#define SMTE_PM_XS_BITS PM_XS_BITS -#define SMTE_U_PM_ENABLE U_PM_ENABLE -#define SMTE_U_PM_CURRENT U_PM_CURRENT -#define SMTE_U_PM_INSN U_PM_INSN -#define SMTE_S_PM_ENABLE S_PM_ENABLE -#define SMTE_S_PM_CURRENT S_PM_CURRENT -#define SMTE_S_PM_INSN S_PM_INSN -#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \ - SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \ - SMTE_PM_XS_BITS) - -/* umte CSR bits */ -#define UMTE_U_PM_ENABLE U_PM_ENABLE -#define UMTE_U_PM_CURRENT U_PM_CURRENT -#define UMTE_U_PM_INSN U_PM_INSN -#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) - /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ #define ISELECT_IPRIO0 0x30 #define ISELECT_IPRIO15 0x3f diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0a3ead69ea..696a17461b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -210,61 +210,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - if (env->cur_pmmask != 0) { - flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); - } - if (env->cur_pmbase != 0) { - flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); - } *pflags = flags; } -void riscv_cpu_update_mask(CPURISCVState *env) -{ - target_ulong mask = 0, base = 0; - RISCVMXL xl = env->xl; - /* - * TODO: Current RVJ spec does not specify - * how the extension interacts with XLEN. - */ -#ifndef CONFIG_USER_ONLY - int mode = cpu_address_mode(env); - xl = cpu_get_xl(env, mode); - if (riscv_has_ext(env, RVJ)) { - switch (mode) { - case PRV_M: - if (env->mmte & M_PM_ENABLE) { - mask = env->mpmmask; - base = env->mpmbase; - } - break; - case PRV_S: - if (env->mmte & S_PM_ENABLE) { - mask = env->spmmask; - base = env->spmbase; - } - break; - case PRV_U: - if (env->mmte & U_PM_ENABLE) { - mask = env->upmmask; - base = env->upmbase; - } - break; - default: - g_assert_not_reached(); - } - } -#endif - if (xl == MXL_RV32) { - env->cur_pmmask = mask & UINT32_MAX; - env->cur_pmbase = base & UINT32_MAX; - } else { - env->cur_pmmask = mask; - env->cur_pmbase = base; - } -} - #ifndef CONFIG_USER_ONLY /* @@ -786,7 +735,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en) /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv = newpriv; env->xl = cpu_recompute_xl(env); - riscv_cpu_update_mask(env); /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9846770820..941c9691da 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -531,16 +531,6 @@ static RISCVException hgatp(CPURISCVState *env, int csrno) return hmode(env, csrno); } -/* Checks if PointerMasking registers could be accessed */ -static RISCVException pointer_masking(CPURISCVState *env, int csrno) -{ - /* Check if j-ext is present */ - if (riscv_has_ext(env, RVJ)) { - return RISCV_EXCP_NONE; - } - return RISCV_EXCP_ILLEGAL_INST; -} - static RISCVException aia_hmode(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia) { @@ -1648,7 +1638,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, env->xl = cpu_recompute_xl(env); } - riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } @@ -4351,302 +4340,6 @@ static RISCVException write_mcontext(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -/* - * Functions to access Pointer Masking feature registers - * We have to check if current priv lvl could modify - * csr in given mode - */ -static bool check_pm_current_disabled(CPURISCVState *env, int csrno) -{ - int csr_priv = get_field(csrno, 0x300); - int pm_current; - - if (env->debugger) { - return false; - } - /* - * If priv lvls differ that means we're accessing csr from higher priv lvl, - * so allow the access - */ - if (env->priv != csr_priv) { - return false; - } - switch (env->priv) { - case PRV_M: - pm_current = get_field(env->mmte, M_PM_CURRENT); - break; - case PRV_S: - pm_current = get_field(env->mmte, S_PM_CURRENT); - break; - case PRV_U: - pm_current = get_field(env->mmte, U_PM_CURRENT); - break; - default: - g_assert_not_reached(); - } - /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ - return !pm_current; -} - -static RISCVException read_mmte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->mmte & MMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mmte(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - target_ulong wpri_val = val & MMTE_MASK; - - if (val != wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x", - val, "vs expected 0x", wpri_val); - } - /* for machine mode pm.current is hardwired to 1 */ - wpri_val |= MMTE_M_PM_CURRENT; - - /* hardwiring pm.instruction bit to 0, since it's not supported yet */ - wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); - env->mmte = wpri_val | EXT_STATUS_DIRTY; - riscv_cpu_update_mask(env); - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_smte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->mmte & SMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_smte(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong wpri_val = val & SMTE_MASK; - - if (val != wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x", - val, "vs expected 0x", wpri_val); - } - - /* if pm.current==0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - - wpri_val |= (env->mmte & ~SMTE_MASK); - write_mmte(env, csrno, wpri_val); - return RISCV_EXCP_NONE; -} - -static RISCVException read_umte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->mmte & UMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_umte(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong wpri_val = val & UMTE_MASK; - - if (val != wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x", - val, "vs expected 0x", wpri_val); - } - - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - - wpri_val |= (env->mmte & ~UMTE_MASK); - write_mmte(env, csrno, wpri_val); - return RISCV_EXCP_NONE; -} - -static RISCVException read_mpmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->mpmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mpmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - env->mpmmask = val; - if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { - env->cur_pmmask = val; - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_spmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->spmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_spmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current==0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->spmmask = val; - if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { - env->cur_pmmask = val; - if (cpu_get_xl(env, PRV_S) == MXL_RV32) { - env->cur_pmmask &= UINT32_MAX; - } - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_upmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->upmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_upmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current==0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->upmmask = val; - if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { - env->cur_pmmask = val; - if (cpu_get_xl(env, PRV_U) == MXL_RV32) { - env->cur_pmmask &= UINT32_MAX; - } - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_mpmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->mpmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mpmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - env->mpmbase = val; - if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { - env->cur_pmbase = val; - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_spmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->spmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_spmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current==0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->spmbase = val; - if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { - env->cur_pmbase = val; - if (cpu_get_xl(env, PRV_S) == MXL_RV32) { - env->cur_pmbase &= UINT32_MAX; - } - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_upmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val = env->upmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_upmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current==0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->upmbase = val; - if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { - env->cur_pmbase = val; - if (cpu_get_xl(env, PRV_U) == MXL_RV32) { - env->cur_pmbase &= UINT32_MAX; - } - } - env->mmte |= EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus = env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - #endif /* Crypto Extension */ @@ -5316,25 +5009,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore }, [CSR_MCONTEXT] = { "mcontext", debug, read_mcontext, write_mcontext }, - /* User Pointer Masking */ - [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, - [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, - write_upmmask }, - [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, - write_upmbase }, - /* Machine Pointer Masking */ - [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, - [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, - write_mpmmask }, - [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, - write_mpmbase }, - /* Supervisor Pointer Masking */ - [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, - [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, - write_spmmask }, - [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, - write_spmbase }, - /* Performance Counters */ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter }, [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 99f0af5077..e40dc73994 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -152,25 +152,15 @@ static const VMStateDescription vmstate_vector = { static bool pointermasking_needed(void *opaque) { - RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; - - return riscv_has_ext(env, RVJ); + return false; } static const VMStateDescription vmstate_pointermasking = { .name = "cpu/pointer_masking", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .needed = pointermasking_needed, .fields = (const VMStateField[]) { - VMSTATE_UINTTL(env.mmte, RISCVCPU), - VMSTATE_UINTTL(env.mpmmask, RISCVCPU), - VMSTATE_UINTTL(env.mpmbase, RISCVCPU), - VMSTATE_UINTTL(env.spmmask, RISCVCPU), - VMSTATE_UINTTL(env.spmbase, RISCVCPU), - VMSTATE_UINTTL(env.upmmask, RISCVCPU), - VMSTATE_UINTTL(env.upmbase, RISCVCPU), VMSTATE_END_OF_LIST() } @@ -266,7 +256,6 @@ static int riscv_cpu_post_load(void *opaque, int version_id) CPURISCVState *env = &cpu->env; env->xl = cpu_recompute_xl(env); - riscv_cpu_update_mask(env); return 0; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c62c221696..179428f3f0 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1086,7 +1086,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { MISA_CFG(RVS, true), MISA_CFG(RVU, true), MISA_CFG(RVH, true), - MISA_CFG(RVJ, false), MISA_CFG(RVV, false), MISA_CFG(RVG, false), MISA_CFG(RVB, false), @@ -1373,8 +1372,8 @@ static void riscv_init_max_cpu_extensions(Object *obj) CPURISCVState *env = &cpu->env; const RISCVCPUMultiExtConfig *prop; - /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV); + /* Enable RVG and RVV that are disabled by default */ + riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index bccaf8e89a..018be5504f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -41,9 +41,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; -/* globals for PM CSRs */ -static TCGv pm_mask; -static TCGv pm_base; /* * If an operation is being performed on less than TARGET_LONG_BITS, @@ -105,9 +102,6 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; - /* PointerMasking extension */ - bool pm_mask_enabled; - bool pm_base_enabled; /* Ztso */ bool ztso; /* Use icount trigger for native debug */ @@ -591,14 +585,9 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); tcg_gen_addi_tl(addr, src1, imm); - if (ctx->pm_mask_enabled) { - tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_address_xl(ctx) == MXL_RV32) { + if (get_address_xl(ctx) == MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } - if (ctx->pm_base_enabled) { - tcg_gen_or_tl(addr, addr, pm_base); - } return addr; } @@ -610,14 +599,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); tcg_gen_add_tl(addr, src1, offs); - if (ctx->pm_mask_enabled) { - tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_xl(ctx) == MXL_RV32) { + if (get_xl(ctx) == MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } - if (ctx->pm_base_enabled) { - tcg_gen_or_tl(addr, addr, pm_base); - } + return addr; } @@ -1245,8 +1230,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs = cs; - ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); - ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); ctx->ztso = cpu->cfg.ext_ztso; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); @@ -1385,9 +1368,4 @@ void riscv_translate_init(void) "load_res"); load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val), "load_val"); - /* Assign PM CSRs to tcg globals */ - pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask), - "pmmask"); - pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase), - "pmbase"); } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a85dd1d200..3589e3ef28 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -107,7 +107,7 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz) static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) { - return (addr & ~env->cur_pmmask) | env->cur_pmbase; + return addr; } /* -- 2.39.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/7] target/riscv: Remove obsolete pointer masking extension code. 2024-11-21 6:12 ` [PATCH v2 1/7] target/riscv: Remove obsolete pointer masking extension code baturo.alexey @ 2024-11-25 4:01 ` Alistair Francis 2024-11-27 5:39 ` Alexey Baturo 0 siblings, 1 reply; 13+ messages in thread From: Alistair Francis @ 2024-11-25 4:01 UTC (permalink / raw) To: baturo.alexey Cc: richard.henderson, zhiwei_liu, dbarboza, liwei1518, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv On Thu, Nov 21, 2024 at 4:13 PM <baturo.alexey@gmail.com> wrote: > > From: Alexey Baturo <baturo.alexey@gmail.com> > > Zjpm extension is finally ratified. And it's much simplier compared to the experimental one. > The newer version doesn't allow to specify custom mask or base for pointer masking. > Instead it allows only certain options for masking top bits. > > Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> Wasn't this and part of this series previously reviewed? Alistair ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/7] target/riscv: Remove obsolete pointer masking extension code. 2024-11-25 4:01 ` Alistair Francis @ 2024-11-27 5:39 ` Alexey Baturo 0 siblings, 0 replies; 13+ messages in thread From: Alexey Baturo @ 2024-11-27 5:39 UTC (permalink / raw) To: Alistair Francis Cc: richard.henderson, zhiwei_liu, dbarboza, liwei1518, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv [-- Attachment #1: Type: text/plain, Size: 924 bytes --] Hi Alistair, You're right. Initially I thought it might be a good idea to do the whole process from scratch, but as @Daniel Henrique Barboza <dbarboza@ventanamicro.com> suggested I resubmitted the series with a proper version tag and added some reviewed-by. Sorry for the confusion. Thanks пн, 25 нояб. 2024 г. в 07:01, Alistair Francis <alistair23@gmail.com>: > On Thu, Nov 21, 2024 at 4:13 PM <baturo.alexey@gmail.com> wrote: > > > > From: Alexey Baturo <baturo.alexey@gmail.com> > > > > Zjpm extension is finally ratified. And it's much simplier compared to > the experimental one. > > The newer version doesn't allow to specify custom mask or base for > pointer masking. > > Instead it allows only certain options for masking top bits. > > > > Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> > > Wasn't this and part of this series previously reviewed? > > Alistair > [-- Attachment #2: Type: text/html, Size: 1621 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 2/7] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 2024-11-21 6:12 [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 baturo.alexey 2024-11-21 6:12 ` [PATCH v2 1/7] target/riscv: Remove obsolete pointer masking extension code baturo.alexey @ 2024-11-21 6:12 ` baturo.alexey 2024-11-21 6:12 ` [PATCH v2 3/7] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking baturo.alexey ` (5 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: baturo.alexey @ 2024-11-21 6:12 UTC (permalink / raw) Cc: baturo.alexey, richard.henderson, zhiwei_liu, dbarboza, liwei1518, alistair23, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv From: Alexey Baturo <baturo.alexey@gmail.com> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu_bits.h | 4 ++++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 31 ++++++++++++++++++++++++++++++- target/riscv/pmp.c | 14 +++++++++++--- target/riscv/pmp.h | 1 + 6 files changed, 57 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e11264231d..417ff45544 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -128,6 +128,14 @@ typedef enum { EXT_STATUS_DIRTY, } RISCVExtStatus; +/* Enum holds PMM field values for Zjpm v1.0 extension */ +typedef enum { + PMM_FIELD_DISABLED = 0, + PMM_FIELD_RESERVED = 1, + PMM_FIELD_PMLEN7 = 2, + PMM_FIELD_PMLEN16 = 3, +} RISCVPmPmm; + typedef struct riscv_cpu_implied_exts_rule { #ifndef CONFIG_USER_ONLY /* diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 2a6aff63ed..d8f9bc68e3 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -574,6 +574,7 @@ typedef enum { #define HSTATUS_VTW 0x00200000 #define HSTATUS_VTSR 0x00400000 #define HSTATUS_VSXL 0x300000000 +#define HSTATUS_HUPMM 0x3000000000000 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL @@ -734,6 +735,7 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_PMM (3ULL << 32) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -749,6 +751,7 @@ typedef enum RISCVException { #define SENVCFG_CBIE MENVCFG_CBIE #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE +#define SENVCFG_PMM MENVCFG_PMM #define HENVCFG_FIOM MENVCFG_FIOM #define HENVCFG_LPE MENVCFG_LPE @@ -756,6 +759,7 @@ typedef enum RISCVException { #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PMM MENVCFG_PMM #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 59d6fc445d..79a114eb07 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -128,6 +128,9 @@ struct RISCVCPUConfig { bool ext_ssaia; bool ext_sscofpmf; bool ext_smepmp; + bool ext_ssnpm; + bool ext_smnpm; + bool ext_smmpm; bool rvv_ta_all_1s; bool rvv_ma_all_1s; bool rvv_vl_half_avl; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 941c9691da..5389ccb983 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -575,6 +575,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, int csrno) if (riscv_cpu_cfg(env)->ext_zkr) { return RISCV_EXCP_NONE; } + if (riscv_cpu_cfg(env)->ext_smmpm) { + return RISCV_EXCP_NONE; + } return RISCV_EXCP_ILLEGAL_INST; } @@ -2379,6 +2382,12 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, if (env_archcpu(env)->cfg.ext_zicfiss) { mask |= MENVCFG_SSE; } + + /* Update PMM field only if the value is valid according to Zjpm v1.0 */ + if (env_archcpu(env)->cfg.ext_smnpm && + get_field(val, MENVCFG_PMM) != PMM_FIELD_RESERVED) { + mask |= MENVCFG_PMM; + } } env->menvcfg = (env->menvcfg & ~mask) | (val & mask); @@ -2425,6 +2434,12 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, { uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; RISCVException ret; + /* Update PMM field only if the value is valid according to Zjpm v1.0 */ + if (env_archcpu(env)->cfg.ext_ssnpm && + riscv_cpu_mxl(env) == MXL_RV64 && + get_field(val, SENVCFG_PMM) != PMM_FIELD_RESERVED) { + mask |= SENVCFG_PMM; + } ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); if (ret != RISCV_EXCP_NONE) { @@ -2489,6 +2504,12 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, get_field(env->menvcfg, MENVCFG_SSE)) { mask |= HENVCFG_SSE; } + + /* Update PMM field only if the value is valid according to Zjpm v1.0 */ + if (env_archcpu(env)->cfg.ext_ssnpm && + get_field(val, HENVCFG_PMM) != PMM_FIELD_RESERVED) { + mask |= HENVCFG_PMM; + } } env->henvcfg = (env->henvcfg & ~mask) | (val & mask); @@ -3525,7 +3546,15 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno, static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { - env->hstatus = val; + uint64_t mask = (target_ulong)-1; + /* Update PMM field only if the value is valid according to Zjpm v1.0 */ + if (!env_archcpu(env)->cfg.ext_ssnpm || + riscv_cpu_mxl(env) != MXL_RV64 || + get_field(val, HSTATUS_HUPMM) == PMM_FIELD_RESERVED) { + mask &= ~HSTATUS_HUPMM; + } + env->hstatus = (env->hstatus & ~mask) | (val & mask); + if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index a1b36664fc..a185c246d6 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -575,6 +575,13 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) void mseccfg_csr_write(CPURISCVState *env, target_ulong val) { int i; + uint64_t mask = MSECCFG_MMWP | MSECCFG_MML; + /* Update PMM field only if the value is valid according to Zjpm v1.0 */ + if (riscv_cpu_cfg(env)->ext_smmpm && + riscv_cpu_mxl(env) == MXL_RV64 && + get_field(val, MSECCFG_PMM) != PMM_FIELD_RESERVED) { + mask |= MSECCFG_PMM; + } trace_mseccfg_csr_write(env->mhartid, val); @@ -590,12 +597,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val) if (riscv_cpu_cfg(env)->ext_smepmp) { /* Sticky bits */ - val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); - if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { + val |= (env->mseccfg & mask); + if ((val ^ env->mseccfg) & mask) { tlb_flush(env_cpu(env)); } } else { - val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); + mask |= MSECCFG_RLB; + val &= ~(mask); } /* M-mode forward cfi to be enabled if cfi extension is implemented */ diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index e0530a17a3..271cf24169 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -46,6 +46,7 @@ typedef enum { MSECCFG_USEED = 1 << 8, MSECCFG_SSEED = 1 << 9, MSECCFG_MLPE = 1 << 10, + MSECCFG_PMM = 3ULL << 32, } mseccfg_field_t; typedef struct { -- 2.39.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/7] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking 2024-11-21 6:12 [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 baturo.alexey 2024-11-21 6:12 ` [PATCH v2 1/7] target/riscv: Remove obsolete pointer masking extension code baturo.alexey 2024-11-21 6:12 ` [PATCH v2 2/7] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 baturo.alexey @ 2024-11-21 6:12 ` baturo.alexey 2024-11-21 6:12 ` [PATCH v2 4/7] target/riscv: Add pointer masking tb flags baturo.alexey ` (4 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: baturo.alexey @ 2024-11-21 6:12 UTC (permalink / raw) Cc: baturo.alexey, richard.henderson, zhiwei_liu, dbarboza, liwei1518, alistair23, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv From: Alexey Baturo <baturo.alexey@gmail.com> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> --- target/riscv/cpu.h | 5 +++ target/riscv/cpu_helper.c | 74 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 417ff45544..74d7076f5a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -768,8 +768,13 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, bool riscv_cpu_is_32bit(RISCVCPU *cpu); +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); +int riscv_pm_get_pmlen(RISCVPmPmm pmm); + RISCVException riscv_csrr(CPURISCVState *env, int csrno, target_ulong *ret_value); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 696a17461b..da2a10384a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -214,6 +214,80 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, *pflags = flags; } +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) +{ + RISCVPmPmm pmm = PMM_FIELD_DISABLED; +#ifndef CONFIG_USER_ONLY + if (get_field(env->mstatus, MSTATUS_MPRV) && + get_field(env->mstatus, MSTATUS_MXR)) { + return pmm; + } + int priv_mode = cpu_address_mode(env); + /* Get current PMM field */ + switch (priv_mode) { + case PRV_M: + if (riscv_cpu_cfg(env)->ext_smmpm) { + pmm = get_field(env->mseccfg, MSECCFG_PMM); + } + break; + case PRV_S: + if (riscv_cpu_cfg(env)->ext_smnpm) { + if (get_field(env->mstatus, MSTATUS_MPV)) { + pmm = get_field(env->henvcfg, HENVCFG_PMM); + } else { + pmm = get_field(env->menvcfg, MENVCFG_PMM); + } + } + break; + case PRV_U: + if (riscv_has_ext(env, RVS)) { + if (riscv_cpu_cfg(env)->ext_ssnpm) { + pmm = get_field(env->senvcfg, SENVCFG_PMM); + } + } else { + if (riscv_cpu_cfg(env)->ext_smnpm) { + pmm = get_field(env->menvcfg, MENVCFG_PMM); + } + } + break; + default: + g_assert_not_reached(); + } +#endif + return pmm; +} + +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) +{ + bool virt_mem_en = false; +#ifndef CONFIG_USER_ONLY + int satp_mode = 0; + int priv_mode = cpu_address_mode(env); + if (riscv_cpu_mxl(env) == MXL_RV32) { + satp_mode = get_field(env->satp, SATP32_MODE); + } else { + satp_mode = get_field(env->satp, SATP64_MODE); + } + virt_mem_en = ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M)); +#endif + return virt_mem_en; +} + +int riscv_pm_get_pmlen(RISCVPmPmm pmm) +{ + switch (pmm) { + case PMM_FIELD_DISABLED: + return 0; + case PMM_FIELD_PMLEN7: + return 7; + case PMM_FIELD_PMLEN16: + return 16; + default: + g_assert_not_reached(); + } + return -1; +} + #ifndef CONFIG_USER_ONLY /* -- 2.39.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 4/7] target/riscv: Add pointer masking tb flags 2024-11-21 6:12 [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 baturo.alexey ` (2 preceding siblings ...) 2024-11-21 6:12 ` [PATCH v2 3/7] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking baturo.alexey @ 2024-11-21 6:12 ` baturo.alexey 2024-11-21 6:12 ` [PATCH v2 5/7] target/riscv: Update address modify functions to take into account pointer masking baturo.alexey ` (3 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: baturo.alexey @ 2024-11-21 6:12 UTC (permalink / raw) Cc: baturo.alexey, richard.henderson, zhiwei_liu, dbarboza, liwei1518, alistair23, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv From: Alexey Baturo <baturo.alexey@gmail.com> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> --- target/riscv/cpu.h | 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 +++++ 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 74d7076f5a..11e3a6d647 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -631,6 +631,9 @@ FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1) FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1) /* zicfiss needs a TB flag so that correct TB is located based on tb flags */ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) +/* If pointer masking should be applied and address sign extended */ +FIELD(TB_FLAGS, PM_PMM, 29, 2) +FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index da2a10384a..78b461a5cf 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -126,6 +126,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, RISCVCPU *cpu = env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags = 0; + bool pm_signext = riscv_cpu_virt_mem_enabled(env); *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base = 0; @@ -210,6 +211,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); *pflags = flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 018be5504f..bb92f36ba1 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -102,6 +102,9 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; + /* actual address width */ + uint8_t addr_xl; + bool addr_signed; /* Ztso */ bool ztso; /* Use icount trigger for native debug */ @@ -1230,6 +1233,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs = cs; + ctx->addr_xl = 0; + ctx->addr_signed = false; ctx->ztso = cpu->cfg.ext_ztso; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); -- 2.39.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 5/7] target/riscv: Update address modify functions to take into account pointer masking 2024-11-21 6:12 [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 baturo.alexey ` (3 preceding siblings ...) 2024-11-21 6:12 ` [PATCH v2 4/7] target/riscv: Add pointer masking tb flags baturo.alexey @ 2024-11-21 6:12 ` baturo.alexey 2024-11-21 6:12 ` [PATCH v2 6/7] target/riscv: Apply pointer masking for virtualized memory accesses baturo.alexey ` (2 subsequent siblings) 7 siblings, 0 replies; 13+ messages in thread From: baturo.alexey @ 2024-11-21 6:12 UTC (permalink / raw) Cc: baturo.alexey, richard.henderson, zhiwei_liu, dbarboza, liwei1518, alistair23, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv From: Alexey Baturo <baturo.alexey@gmail.com> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> --- target/riscv/translate.c | 22 ++++++++++++++++------ target/riscv/vector_helper.c | 16 ++++++++++++++++ 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index bb92f36ba1..32df295123 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -588,8 +588,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); tcg_gen_addi_tl(addr, src1, imm); - if (get_address_xl(ctx) == MXL_RV32) { - tcg_gen_ext32u_tl(addr, addr); + if (ctx->addr_signed) { + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl); + } else { + tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl); } return addr; @@ -602,8 +604,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); tcg_gen_add_tl(addr, src1, offs); - if (get_xl(ctx) == MXL_RV32) { - tcg_gen_ext32u_tl(addr, addr); + if (ctx->addr_signed) { + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl); + } else { + tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl); } return addr; @@ -1233,8 +1237,14 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs = cs; - ctx->addr_xl = 0; - ctx->addr_signed = false; + if (get_xl(ctx) == MXL_RV32) { + ctx->addr_xl = 32; + ctx->addr_signed = false; + } else { + int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM); + ctx->addr_xl = 64 - riscv_pm_get_pmlen(pm_pmm); + ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); + } ctx->ztso = cpu->cfg.ext_ztso; ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 3589e3ef28..37c6c198a5 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -107,6 +107,22 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz) static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) { + if (riscv_cpu_mxl(env) == MXL_RV32) { + return addr; + } + RISCVPmPmm pmm = riscv_pm_get_pmm(env); + if (pmm == PMM_FIELD_DISABLED) { + return addr; + } + int pmlen = riscv_pm_get_pmlen(pmm); + bool signext = riscv_cpu_virt_mem_enabled(env); + addr = addr << pmlen; + /* sign/zero extend masked address by N-1 bit */ + if (signext) { + addr = (target_long)addr >> pmlen; + } else { + addr = addr >> pmlen; + } return addr; } -- 2.39.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 6/7] target/riscv: Apply pointer masking for virtualized memory accesses 2024-11-21 6:12 [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 baturo.alexey ` (4 preceding siblings ...) 2024-11-21 6:12 ` [PATCH v2 5/7] target/riscv: Update address modify functions to take into account pointer masking baturo.alexey @ 2024-11-21 6:12 ` baturo.alexey 2024-11-21 6:12 ` [PATCH v2 7/7] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension baturo.alexey 2024-11-25 13:37 ` [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 Daniel Henrique Barboza 7 siblings, 0 replies; 13+ messages in thread From: baturo.alexey @ 2024-11-21 6:12 UTC (permalink / raw) Cc: baturo.alexey, richard.henderson, zhiwei_liu, dbarboza, liwei1518, alistair23, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv From: Alexey Baturo <baturo.alexey@gmail.com> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 19 +++++++++++++++++++ target/riscv/insn_trans/trans_rvh.c.inc | 11 +++++++++++ target/riscv/translate.c | 4 ++++ 4 files changed, 36 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 11e3a6d647..6bbd9c6c25 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -634,6 +634,7 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) /* If pointer masking should be applied and address sign extended */ FIELD(TB_FLAGS, PM_PMM, 29, 2) FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) +FIELD(TB_FLAGS, PM_VPMM, 32, 2) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) @@ -773,6 +774,7 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu); bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env); int riscv_pm_get_pmlen(RISCVPmPmm pmm); RISCVException riscv_csrr(CPURISCVState *env, int csrno, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 78b461a5cf..4065809d9f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -213,6 +213,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); + flags = FIELD_DP64(flags, TB_FLAGS, PM_VPMM, riscv_pm_get_virt_pmm(env)); *pflags = flags; } @@ -260,6 +261,24 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) return pmm; } +RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env) +{ + RISCVPmPmm pmm = PMM_FIELD_DISABLED; +#ifndef CONFIG_USER_ONLY + int priv_mode = cpu_address_mode(env); + if (priv_mode == PRV_U) { + pmm = get_field(env->hstatus, HSTATUS_HUPMM); + } else { + if (get_field(env->hstatus, HSTATUS_SPVP)) { + pmm = get_field(env->henvcfg, HENVCFG_PMM); + } else { + pmm = get_field(env->senvcfg, SENVCFG_PMM); + } + } +#endif + return pmm; +} + bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) { bool virt_mem_en = false; diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index 03c6694430..ae067789d1 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -44,6 +44,14 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, TCGv dest = dest_gpr(ctx, a->rd); TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); + bool is_hlvx = (func == gen_helper_hyp_hlvx_hu) || + (func == gen_helper_hyp_hlvx_wu); + + /* Apply Zjpm pointer masking */ + if (!is_hlvx) { + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_vxl); + } + decode_save_opc(ctx, 0); func(dest, tcg_env, addr); gen_set_gpr(ctx, a->rd, dest); @@ -56,6 +64,9 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); + /* Apply Zjpm pointer masking */ + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_vxl); + decode_save_opc(ctx, 0); func(tcg_env, addr, data); return true; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 32df295123..d8f83315c6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -104,6 +104,7 @@ typedef struct DisasContext { TCGv zero; /* actual address width */ uint8_t addr_xl; + uint8_t addr_vxl; bool addr_signed; /* Ztso */ bool ztso; @@ -1239,10 +1240,13 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cs = cs; if (get_xl(ctx) == MXL_RV32) { ctx->addr_xl = 32; + ctx->addr_vxl = 32; ctx->addr_signed = false; } else { int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM); ctx->addr_xl = 64 - riscv_pm_get_pmlen(pm_pmm); + int pm_vpmm = FIELD_EX64(tb_flags, TB_FLAGS, PM_VPMM); + ctx->addr_vxl = 64 - riscv_pm_get_pmlen(pm_vpmm); ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); } ctx->ztso = cpu->cfg.ext_ztso; -- 2.39.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 7/7] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension 2024-11-21 6:12 [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 baturo.alexey ` (5 preceding siblings ...) 2024-11-21 6:12 ` [PATCH v2 6/7] target/riscv: Apply pointer masking for virtualized memory accesses baturo.alexey @ 2024-11-21 6:12 ` baturo.alexey 2024-11-25 13:37 ` [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 Daniel Henrique Barboza 7 siblings, 0 replies; 13+ messages in thread From: baturo.alexey @ 2024-11-21 6:12 UTC (permalink / raw) Cc: baturo.alexey, richard.henderson, zhiwei_liu, dbarboza, liwei1518, alistair23, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv From: Alexey Baturo <baturo.alexey@gmail.com> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com> --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e80dcd2e6..fd3ea9ce76 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -186,11 +186,14 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), + ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm), + ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -1490,9 +1493,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false), MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), + MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), + MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false), + MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), MULTI_EXT_CFG_BOOL("svade", ext_svade, false), -- 2.39.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 2024-11-21 6:12 [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 baturo.alexey ` (6 preceding siblings ...) 2024-11-21 6:12 ` [PATCH v2 7/7] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension baturo.alexey @ 2024-11-25 13:37 ` Daniel Henrique Barboza 2024-11-27 5:38 ` Alexey Baturo 7 siblings, 1 reply; 13+ messages in thread From: Daniel Henrique Barboza @ 2024-11-25 13:37 UTC (permalink / raw) To: baturo.alexey Cc: richard.henderson, zhiwei_liu, liwei1518, alistair23, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv Hi Alexey, I believe this is not the second version of this work. When I asked about the next versions this was already in v9: https://lore.kernel.org/qemu-riscv/d4241c7b-ae97-4dc1-bc60-5f0eed58d3a5@ventanamicro.com/ And it had most of the patches already reviewed by Alistair and Richard. So this would be in fact v11, with a lot of patches already reviewed. If you could re-send this series as v11, keeping reviewed-by tags from code that you didn't change from one version to the other, the review will go faster. Thanks, Daniel On 11/21/24 3:12 AM, baturo.alexey@gmail.com wrote: > From: Alexey Baturo <baturo.alexey@gmail.com> > > Hi, > > I've rebased this patch series and addressed Richard's and Daniel's comments. > Thanks > > *** BLURB HERE *** > [v0]: > As Pointer Masking is finally ratified, these patches intend to update the existing code to the final version. > These patches have been submitted previously and I tried to address all the suggestions, but I'd suggest to review them from the clean slate and then finally push them to the repo. > Thanks. > > Alexey Baturo (7): > target/riscv: Remove obsolete pointer masking extension code. > target/riscv: Add new CSR fields for S{sn,mn,m}pm extensions as part > of Zjpm v1.0 > target/riscv: Add helper functions to calculate current number of > masked bits for pointer masking > target/riscv: Add pointer masking tb flags > target/riscv: Update address modify functions to take into account > pointer masking > target/riscv: Apply pointer masking for virtualized memory accesses > target/riscv: Enable updates for pointer masking variables and thus > enable pointer masking extension > > target/riscv/cpu.c | 19 +- > target/riscv/cpu.h | 51 ++-- > target/riscv/cpu_bits.h | 91 +----- > target/riscv/cpu_cfg.h | 3 + > target/riscv/cpu_helper.c | 124 +++++--- > target/riscv/csr.c | 357 ++---------------------- > target/riscv/insn_trans/trans_rvh.c.inc | 11 + > target/riscv/machine.c | 17 +- > target/riscv/pmp.c | 14 +- > target/riscv/pmp.h | 1 + > target/riscv/tcg/tcg-cpu.c | 5 +- > target/riscv/translate.c | 51 ++-- > target/riscv/vector_helper.c | 18 +- > 13 files changed, 224 insertions(+), 538 deletions(-) > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 2024-11-25 13:37 ` [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 Daniel Henrique Barboza @ 2024-11-27 5:38 ` Alexey Baturo 2024-11-28 0:45 ` Alistair Francis 0 siblings, 1 reply; 13+ messages in thread From: Alexey Baturo @ 2024-11-27 5:38 UTC (permalink / raw) To: Daniel Henrique Barboza Cc: richard.henderson, zhiwei_liu, liwei1518, alistair23, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv [-- Attachment #1: Type: text/plain, Size: 2905 bytes --] Hi Daniel, Thanks for the suggestion. I've resubmitted it with the v11 tag and put some reviewed-bys. Thanks пн, 25 нояб. 2024 г. в 16:37, Daniel Henrique Barboza < dbarboza@ventanamicro.com>: > Hi Alexey, > > > I believe this is not the second version of this work. When I asked about > the > next versions this was already in v9: > > > https://lore.kernel.org/qemu-riscv/d4241c7b-ae97-4dc1-bc60-5f0eed58d3a5@ventanamicro.com/ > > And it had most of the patches already reviewed by Alistair and Richard. > So this > would be in fact v11, with a lot of patches already reviewed. > > If you could re-send this series as v11, keeping reviewed-by tags from > code that you > didn't change from one version to the other, the review will go faster. > > > Thanks, > > Daniel > > On 11/21/24 3:12 AM, baturo.alexey@gmail.com wrote: > > From: Alexey Baturo <baturo.alexey@gmail.com> > > > > Hi, > > > > I've rebased this patch series and addressed Richard's and Daniel's > comments. > > Thanks > > > > *** BLURB HERE *** > > [v0]: > > As Pointer Masking is finally ratified, these patches intend to update > the existing code to the final version. > > These patches have been submitted previously and I tried to address all > the suggestions, but I'd suggest to review them from the clean slate and > then finally push them to the repo. > > Thanks. > > > > Alexey Baturo (7): > > target/riscv: Remove obsolete pointer masking extension code. > > target/riscv: Add new CSR fields for S{sn,mn,m}pm extensions as part > > of Zjpm v1.0 > > target/riscv: Add helper functions to calculate current number of > > masked bits for pointer masking > > target/riscv: Add pointer masking tb flags > > target/riscv: Update address modify functions to take into account > > pointer masking > > target/riscv: Apply pointer masking for virtualized memory accesses > > target/riscv: Enable updates for pointer masking variables and thus > > enable pointer masking extension > > > > target/riscv/cpu.c | 19 +- > > target/riscv/cpu.h | 51 ++-- > > target/riscv/cpu_bits.h | 91 +----- > > target/riscv/cpu_cfg.h | 3 + > > target/riscv/cpu_helper.c | 124 +++++--- > > target/riscv/csr.c | 357 ++---------------------- > > target/riscv/insn_trans/trans_rvh.c.inc | 11 + > > target/riscv/machine.c | 17 +- > > target/riscv/pmp.c | 14 +- > > target/riscv/pmp.h | 1 + > > target/riscv/tcg/tcg-cpu.c | 5 +- > > target/riscv/translate.c | 51 ++-- > > target/riscv/vector_helper.c | 18 +- > > 13 files changed, 224 insertions(+), 538 deletions(-) > > > > [-- Attachment #2: Type: text/html, Size: 3953 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 2024-11-27 5:38 ` Alexey Baturo @ 2024-11-28 0:45 ` Alistair Francis 0 siblings, 0 replies; 13+ messages in thread From: Alistair Francis @ 2024-11-28 0:45 UTC (permalink / raw) To: Alexey Baturo Cc: Daniel Henrique Barboza, richard.henderson, zhiwei_liu, liwei1518, frank.chang, palmer, Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv On Wed, Nov 27, 2024 at 3:38 PM Alexey Baturo <baturo.alexey@gmail.com> wrote: > > Hi Daniel, > > Thanks for the suggestion. I've resubmitted it with the v11 tag and put some reviewed-bys. Thanks! It's a lot of time and effort to review code, so it's helpful to keep existing tags. Note that it's fine (and you should) to remove tags if the code has changed Alistair ^ permalink raw reply [flat|nested] 13+ messages in thread
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2024-11-21 6:12 [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 baturo.alexey
2024-11-21 6:12 ` [PATCH v2 1/7] target/riscv: Remove obsolete pointer masking extension code baturo.alexey
2024-11-25 4:01 ` Alistair Francis
2024-11-27 5:39 ` Alexey Baturo
2024-11-21 6:12 ` [PATCH v2 2/7] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 baturo.alexey
2024-11-21 6:12 ` [PATCH v2 3/7] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking baturo.alexey
2024-11-21 6:12 ` [PATCH v2 4/7] target/riscv: Add pointer masking tb flags baturo.alexey
2024-11-21 6:12 ` [PATCH v2 5/7] target/riscv: Update address modify functions to take into account pointer masking baturo.alexey
2024-11-21 6:12 ` [PATCH v2 6/7] target/riscv: Apply pointer masking for virtualized memory accesses baturo.alexey
2024-11-21 6:12 ` [PATCH v2 7/7] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension baturo.alexey
2024-11-25 13:37 ` [PATCH v2 0/7] Pointer Masking update for Zjpm v1.0 Daniel Henrique Barboza
2024-11-27 5:38 ` Alexey Baturo
2024-11-28 0:45 ` Alistair Francis
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