* [PATCH 01/67] target/arm: Use ### to separate 3rd-level sections in a64.decode
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 14:12 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 02/67] target/arm: Convert UDIV, SDIV to decodetree Richard Henderson
` (66 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
We already use ### for 4.1.92 Data Processing (immediate),
but not the two following two third-level sections:
4.1.93 Branches, and 4.1.94 Loads and stores.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/a64.decode | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 331a8e180c..197437ba8e 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -161,7 +161,7 @@ UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32
EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1
EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0
-# Branches
+### Branches
%imm26 0:s26 !function=times_4
@branch . ..... .......................... &i imm=%imm26
@@ -291,7 +291,7 @@ HLT 1101 0100 010 ................ 000 00 @i16
# DCPS2 1101 0100 101 ................ 000 10 @i16
# DCPS3 1101 0100 101 ................ 000 11 @i16
-# Loads and stores
+### Loads and stores
&stxr rn rt rt2 rs sz lasr
&stlr rn rt sz lasr
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 01/67] target/arm: Use ### to separate 3rd-level sections in a64.decode
2024-12-01 15:05 ` [PATCH 01/67] target/arm: Use ### to separate 3rd-level sections in a64.decode Richard Henderson
@ 2024-12-02 14:12 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 147+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-12-02 14:12 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 1/12/24 16:05, Richard Henderson wrote:
> We already use ### for 4.1.92 Data Processing (immediate),
> but not the two following two third-level sections:
> 4.1.93 Branches, and 4.1.94 Loads and stores.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/a64.decode | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index 331a8e180c..197437ba8e 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -161,7 +161,7 @@ UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32
> EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1
> EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0
>
> -# Branches
> +### Branches
>
> %imm26 0:s26 !function=times_4
> @branch . ..... .......................... &i imm=%imm26
> @@ -291,7 +291,7 @@ HLT 1101 0100 010 ................ 000 00 @i16
> # DCPS2 1101 0100 101 ................ 000 10 @i16
> # DCPS3 1101 0100 101 ................ 000 11 @i16
>
> -# Loads and stores
> +### Loads and stores
>
> &stxr rn rt rt2 rs sz lasr
> &stlr rn rt sz lasr
I'd include in this patch (from next one):
+### Data Processing (register)
+
+# Data Processing (2-source)
+# Data Processing (1-source)
+# Logical (shifted reg)
+# Add/subtract (shifted reg)
+# Add/subtract (extended reg)
+# Add/subtract (carry)
+# Rotate right into flags
+# Evaluate into flags
+# Conditional compare (regster)
+# Conditional compare (immediate)
+# Conditional select
+# Data Processing (3-source)
Because it looks (to me) out of context in in the next one.
Anyway,
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 02/67] target/arm: Convert UDIV, SDIV to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
2024-12-01 15:05 ` [PATCH 01/67] target/arm: Use ### to separate 3rd-level sections in a64.decode Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 13:49 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 03/67] target/arm: Convert LSLV, LSRV, ASRV, RORV " Richard Henderson
` (65 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 64 +++++++++++++++++-----------------
target/arm/tcg/a64.decode | 22 ++++++++++++
2 files changed, 54 insertions(+), 32 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index b2851ea503..9f687ba840 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7485,6 +7485,36 @@ TRANS(UQRSHRN_si, do_scalar_shift_imm_narrow, a, uqrshrn_fns, 0, false)
TRANS(SQSHRUN_si, do_scalar_shift_imm_narrow, a, sqshrun_fns, MO_SIGN, false)
TRANS(SQRSHRUN_si, do_scalar_shift_imm_narrow, a, sqrshrun_fns, MO_SIGN, false)
+static bool do_div(DisasContext *s, arg_rrr_sf *a, bool is_signed)
+{
+ TCGv_i64 tcg_n, tcg_m, tcg_rd;
+ tcg_rd = cpu_reg(s, a->rd);
+
+ if (!a->sf && is_signed) {
+ tcg_n = tcg_temp_new_i64();
+ tcg_m = tcg_temp_new_i64();
+ tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, a->rn));
+ tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, a->rm));
+ } else {
+ tcg_n = read_cpu_reg(s, a->rn, a->sf);
+ tcg_m = read_cpu_reg(s, a->rm, a->sf);
+ }
+
+ if (is_signed) {
+ gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m);
+ } else {
+ gen_helper_udiv64(tcg_rd, tcg_n, tcg_m);
+ }
+
+ if (!a->sf) { /* zero extend final result */
+ tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+ }
+ return true;
+}
+
+TRANS(SDIV, do_div, a, true)
+TRANS(UDIV, do_div, a, false)
+
/* Shift a TCGv src by TCGv shift_amount, put result in dst.
* Note that it is the caller's responsibility to ensure that the
* shift amount is in range (ie 0..31 or 0..63) and provide the ARM
@@ -8425,32 +8455,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
#undef MAP
}
-static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
- unsigned int rm, unsigned int rn, unsigned int rd)
-{
- TCGv_i64 tcg_n, tcg_m, tcg_rd;
- tcg_rd = cpu_reg(s, rd);
-
- if (!sf && is_signed) {
- tcg_n = tcg_temp_new_i64();
- tcg_m = tcg_temp_new_i64();
- tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn));
- tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm));
- } else {
- tcg_n = read_cpu_reg(s, rn, sf);
- tcg_m = read_cpu_reg(s, rm, sf);
- }
-
- if (is_signed) {
- gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m);
- } else {
- gen_helper_udiv64(tcg_rd, tcg_n, tcg_m);
- }
-
- if (!sf) { /* zero extend final result */
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
- }
-}
/* LSLV, LSRV, ASRV, RORV */
static void handle_shift_reg(DisasContext *s,
@@ -8552,12 +8556,6 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
}
}
break;
- case 2: /* UDIV */
- handle_div(s, false, sf, rm, rn, rd);
- break;
- case 3: /* SDIV */
- handle_div(s, true, sf, rm, rn, rd);
- break;
case 4: /* IRG */
if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
goto do_unallocated;
@@ -8616,6 +8614,8 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
}
default:
do_unallocated:
+ case 2: /* UDIV */
+ case 3: /* SDIV */
unallocated_encoding(s);
break;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 197437ba8e..c218f6afbc 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -28,6 +28,7 @@
&r rn
&ri rd imm
&rri_sf rd rn imm sf
+&rrr_sf rd rn rm sf
&i imm
&rr_e rd rn esz
&rri_e rd rn imm esz
@@ -649,6 +650,27 @@ CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy
CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy
CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy
+### Data Processing (register)
+
+# Data Processing (2-source)
+
+@rrr_sf sf:1 .......... rm:5 ...... rn:5 rd:5 &rrr_sf
+
+UDIV . 00 11010110 ..... 00001 0 ..... ..... @rrr_sf
+SDIV . 00 11010110 ..... 00001 1 ..... ..... @rrr_sf
+
+# Data Processing (1-source)
+# Logical (shifted reg)
+# Add/subtract (shifted reg)
+# Add/subtract (extended reg)
+# Add/subtract (carry)
+# Rotate right into flags
+# Evaluate into flags
+# Conditional compare (regster)
+# Conditional compare (immediate)
+# Conditional select
+# Data Processing (3-source)
+
### Cryptographic AES
AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 03/67] target/arm: Convert LSLV, LSRV, ASRV, RORV to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
2024-12-01 15:05 ` [PATCH 01/67] target/arm: Use ### to separate 3rd-level sections in a64.decode Richard Henderson
2024-12-01 15:05 ` [PATCH 02/67] target/arm: Convert UDIV, SDIV to decodetree Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 19:31 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 04/67] target/arm: Convert CRC32, CRC32C " Richard Henderson
` (64 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 46 ++++++++++++++++------------------
target/arm/tcg/a64.decode | 4 +++
2 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 9f687ba840..8b7ca2c68a 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7575,6 +7575,23 @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
}
}
+static bool do_shift_reg(DisasContext *s, arg_rrr_sf *a,
+ enum a64_shift_type shift_type)
+{
+ TCGv_i64 tcg_shift = tcg_temp_new_i64();
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ TCGv_i64 tcg_rn = read_cpu_reg(s, a->rn, a->sf);
+
+ tcg_gen_andi_i64(tcg_shift, cpu_reg(s, a->rm), a->sf ? 63 : 31);
+ shift_reg(tcg_rd, tcg_rn, a->sf, shift_type, tcg_shift);
+ return true;
+}
+
+TRANS(LSLV, do_shift_reg, a, A64_SHIFT_TYPE_LSL)
+TRANS(LSRV, do_shift_reg, a, A64_SHIFT_TYPE_LSR)
+TRANS(ASRV, do_shift_reg, a, A64_SHIFT_TYPE_ASR)
+TRANS(RORV, do_shift_reg, a, A64_SHIFT_TYPE_ROR)
+
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@@ -8456,19 +8473,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
}
-/* LSLV, LSRV, ASRV, RORV */
-static void handle_shift_reg(DisasContext *s,
- enum a64_shift_type shift_type, unsigned int sf,
- unsigned int rm, unsigned int rn, unsigned int rd)
-{
- TCGv_i64 tcg_shift = tcg_temp_new_i64();
- TCGv_i64 tcg_rd = cpu_reg(s, rd);
- TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
-
- tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31);
- shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift);
-}
-
/* CRC32[BHWX], CRC32C[BHWX] */
static void handle_crc32(DisasContext *s,
unsigned int sf, unsigned int sz, bool crc32c,
@@ -8579,18 +8583,6 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t);
}
break;
- case 8: /* LSLV */
- handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
- break;
- case 9: /* LSRV */
- handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd);
- break;
- case 10: /* ASRV */
- handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd);
- break;
- case 11: /* RORV */
- handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd);
- break;
case 12: /* PACGA */
if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
@@ -8616,6 +8608,10 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
do_unallocated:
case 2: /* UDIV */
case 3: /* SDIV */
+ case 8: /* LSLV */
+ case 9: /* LSRV */
+ case 10: /* ASRV */
+ case 11: /* RORV */
unallocated_encoding(s);
break;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index c218f6afbc..3db55b78a6 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -658,6 +658,10 @@ CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy
UDIV . 00 11010110 ..... 00001 0 ..... ..... @rrr_sf
SDIV . 00 11010110 ..... 00001 1 ..... ..... @rrr_sf
+LSLV . 00 11010110 ..... 00100 0 ..... ..... @rrr_sf
+LSRV . 00 11010110 ..... 00100 1 ..... ..... @rrr_sf
+ASRV . 00 11010110 ..... 00101 0 ..... ..... @rrr_sf
+RORV . 00 11010110 ..... 00101 1 ..... ..... @rrr_sf
# Data Processing (1-source)
# Logical (shifted reg)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 03/67] target/arm: Convert LSLV, LSRV, ASRV, RORV to decodetree
2024-12-01 15:05 ` [PATCH 03/67] target/arm: Convert LSLV, LSRV, ASRV, RORV " Richard Henderson
@ 2024-12-02 19:31 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 147+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-12-02 19:31 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 1/12/24 16:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 46 ++++++++++++++++------------------
> target/arm/tcg/a64.decode | 4 +++
> 2 files changed, 25 insertions(+), 25 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 04/67] target/arm: Convert CRC32, CRC32C to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (2 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 03/67] target/arm: Convert LSLV, LSRV, ASRV, RORV " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 14:01 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 05/67] target/arm: Convert SUBP, IRG, GMI " Richard Henderson
` (63 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 101 +++++++++++++--------------------
target/arm/tcg/a64.decode | 12 ++++
2 files changed, 53 insertions(+), 60 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 8b7ca2c68a..22594a1149 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7592,6 +7592,39 @@ TRANS(LSRV, do_shift_reg, a, A64_SHIFT_TYPE_LSR)
TRANS(ASRV, do_shift_reg, a, A64_SHIFT_TYPE_ASR)
TRANS(RORV, do_shift_reg, a, A64_SHIFT_TYPE_ROR)
+static bool do_crc32(DisasContext *s, arg_rrr_e *a, bool crc32c)
+{
+ TCGv_i64 tcg_acc, tcg_val, tcg_rd;
+ TCGv_i32 tcg_bytes;
+
+ switch (a->esz) {
+ case MO_8:
+ case MO_16:
+ case MO_32:
+ tcg_val = tcg_temp_new_i64();
+ tcg_gen_extract_i64(tcg_val, cpu_reg(s, a->rm), 0, 8 << a->esz);
+ break;
+ case MO_64:
+ tcg_val = cpu_reg(s, a->rm);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_acc = cpu_reg(s, a->rn);
+ tcg_bytes = tcg_constant_i32(1 << a->esz);
+ tcg_rd = cpu_reg(s, a->rd);
+
+ if (crc32c) {
+ gen_helper_crc32c_64(tcg_rd, tcg_acc, tcg_val, tcg_bytes);
+ } else {
+ gen_helper_crc32_64(tcg_rd, tcg_acc, tcg_val, tcg_bytes);
+ }
+ return true;
+}
+
+TRANS_FEAT(CRC32, aa64_crc32, do_crc32, a, false)
+TRANS_FEAT(CRC32C, aa64_crc32, do_crc32, a, true)
+
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@@ -8473,52 +8506,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
}
-/* CRC32[BHWX], CRC32C[BHWX] */
-static void handle_crc32(DisasContext *s,
- unsigned int sf, unsigned int sz, bool crc32c,
- unsigned int rm, unsigned int rn, unsigned int rd)
-{
- TCGv_i64 tcg_acc, tcg_val;
- TCGv_i32 tcg_bytes;
-
- if (!dc_isar_feature(aa64_crc32, s)
- || (sf == 1 && sz != 3)
- || (sf == 0 && sz == 3)) {
- unallocated_encoding(s);
- return;
- }
-
- if (sz == 3) {
- tcg_val = cpu_reg(s, rm);
- } else {
- uint64_t mask;
- switch (sz) {
- case 0:
- mask = 0xFF;
- break;
- case 1:
- mask = 0xFFFF;
- break;
- case 2:
- mask = 0xFFFFFFFF;
- break;
- default:
- g_assert_not_reached();
- }
- tcg_val = tcg_temp_new_i64();
- tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask);
- }
-
- tcg_acc = cpu_reg(s, rn);
- tcg_bytes = tcg_constant_i32(1 << sz);
-
- if (crc32c) {
- gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
- } else {
- gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
- }
-}
-
/* Data-processing (2 source)
* 31 30 29 28 21 20 16 15 10 9 5 4 0
* +----+---+---+-----------------+------+--------+------+------+
@@ -8590,20 +8577,6 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
gen_helper_pacga(cpu_reg(s, rd), tcg_env,
cpu_reg(s, rn), cpu_reg_sp(s, rm));
break;
- case 16:
- case 17:
- case 18:
- case 19:
- case 20:
- case 21:
- case 22:
- case 23: /* CRC32 */
- {
- int sz = extract32(opcode, 0, 2);
- bool crc32c = extract32(opcode, 2, 1);
- handle_crc32(s, sf, sz, crc32c, rm, rn, rd);
- break;
- }
default:
do_unallocated:
case 2: /* UDIV */
@@ -8612,6 +8585,14 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
case 9: /* LSRV */
case 10: /* ASRV */
case 11: /* RORV */
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 20:
+ case 21:
+ case 22:
+ case 23: /* CRC32 */
unallocated_encoding(s);
break;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 3db55b78a6..1664f4793c 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -45,7 +45,9 @@
@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
+@rrr_b ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=0
@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1
+@rrr_s ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=2
@rrr_d ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3
@rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd
@rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd
@@ -663,6 +665,16 @@ LSRV . 00 11010110 ..... 00100 1 ..... ..... @rrr_sf
ASRV . 00 11010110 ..... 00101 0 ..... ..... @rrr_sf
RORV . 00 11010110 ..... 00101 1 ..... ..... @rrr_sf
+CRC32 0 00 11010110 ..... 0100 00 ..... ..... @rrr_b
+CRC32 0 00 11010110 ..... 0100 01 ..... ..... @rrr_h
+CRC32 0 00 11010110 ..... 0100 10 ..... ..... @rrr_s
+CRC32 1 00 11010110 ..... 0100 11 ..... ..... @rrr_d
+
+CRC32C 0 00 11010110 ..... 0101 00 ..... ..... @rrr_b
+CRC32C 0 00 11010110 ..... 0101 01 ..... ..... @rrr_h
+CRC32C 0 00 11010110 ..... 0101 10 ..... ..... @rrr_s
+CRC32C 1 00 11010110 ..... 0101 11 ..... ..... @rrr_d
+
# Data Processing (1-source)
# Logical (shifted reg)
# Add/subtract (shifted reg)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 04/67] target/arm: Convert CRC32, CRC32C to decodetree
2024-12-01 15:05 ` [PATCH 04/67] target/arm: Convert CRC32, CRC32C " Richard Henderson
@ 2024-12-02 14:01 ` Philippe Mathieu-Daudé
2024-12-02 17:49 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-12-02 14:01 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
Hi Richard,
On 1/12/24 16:05, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 101 +++++++++++++--------------------
> target/arm/tcg/a64.decode | 12 ++++
> 2 files changed, 53 insertions(+), 60 deletions(-)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 8b7ca2c68a..22594a1149 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -7592,6 +7592,39 @@ TRANS(LSRV, do_shift_reg, a, A64_SHIFT_TYPE_LSR)
> TRANS(ASRV, do_shift_reg, a, A64_SHIFT_TYPE_ASR)
> TRANS(RORV, do_shift_reg, a, A64_SHIFT_TYPE_ROR)
>
> +static bool do_crc32(DisasContext *s, arg_rrr_e *a, bool crc32c)
> +{
> + TCGv_i64 tcg_acc, tcg_val, tcg_rd;
> + TCGv_i32 tcg_bytes;
> +
> + switch (a->esz) {
> + case MO_8:
> + case MO_16:
> + case MO_32:
> + tcg_val = tcg_temp_new_i64();
> + tcg_gen_extract_i64(tcg_val, cpu_reg(s, a->rm), 0, 8 << a->esz);
> + break;
> + case MO_64:
> + tcg_val = cpu_reg(s, a->rm);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + tcg_acc = cpu_reg(s, a->rn);
> + tcg_bytes = tcg_constant_i32(1 << a->esz);
> + tcg_rd = cpu_reg(s, a->rd);
> +
> + if (crc32c) {
> + gen_helper_crc32c_64(tcg_rd, tcg_acc, tcg_val, tcg_bytes);
> + } else {
> + gen_helper_crc32_64(tcg_rd, tcg_acc, tcg_val, tcg_bytes);
> + }
> + return true;
> +}
> +
> +TRANS_FEAT(CRC32, aa64_crc32, do_crc32, a, false)
> +TRANS_FEAT(CRC32C, aa64_crc32, do_crc32, a, true)
> +
> /* Logical (shifted register)
> * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
> * +----+-----+-----------+-------+---+------+--------+------+------+
> @@ -8473,52 +8506,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
> }
>
>
> -/* CRC32[BHWX], CRC32C[BHWX] */
> -static void handle_crc32(DisasContext *s,
> - unsigned int sf, unsigned int sz, bool crc32c,
> - unsigned int rm, unsigned int rn, unsigned int rd)
> -{
> - TCGv_i64 tcg_acc, tcg_val;
> - TCGv_i32 tcg_bytes;
> -
> - if (!dc_isar_feature(aa64_crc32, s)
> - || (sf == 1 && sz != 3)
> - || (sf == 0 && sz == 3)) {
We are not checking the sf bit anymore, is that intended?
Should we add the 'rrr_sf_[bhsd]' format?
> - unallocated_encoding(s);
> - return;
> - }
> -
> - if (sz == 3) {
> - tcg_val = cpu_reg(s, rm);
> - } else {
> - uint64_t mask;
> - switch (sz) {
> - case 0:
> - mask = 0xFF;
> - break;
> - case 1:
> - mask = 0xFFFF;
> - break;
> - case 2:
> - mask = 0xFFFFFFFF;
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - tcg_val = tcg_temp_new_i64();
> - tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask);
> - }
> -
> - tcg_acc = cpu_reg(s, rn);
> - tcg_bytes = tcg_constant_i32(1 << sz);
> -
> - if (crc32c) {
> - gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
> - } else {
> - gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
> - }
> -}
> -
> /* Data-processing (2 source)
> * 31 30 29 28 21 20 16 15 10 9 5 4 0
> * +----+---+---+-----------------+------+--------+------+------+
> @@ -8590,20 +8577,6 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
> gen_helper_pacga(cpu_reg(s, rd), tcg_env,
> cpu_reg(s, rn), cpu_reg_sp(s, rm));
> break;
> - case 16:
> - case 17:
> - case 18:
> - case 19:
> - case 20:
> - case 21:
> - case 22:
> - case 23: /* CRC32 */
> - {
> - int sz = extract32(opcode, 0, 2);
> - bool crc32c = extract32(opcode, 2, 1);
> - handle_crc32(s, sf, sz, crc32c, rm, rn, rd);
> - break;
> - }
> default:
> do_unallocated:
> case 2: /* UDIV */
> @@ -8612,6 +8585,14 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
> case 9: /* LSRV */
> case 10: /* ASRV */
> case 11: /* RORV */
> + case 16:
> + case 17:
> + case 18:
> + case 19:
> + case 20:
> + case 21:
> + case 22:
> + case 23: /* CRC32 */
> unallocated_encoding(s);
> break;
> }
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index 3db55b78a6..1664f4793c 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -45,7 +45,9 @@
> @rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
> @rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
>
> +@rrr_b ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=0
> @rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1
> +@rrr_s ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=2
> @rrr_d ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=3
> @rrr_sd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_sd
> @rrr_hsd ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=%esz_hsd
> @@ -663,6 +665,16 @@ LSRV . 00 11010110 ..... 00100 1 ..... ..... @rrr_sf
> ASRV . 00 11010110 ..... 00101 0 ..... ..... @rrr_sf
> RORV . 00 11010110 ..... 00101 1 ..... ..... @rrr_sf
>
> +CRC32 0 00 11010110 ..... 0100 00 ..... ..... @rrr_b
> +CRC32 0 00 11010110 ..... 0100 01 ..... ..... @rrr_h
> +CRC32 0 00 11010110 ..... 0100 10 ..... ..... @rrr_s
> +CRC32 1 00 11010110 ..... 0100 11 ..... ..... @rrr_d
> +
> +CRC32C 0 00 11010110 ..... 0101 00 ..... ..... @rrr_b
> +CRC32C 0 00 11010110 ..... 0101 01 ..... ..... @rrr_h
> +CRC32C 0 00 11010110 ..... 0101 10 ..... ..... @rrr_s
> +CRC32C 1 00 11010110 ..... 0101 11 ..... ..... @rrr_d
> +
> # Data Processing (1-source)
> # Logical (shifted reg)
> # Add/subtract (shifted reg)
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 04/67] target/arm: Convert CRC32, CRC32C to decodetree
2024-12-02 14:01 ` Philippe Mathieu-Daudé
@ 2024-12-02 17:49 ` Richard Henderson
2024-12-02 21:04 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-02 17:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: qemu-arm
On 12/2/24 08:01, Philippe Mathieu-Daudé wrote:
>> - if (!dc_isar_feature(aa64_crc32, s)
>> - || (sf == 1 && sz != 3)
>> - || (sf == 0 && sz == 3)) {
>
> We are not checking the sf bit anymore, is that intended?
Yes.
>> +CRC32 0 00 11010110 ..... 0100 00 ..... ..... @rrr_b
>> +CRC32 0 00 11010110 ..... 0100 01 ..... ..... @rrr_h
>> +CRC32 0 00 11010110 ..... 0100 10 ..... ..... @rrr_s
>> +CRC32 1 00 11010110 ..... 0100 11 ..... ..... @rrr_d
>> +
>> +CRC32C 0 00 11010110 ..... 0101 00 ..... ..... @rrr_b
>> +CRC32C 0 00 11010110 ..... 0101 01 ..... ..... @rrr_h
>> +CRC32C 0 00 11010110 ..... 0101 10 ..... ..... @rrr_s
>> +CRC32C 1 00 11010110 ..... 0101 11 ..... ..... @rrr_d
We are forcing sf (bit 31) to match sz (bits 10:11) in decode.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 04/67] target/arm: Convert CRC32, CRC32C to decodetree
2024-12-02 17:49 ` Richard Henderson
@ 2024-12-02 21:04 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 147+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-12-02 21:04 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 2/12/24 18:49, Richard Henderson wrote:
> On 12/2/24 08:01, Philippe Mathieu-Daudé wrote:
>>> - if (!dc_isar_feature(aa64_crc32, s)
>>> - || (sf == 1 && sz != 3)
>>> - || (sf == 0 && sz == 3)) {
>>
>> We are not checking the sf bit anymore, is that intended?
>
> Yes.
>
>>> +CRC32 0 00 11010110 ..... 0100 00 ..... ..... @rrr_b
>>> +CRC32 0 00 11010110 ..... 0100 01 ..... ..... @rrr_h
>>> +CRC32 0 00 11010110 ..... 0100 10 ..... ..... @rrr_s
>>> +CRC32 1 00 11010110 ..... 0100 11 ..... ..... @rrr_d
>>> +
>>> +CRC32C 0 00 11010110 ..... 0101 00 ..... ..... @rrr_b
>>> +CRC32C 0 00 11010110 ..... 0101 01 ..... ..... @rrr_h
>>> +CRC32C 0 00 11010110 ..... 0101 10 ..... ..... @rrr_s
>>> +CRC32C 1 00 11010110 ..... 0101 11 ..... ..... @rrr_d
>
> We are forcing sf (bit 31) to match sz (bits 10:11) in decode.
Oh, indeed :)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 05/67] target/arm: Convert SUBP, IRG, GMI to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (3 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 04/67] target/arm: Convert CRC32, CRC32C " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 14:05 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 06/67] target/arm: Convert PACGA " Richard Henderson
` (62 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 94 +++++++++++++++++++---------------
target/arm/tcg/a64.decode | 7 +++
2 files changed, 59 insertions(+), 42 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 22594a1149..00e55d42ff 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7625,6 +7625,55 @@ static bool do_crc32(DisasContext *s, arg_rrr_e *a, bool crc32c)
TRANS_FEAT(CRC32, aa64_crc32, do_crc32, a, false)
TRANS_FEAT(CRC32C, aa64_crc32, do_crc32, a, true)
+static bool do_subp(DisasContext *s, arg_rrr *a, bool setflag)
+{
+ TCGv_i64 tcg_n = read_cpu_reg_sp(s, a->rn, true);
+ TCGv_i64 tcg_m = read_cpu_reg_sp(s, a->rm, true);
+ TCGv_i64 tcg_d = cpu_reg(s, a->rd);
+
+ tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56);
+ tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56);
+
+ if (setflag) {
+ gen_sub_CC(true, tcg_d, tcg_n, tcg_m);
+ } else {
+ tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m);
+ }
+ return true;
+}
+
+TRANS_FEAT(SUBP, aa64_mte_insn_reg, do_subp, a, false)
+TRANS_FEAT(SUBPS, aa64_mte_insn_reg, do_subp, a, true)
+
+static bool trans_IRG(DisasContext *s, arg_rrr *a)
+{
+ if (dc_isar_feature(aa64_mte_insn_reg, s)) {
+ TCGv_i64 tcg_rd = cpu_reg_sp(s, a->rd);
+ TCGv_i64 tcg_rn = cpu_reg_sp(s, a->rn);
+
+ if (s->ata[0]) {
+ gen_helper_irg(tcg_rd, tcg_env, tcg_rn, cpu_reg(s, a->rm));
+ } else {
+ gen_address_with_allocation_tag0(tcg_rd, tcg_rn);
+ }
+ return true;
+ }
+ return false;
+}
+
+static bool trans_GMI(DisasContext *s, arg_rrr *a)
+{
+ if (dc_isar_feature(aa64_mte_insn_reg, s)) {
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_extract_i64(t, cpu_reg_sp(s, a->rn), 56, 4);
+ tcg_gen_shl_i64(t, tcg_constant_i64(1), t);
+ tcg_gen_or_i64(cpu_reg(s, a->rd), cpu_reg(s, a->rm), t);
+ return true;
+ }
+ return false;
+}
+
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@@ -8528,48 +8577,6 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
}
switch (opcode) {
- case 0: /* SUBP(S) */
- if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
- goto do_unallocated;
- } else {
- TCGv_i64 tcg_n, tcg_m, tcg_d;
-
- tcg_n = read_cpu_reg_sp(s, rn, true);
- tcg_m = read_cpu_reg_sp(s, rm, true);
- tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 56);
- tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 56);
- tcg_d = cpu_reg(s, rd);
-
- if (setflag) {
- gen_sub_CC(true, tcg_d, tcg_n, tcg_m);
- } else {
- tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m);
- }
- }
- break;
- case 4: /* IRG */
- if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
- goto do_unallocated;
- }
- if (s->ata[0]) {
- gen_helper_irg(cpu_reg_sp(s, rd), tcg_env,
- cpu_reg_sp(s, rn), cpu_reg(s, rm));
- } else {
- gen_address_with_allocation_tag0(cpu_reg_sp(s, rd),
- cpu_reg_sp(s, rn));
- }
- break;
- case 5: /* GMI */
- if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
- goto do_unallocated;
- } else {
- TCGv_i64 t = tcg_temp_new_i64();
-
- tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4);
- tcg_gen_shl_i64(t, tcg_constant_i64(1), t);
- tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t);
- }
- break;
case 12: /* PACGA */
if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) {
goto do_unallocated;
@@ -8579,8 +8586,11 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
break;
default:
do_unallocated:
+ case 0: /* SUBP(S) */
case 2: /* UDIV */
case 3: /* SDIV */
+ case 4: /* IRG */
+ case 5: /* GMI */
case 8: /* LSLV */
case 9: /* LSRV */
case 10: /* ASRV */
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 1664f4793c..f0a5ffb1cd 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -26,6 +26,7 @@
%hlm 11:1 20:2
&r rn
+&rrr rd rn rm
&ri rd imm
&rri_sf rd rn imm sf
&rrr_sf rd rn rm sf
@@ -656,6 +657,7 @@ CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy
# Data Processing (2-source)
+@rrr . .......... rm:5 ...... rn:5 rd:5 &rrr
@rrr_sf sf:1 .......... rm:5 ...... rn:5 rd:5 &rrr_sf
UDIV . 00 11010110 ..... 00001 0 ..... ..... @rrr_sf
@@ -675,6 +677,11 @@ CRC32C 0 00 11010110 ..... 0101 01 ..... ..... @rrr_h
CRC32C 0 00 11010110 ..... 0101 10 ..... ..... @rrr_s
CRC32C 1 00 11010110 ..... 0101 11 ..... ..... @rrr_d
+SUBP 1 00 11010110 ..... 000000 ..... ..... @rrr
+SUBPS 1 01 11010110 ..... 000000 ..... ..... @rrr
+IRG 1 00 11010110 ..... 000100 ..... ..... @rrr
+GMI 1 00 11010110 ..... 000101 ..... ..... @rrr
+
# Data Processing (1-source)
# Logical (shifted reg)
# Add/subtract (shifted reg)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 06/67] target/arm: Convert PACGA to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (4 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 05/67] target/arm: Convert SUBP, IRG, GMI " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 10:30 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 07/67] target/arm: Convert RBIT, REV16, REV32, REV64 " Richard Henderson
` (61 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove disas_data_proc_2src, as this was the last insn
decoded by that function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 65 ++++++----------------------------
target/arm/tcg/a64.decode | 2 ++
2 files changed, 13 insertions(+), 54 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 00e55d42ff..ca8b644dc7 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7674,6 +7674,16 @@ static bool trans_GMI(DisasContext *s, arg_rrr *a)
return false;
}
+static bool trans_PACGA(DisasContext *s, arg_rrr *a)
+{
+ if (dc_isar_feature(aa64_pauth, s)) {
+ gen_helper_pacga(cpu_reg(s, a->rd), tcg_env,
+ cpu_reg(s, a->rn), cpu_reg_sp(s, a->rm));
+ return true;
+ }
+ return false;
+}
+
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@@ -8555,59 +8565,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
}
-/* Data-processing (2 source)
- * 31 30 29 28 21 20 16 15 10 9 5 4 0
- * +----+---+---+-----------------+------+--------+------+------+
- * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
- * +----+---+---+-----------------+------+--------+------+------+
- */
-static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
-{
- unsigned int sf, rm, opcode, rn, rd, setflag;
- sf = extract32(insn, 31, 1);
- setflag = extract32(insn, 29, 1);
- rm = extract32(insn, 16, 5);
- opcode = extract32(insn, 10, 6);
- rn = extract32(insn, 5, 5);
- rd = extract32(insn, 0, 5);
-
- if (setflag && opcode != 0) {
- unallocated_encoding(s);
- return;
- }
-
- switch (opcode) {
- case 12: /* PACGA */
- if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) {
- goto do_unallocated;
- }
- gen_helper_pacga(cpu_reg(s, rd), tcg_env,
- cpu_reg(s, rn), cpu_reg_sp(s, rm));
- break;
- default:
- do_unallocated:
- case 0: /* SUBP(S) */
- case 2: /* UDIV */
- case 3: /* SDIV */
- case 4: /* IRG */
- case 5: /* GMI */
- case 8: /* LSLV */
- case 9: /* LSRV */
- case 10: /* ASRV */
- case 11: /* RORV */
- case 16:
- case 17:
- case 18:
- case 19:
- case 20:
- case 21:
- case 22:
- case 23: /* CRC32 */
- unallocated_encoding(s);
- break;
- }
-}
-
/*
* Data processing - register
* 31 30 29 28 25 21 20 16 10 0
@@ -8674,7 +8631,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
if (op0) { /* (1 source) */
disas_data_proc_1src(s, insn);
} else { /* (2 source) */
- disas_data_proc_2src(s, insn);
+ goto do_unallocated;
}
break;
case 0x8 ... 0xf: /* (3 source) */
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index f0a5ffb1cd..a23d6a6645 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -682,6 +682,8 @@ SUBPS 1 01 11010110 ..... 000000 ..... ..... @rrr
IRG 1 00 11010110 ..... 000100 ..... ..... @rrr
GMI 1 00 11010110 ..... 000101 ..... ..... @rrr
+PACGA 1 00 11010110 ..... 001100 ..... ..... @rrr
+
# Data Processing (1-source)
# Logical (shifted reg)
# Add/subtract (shifted reg)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 07/67] target/arm: Convert RBIT, REV16, REV32, REV64 to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (5 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 06/67] target/arm: Convert PACGA " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 17:22 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 08/67] target/arm: Convert CLZ, CLS " Richard Henderson
` (60 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 137 +++++++++++++++------------------
target/arm/tcg/a64.decode | 11 +++
2 files changed, 72 insertions(+), 76 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index ca8b644dc7..1805d77f43 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7684,6 +7684,60 @@ static bool trans_PACGA(DisasContext *s, arg_rrr *a)
return false;
}
+typedef void ArithOneOp(TCGv_i64, TCGv_i64);
+
+static bool gen_rr(DisasContext *s, int rd, int rn, ArithOneOp fn)
+{
+ fn(cpu_reg(s, rd), cpu_reg(s, rn));
+ return true;
+}
+
+static void gen_rbit32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
+{
+ TCGv_i32 t32 = tcg_temp_new_i32();
+
+ tcg_gen_extrl_i64_i32(t32, tcg_rn);
+ gen_helper_rbit(t32, t32);
+ tcg_gen_extu_i32_i64(tcg_rd, t32);
+}
+
+static void gen_rev16_xx(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 mask)
+{
+ TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
+ tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
+ tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask);
+ tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
+ tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
+}
+
+static void gen_rev16_32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
+{
+ gen_rev16_xx(tcg_rd, tcg_rn, tcg_constant_i64(0x00ff00ff));
+}
+
+static void gen_rev16_64(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
+{
+ gen_rev16_xx(tcg_rd, tcg_rn, tcg_constant_i64(0x00ff00ff00ff00ffull));
+}
+
+static void gen_rev_32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
+{
+ tcg_gen_bswap32_i64(tcg_rd, tcg_rn, TCG_BSWAP_OZ);
+}
+
+static void gen_rev32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
+{
+ tcg_gen_bswap64_i64(tcg_rd, tcg_rn);
+ tcg_gen_rotri_i64(tcg_rd, tcg_rd, 32);
+}
+
+TRANS(RBIT, gen_rr, a->rd, a->rn, a->sf ? gen_helper_rbit64 : gen_rbit32)
+TRANS(REV16, gen_rr, a->rd, a->rn, a->sf ? gen_rev16_64 : gen_rev16_32)
+TRANS(REV32, gen_rr, a->rd, a->rn, a->sf ? gen_rev32 : gen_rev_32)
+TRANS(REV64, gen_rr, a->rd, a->rn, tcg_gen_bswap64_i64)
+
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@@ -8302,67 +8356,6 @@ static void handle_cls(DisasContext *s, unsigned int sf,
}
}
-static void handle_rbit(DisasContext *s, unsigned int sf,
- unsigned int rn, unsigned int rd)
-{
- TCGv_i64 tcg_rd, tcg_rn;
- tcg_rd = cpu_reg(s, rd);
- tcg_rn = cpu_reg(s, rn);
-
- if (sf) {
- gen_helper_rbit64(tcg_rd, tcg_rn);
- } else {
- TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
- gen_helper_rbit(tcg_tmp32, tcg_tmp32);
- tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
- }
-}
-
-/* REV with sf==1, opcode==3 ("REV64") */
-static void handle_rev64(DisasContext *s, unsigned int sf,
- unsigned int rn, unsigned int rd)
-{
- if (!sf) {
- unallocated_encoding(s);
- return;
- }
- tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
-}
-
-/* REV with sf==0, opcode==2
- * REV32 (sf==1, opcode==2)
- */
-static void handle_rev32(DisasContext *s, unsigned int sf,
- unsigned int rn, unsigned int rd)
-{
- TCGv_i64 tcg_rd = cpu_reg(s, rd);
- TCGv_i64 tcg_rn = cpu_reg(s, rn);
-
- if (sf) {
- tcg_gen_bswap64_i64(tcg_rd, tcg_rn);
- tcg_gen_rotri_i64(tcg_rd, tcg_rd, 32);
- } else {
- tcg_gen_bswap32_i64(tcg_rd, tcg_rn, TCG_BSWAP_OZ);
- }
-}
-
-/* REV16 (opcode==1) */
-static void handle_rev16(DisasContext *s, unsigned int sf,
- unsigned int rn, unsigned int rd)
-{
- TCGv_i64 tcg_rd = cpu_reg(s, rd);
- TCGv_i64 tcg_tmp = tcg_temp_new_i64();
- TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
- TCGv_i64 mask = tcg_constant_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
-
- tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
- tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
- tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask);
- tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
- tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
-}
-
/* Data-processing (1 source)
* 31 30 29 28 21 20 16 15 10 9 5 4 0
* +----+---+---+-----------------+---------+--------+------+------+
@@ -8388,21 +8381,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
#define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
switch (MAP(sf, opcode2, opcode)) {
- case MAP(0, 0x00, 0x00): /* RBIT */
- case MAP(1, 0x00, 0x00):
- handle_rbit(s, sf, rn, rd);
- break;
- case MAP(0, 0x00, 0x01): /* REV16 */
- case MAP(1, 0x00, 0x01):
- handle_rev16(s, sf, rn, rd);
- break;
- case MAP(0, 0x00, 0x02): /* REV/REV32 */
- case MAP(1, 0x00, 0x02):
- handle_rev32(s, sf, rn, rd);
- break;
- case MAP(1, 0x00, 0x03): /* REV64 */
- handle_rev64(s, sf, rn, rd);
- break;
case MAP(0, 0x00, 0x04): /* CLZ */
case MAP(1, 0x00, 0x04):
handle_clz(s, sf, rn, rd);
@@ -8557,6 +8535,13 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
break;
default:
do_unallocated:
+ case MAP(0, 0x00, 0x00): /* RBIT */
+ case MAP(1, 0x00, 0x00):
+ case MAP(0, 0x00, 0x01): /* REV16 */
+ case MAP(1, 0x00, 0x01):
+ case MAP(0, 0x00, 0x02): /* REV/REV32 */
+ case MAP(1, 0x00, 0x02):
+ case MAP(1, 0x00, 0x03): /* REV64 */
unallocated_encoding(s);
break;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index a23d6a6645..dd44651f34 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -28,6 +28,8 @@
&r rn
&rrr rd rn rm
&ri rd imm
+&rr rd rn
+&rr_sf rd rn sf
&rri_sf rd rn imm sf
&rrr_sf rd rn rm sf
&i imm
@@ -685,6 +687,15 @@ GMI 1 00 11010110 ..... 000101 ..... ..... @rrr
PACGA 1 00 11010110 ..... 001100 ..... ..... @rrr
# Data Processing (1-source)
+
+@rr . .......... ..... ...... rn:5 rd:5 &rr
+@rr_sf sf:1 .......... ..... ...... rn:5 rd:5 &rr_sf
+
+RBIT . 10 11010110 00000 000000 ..... ..... @rr_sf
+REV16 . 10 11010110 00000 000001 ..... ..... @rr_sf
+REV32 . 10 11010110 00000 000010 ..... ..... @rr_sf
+REV64 1 10 11010110 00000 000011 ..... ..... @rr
+
# Logical (shifted reg)
# Add/subtract (shifted reg)
# Add/subtract (extended reg)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 07/67] target/arm: Convert RBIT, REV16, REV32, REV64 to decodetree
2024-12-01 15:05 ` [PATCH 07/67] target/arm: Convert RBIT, REV16, REV32, REV64 " Richard Henderson
@ 2024-12-05 17:22 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-05 17:22 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:08, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 137 +++++++++++++++------------------
> target/arm/tcg/a64.decode | 11 +++
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 08/67] target/arm: Convert CLZ, CLS to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (6 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 07/67] target/arm: Convert RBIT, REV16, REV32, REV64 " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 14:08 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 09/67] target/arm: Convert PAC[ID]*, AUT[ID]* " Richard Henderson
` (59 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 72 ++++++++++++++--------------------
target/arm/tcg/a64.decode | 3 ++
2 files changed, 33 insertions(+), 42 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 1805d77f43..552b45b4e2 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7738,6 +7738,32 @@ TRANS(REV16, gen_rr, a->rd, a->rn, a->sf ? gen_rev16_64 : gen_rev16_32)
TRANS(REV32, gen_rr, a->rd, a->rn, a->sf ? gen_rev32 : gen_rev_32)
TRANS(REV64, gen_rr, a->rd, a->rn, tcg_gen_bswap64_i64)
+static void gen_clz32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
+{
+ TCGv_i32 t32 = tcg_temp_new_i32();
+
+ tcg_gen_extrl_i64_i32(t32, tcg_rn);
+ tcg_gen_clzi_i32(t32, t32, 32);
+ tcg_gen_extu_i32_i64(tcg_rd, t32);
+}
+
+static void gen_clz64(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
+{
+ tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64);
+}
+
+static void gen_cls32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
+{
+ TCGv_i32 t32 = tcg_temp_new_i32();
+
+ tcg_gen_extrl_i64_i32(t32, tcg_rn);
+ tcg_gen_clrsb_i32(t32, t32);
+ tcg_gen_extu_i32_i64(tcg_rd, t32);
+}
+
+TRANS(CLZ, gen_rr, a->rd, a->rn, a->sf ? gen_clz64 : gen_clz32)
+TRANS(CLS, gen_rr, a->rd, a->rn, a->sf ? tcg_gen_clrsb_i64 : gen_cls32)
+
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@@ -8322,40 +8348,6 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
}
}
-static void handle_clz(DisasContext *s, unsigned int sf,
- unsigned int rn, unsigned int rd)
-{
- TCGv_i64 tcg_rd, tcg_rn;
- tcg_rd = cpu_reg(s, rd);
- tcg_rn = cpu_reg(s, rn);
-
- if (sf) {
- tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64);
- } else {
- TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
- tcg_gen_clzi_i32(tcg_tmp32, tcg_tmp32, 32);
- tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
- }
-}
-
-static void handle_cls(DisasContext *s, unsigned int sf,
- unsigned int rn, unsigned int rd)
-{
- TCGv_i64 tcg_rd, tcg_rn;
- tcg_rd = cpu_reg(s, rd);
- tcg_rn = cpu_reg(s, rn);
-
- if (sf) {
- tcg_gen_clrsb_i64(tcg_rd, tcg_rn);
- } else {
- TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
- tcg_gen_clrsb_i32(tcg_tmp32, tcg_tmp32);
- tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
- }
-}
-
/* Data-processing (1 source)
* 31 30 29 28 21 20 16 15 10 9 5 4 0
* +----+---+---+-----------------+---------+--------+------+------+
@@ -8381,14 +8373,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
#define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
switch (MAP(sf, opcode2, opcode)) {
- case MAP(0, 0x00, 0x04): /* CLZ */
- case MAP(1, 0x00, 0x04):
- handle_clz(s, sf, rn, rd);
- break;
- case MAP(0, 0x00, 0x05): /* CLS */
- case MAP(1, 0x00, 0x05):
- handle_cls(s, sf, rn, rd);
- break;
case MAP(1, 0x01, 0x00): /* PACIA */
if (s->pauth_active) {
tcg_rd = cpu_reg(s, rd);
@@ -8542,6 +8526,10 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
case MAP(0, 0x00, 0x02): /* REV/REV32 */
case MAP(1, 0x00, 0x02):
case MAP(1, 0x00, 0x03): /* REV64 */
+ case MAP(0, 0x00, 0x04): /* CLZ */
+ case MAP(1, 0x00, 0x04):
+ case MAP(0, 0x00, 0x05): /* CLS */
+ case MAP(1, 0x00, 0x05):
unallocated_encoding(s);
break;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index dd44651f34..410eaa9333 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -696,6 +696,9 @@ REV16 . 10 11010110 00000 000001 ..... ..... @rr_sf
REV32 . 10 11010110 00000 000010 ..... ..... @rr_sf
REV64 1 10 11010110 00000 000011 ..... ..... @rr
+CLZ . 10 11010110 00000 000100 ..... ..... @rr_sf
+CLS . 10 11010110 00000 000101 ..... ..... @rr_sf
+
# Logical (shifted reg)
# Add/subtract (shifted reg)
# Add/subtract (extended reg)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 09/67] target/arm: Convert PAC[ID]*, AUT[ID]* to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (7 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 08/67] target/arm: Convert CLZ, CLS " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 17:29 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 10/67] target/arm: Convert XPAC[ID] " Richard Henderson
` (58 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes PACIA, PACIZA, PACIB, PACIZB, PACDA, PACDZA, PACDB,
PACDZB, AUTIA, AUTIZA, AUTIB, AUTIZB, AUTDA, AUTDZA, AUTDB, AUTDZB.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 173 +++++++++------------------------
target/arm/tcg/a64.decode | 13 +++
2 files changed, 58 insertions(+), 128 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 552b45b4e2..852545dfcc 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7764,6 +7764,35 @@ static void gen_cls32(TCGv_i64 tcg_rd, TCGv_i64 tcg_rn)
TRANS(CLZ, gen_rr, a->rd, a->rn, a->sf ? gen_clz64 : gen_clz32)
TRANS(CLS, gen_rr, a->rd, a->rn, a->sf ? tcg_gen_clrsb_i64 : gen_cls32)
+static bool gen_pacaut(DisasContext *s, arg_pacaut *a, NeonGenTwo64OpEnvFn fn)
+{
+ TCGv_i64 tcg_rd, tcg_rn;
+
+ if (a->z) {
+ if (a->rn != 31) {
+ return false;
+ }
+ tcg_rn = tcg_constant_i64(0);
+ } else {
+ tcg_rn = cpu_reg_sp(s, a->rn);
+ }
+ if (s->pauth_active) {
+ tcg_rd = cpu_reg(s, a->rd);
+ fn(tcg_rd, tcg_env, tcg_rd, tcg_rn);
+ }
+ return true;
+}
+
+TRANS_FEAT(PACIA, aa64_pauth, gen_pacaut, a, gen_helper_pacia)
+TRANS_FEAT(PACIB, aa64_pauth, gen_pacaut, a, gen_helper_pacib)
+TRANS_FEAT(PACDA, aa64_pauth, gen_pacaut, a, gen_helper_pacda)
+TRANS_FEAT(PACDB, aa64_pauth, gen_pacaut, a, gen_helper_pacdb)
+
+TRANS_FEAT(AUTIA, aa64_pauth, gen_pacaut, a, gen_helper_autia)
+TRANS_FEAT(AUTIB, aa64_pauth, gen_pacaut, a, gen_helper_autib)
+TRANS_FEAT(AUTDA, aa64_pauth, gen_pacaut, a, gen_helper_autda)
+TRANS_FEAT(AUTDB, aa64_pauth, gen_pacaut, a, gen_helper_autdb)
+
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@@ -8373,134 +8402,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
#define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
switch (MAP(sf, opcode2, opcode)) {
- case MAP(1, 0x01, 0x00): /* PACIA */
- if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_pacia(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
- } else if (!dc_isar_feature(aa64_pauth, s)) {
- goto do_unallocated;
- }
- break;
- case MAP(1, 0x01, 0x01): /* PACIB */
- if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_pacib(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
- } else if (!dc_isar_feature(aa64_pauth, s)) {
- goto do_unallocated;
- }
- break;
- case MAP(1, 0x01, 0x02): /* PACDA */
- if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_pacda(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
- } else if (!dc_isar_feature(aa64_pauth, s)) {
- goto do_unallocated;
- }
- break;
- case MAP(1, 0x01, 0x03): /* PACDB */
- if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_pacdb(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
- } else if (!dc_isar_feature(aa64_pauth, s)) {
- goto do_unallocated;
- }
- break;
- case MAP(1, 0x01, 0x04): /* AUTIA */
- if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_autia(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
- } else if (!dc_isar_feature(aa64_pauth, s)) {
- goto do_unallocated;
- }
- break;
- case MAP(1, 0x01, 0x05): /* AUTIB */
- if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_autib(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
- } else if (!dc_isar_feature(aa64_pauth, s)) {
- goto do_unallocated;
- }
- break;
- case MAP(1, 0x01, 0x06): /* AUTDA */
- if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_autda(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
- } else if (!dc_isar_feature(aa64_pauth, s)) {
- goto do_unallocated;
- }
- break;
- case MAP(1, 0x01, 0x07): /* AUTDB */
- if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_autdb(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn));
- } else if (!dc_isar_feature(aa64_pauth, s)) {
- goto do_unallocated;
- }
- break;
- case MAP(1, 0x01, 0x08): /* PACIZA */
- if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
- goto do_unallocated;
- } else if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_pacia(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
- }
- break;
- case MAP(1, 0x01, 0x09): /* PACIZB */
- if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
- goto do_unallocated;
- } else if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_pacib(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
- }
- break;
- case MAP(1, 0x01, 0x0a): /* PACDZA */
- if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
- goto do_unallocated;
- } else if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_pacda(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
- }
- break;
- case MAP(1, 0x01, 0x0b): /* PACDZB */
- if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
- goto do_unallocated;
- } else if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_pacdb(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
- }
- break;
- case MAP(1, 0x01, 0x0c): /* AUTIZA */
- if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
- goto do_unallocated;
- } else if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_autia(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
- }
- break;
- case MAP(1, 0x01, 0x0d): /* AUTIZB */
- if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
- goto do_unallocated;
- } else if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_autib(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
- }
- break;
- case MAP(1, 0x01, 0x0e): /* AUTDZA */
- if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
- goto do_unallocated;
- } else if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_autda(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
- }
- break;
- case MAP(1, 0x01, 0x0f): /* AUTDZB */
- if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
- goto do_unallocated;
- } else if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_autdb(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0));
- }
- break;
case MAP(1, 0x01, 0x10): /* XPACI */
if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
goto do_unallocated;
@@ -8530,6 +8431,22 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
case MAP(1, 0x00, 0x04):
case MAP(0, 0x00, 0x05): /* CLS */
case MAP(1, 0x00, 0x05):
+ case MAP(1, 0x01, 0x00): /* PACIA */
+ case MAP(1, 0x01, 0x01): /* PACIB */
+ case MAP(1, 0x01, 0x02): /* PACDA */
+ case MAP(1, 0x01, 0x03): /* PACDB */
+ case MAP(1, 0x01, 0x04): /* AUTIA */
+ case MAP(1, 0x01, 0x05): /* AUTIB */
+ case MAP(1, 0x01, 0x06): /* AUTDA */
+ case MAP(1, 0x01, 0x07): /* AUTDB */
+ case MAP(1, 0x01, 0x08): /* PACIZA */
+ case MAP(1, 0x01, 0x09): /* PACIZB */
+ case MAP(1, 0x01, 0x0a): /* PACDZA */
+ case MAP(1, 0x01, 0x0b): /* PACDZB */
+ case MAP(1, 0x01, 0x0c): /* AUTIZA */
+ case MAP(1, 0x01, 0x0d): /* AUTIZB */
+ case MAP(1, 0x01, 0x0e): /* AUTDZA */
+ case MAP(1, 0x01, 0x0f): /* AUTDZB */
unallocated_encoding(s);
break;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 410eaa9333..9083ac4ac3 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -699,6 +699,19 @@ REV64 1 10 11010110 00000 000011 ..... ..... @rr
CLZ . 10 11010110 00000 000100 ..... ..... @rr_sf
CLS . 10 11010110 00000 000101 ..... ..... @rr_sf
+&pacaut rd rn z
+@pacaut . .. ........ ..... .. z:1 ... rn:5 rd:5 &pacaut
+
+PACIA 1 10 11010110 00001 00.000 ..... ..... @pacaut
+PACIB 1 10 11010110 00001 00.001 ..... ..... @pacaut
+PACDA 1 10 11010110 00001 00.010 ..... ..... @pacaut
+PACDB 1 10 11010110 00001 00.011 ..... ..... @pacaut
+
+AUTIA 1 10 11010110 00001 00.100 ..... ..... @pacaut
+AUTIB 1 10 11010110 00001 00.101 ..... ..... @pacaut
+AUTDA 1 10 11010110 00001 00.110 ..... ..... @pacaut
+AUTDB 1 10 11010110 00001 00.111 ..... ..... @pacaut
+
# Logical (shifted reg)
# Add/subtract (shifted reg)
# Add/subtract (extended reg)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 09/67] target/arm: Convert PAC[ID]*, AUT[ID]* to decodetree
2024-12-01 15:05 ` [PATCH 09/67] target/arm: Convert PAC[ID]*, AUT[ID]* " Richard Henderson
@ 2024-12-05 17:29 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-05 17:29 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:12, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This includes PACIA, PACIZA, PACIB, PACIZB, PACDA, PACDZA, PACDB,
> PACDZB, AUTIA, AUTIZA, AUTIB, AUTIZB, AUTDA, AUTDZA, AUTDB, AUTDZB.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 173 +++++++++------------------------
> target/arm/tcg/a64.decode | 13 +++
> 2 files changed, 58 insertions(+), 128 deletions(-)
Well, that's certainly a more compact representation than we had before :-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 10/67] target/arm: Convert XPAC[ID] to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (8 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 09/67] target/arm: Convert PAC[ID]*, AUT[ID]* " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 14:11 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 11/67] target/arm: Convert disas_logic_reg " Richard Henderson
` (57 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove disas_data_proc_1src, as these were the last insns
decoded by that function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 99 +++++-----------------------------
target/arm/tcg/a64.decode | 3 ++
2 files changed, 16 insertions(+), 86 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 852545dfcc..d92fe68299 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7793,6 +7793,18 @@ TRANS_FEAT(AUTIB, aa64_pauth, gen_pacaut, a, gen_helper_autib)
TRANS_FEAT(AUTDA, aa64_pauth, gen_pacaut, a, gen_helper_autda)
TRANS_FEAT(AUTDB, aa64_pauth, gen_pacaut, a, gen_helper_autdb)
+static bool do_xpac(DisasContext *s, int rd, NeonGenOne64OpEnvFn *fn)
+{
+ if (s->pauth_active) {
+ TCGv_i64 tcg_rd = cpu_reg(s, rd);
+ fn(tcg_rd, tcg_env, tcg_rd);
+ }
+ return true;
+}
+
+TRANS_FEAT(XPACI, aa64_pauth, do_xpac, a->rd, gen_helper_xpaci)
+TRANS_FEAT(XPACD, aa64_pauth, do_xpac, a->rd, gen_helper_xpacd)
+
/* Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
@@ -8377,84 +8389,6 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
}
}
-/* Data-processing (1 source)
- * 31 30 29 28 21 20 16 15 10 9 5 4 0
- * +----+---+---+-----------------+---------+--------+------+------+
- * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
- * +----+---+---+-----------------+---------+--------+------+------+
- */
-static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
-{
- unsigned int sf, opcode, opcode2, rn, rd;
- TCGv_i64 tcg_rd;
-
- if (extract32(insn, 29, 1)) {
- unallocated_encoding(s);
- return;
- }
-
- sf = extract32(insn, 31, 1);
- opcode = extract32(insn, 10, 6);
- opcode2 = extract32(insn, 16, 5);
- rn = extract32(insn, 5, 5);
- rd = extract32(insn, 0, 5);
-
-#define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
-
- switch (MAP(sf, opcode2, opcode)) {
- case MAP(1, 0x01, 0x10): /* XPACI */
- if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
- goto do_unallocated;
- } else if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_xpaci(tcg_rd, tcg_env, tcg_rd);
- }
- break;
- case MAP(1, 0x01, 0x11): /* XPACD */
- if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
- goto do_unallocated;
- } else if (s->pauth_active) {
- tcg_rd = cpu_reg(s, rd);
- gen_helper_xpacd(tcg_rd, tcg_env, tcg_rd);
- }
- break;
- default:
- do_unallocated:
- case MAP(0, 0x00, 0x00): /* RBIT */
- case MAP(1, 0x00, 0x00):
- case MAP(0, 0x00, 0x01): /* REV16 */
- case MAP(1, 0x00, 0x01):
- case MAP(0, 0x00, 0x02): /* REV/REV32 */
- case MAP(1, 0x00, 0x02):
- case MAP(1, 0x00, 0x03): /* REV64 */
- case MAP(0, 0x00, 0x04): /* CLZ */
- case MAP(1, 0x00, 0x04):
- case MAP(0, 0x00, 0x05): /* CLS */
- case MAP(1, 0x00, 0x05):
- case MAP(1, 0x01, 0x00): /* PACIA */
- case MAP(1, 0x01, 0x01): /* PACIB */
- case MAP(1, 0x01, 0x02): /* PACDA */
- case MAP(1, 0x01, 0x03): /* PACDB */
- case MAP(1, 0x01, 0x04): /* AUTIA */
- case MAP(1, 0x01, 0x05): /* AUTIB */
- case MAP(1, 0x01, 0x06): /* AUTDA */
- case MAP(1, 0x01, 0x07): /* AUTDB */
- case MAP(1, 0x01, 0x08): /* PACIZA */
- case MAP(1, 0x01, 0x09): /* PACIZB */
- case MAP(1, 0x01, 0x0a): /* PACDZA */
- case MAP(1, 0x01, 0x0b): /* PACDZB */
- case MAP(1, 0x01, 0x0c): /* AUTIZA */
- case MAP(1, 0x01, 0x0d): /* AUTIZB */
- case MAP(1, 0x01, 0x0e): /* AUTDZA */
- case MAP(1, 0x01, 0x0f): /* AUTDZB */
- unallocated_encoding(s);
- break;
- }
-
-#undef MAP
-}
-
-
/*
* Data processing - register
* 31 30 29 28 25 21 20 16 10 0
@@ -8464,7 +8398,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
*/
static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
{
- int op0 = extract32(insn, 30, 1);
int op1 = extract32(insn, 28, 1);
int op2 = extract32(insn, 21, 4);
int op3 = extract32(insn, 10, 6);
@@ -8517,19 +8450,13 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
disas_cond_select(s, insn);
break;
- case 0x6: /* Data-processing */
- if (op0) { /* (1 source) */
- disas_data_proc_1src(s, insn);
- } else { /* (2 source) */
- goto do_unallocated;
- }
- break;
case 0x8 ... 0xf: /* (3 source) */
disas_data_proc_3src(s, insn);
break;
default:
do_unallocated:
+ case 0x6: /* Data-processing */
unallocated_encoding(s);
break;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 9083ac4ac3..0e04ab6ce4 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -712,6 +712,9 @@ AUTIB 1 10 11010110 00001 00.101 ..... ..... @pacaut
AUTDA 1 10 11010110 00001 00.110 ..... ..... @pacaut
AUTDB 1 10 11010110 00001 00.111 ..... ..... @pacaut
+XPACI 1 10 11010110 00001 010000 11111 rd:5
+XPACD 1 10 11010110 00001 010001 11111 rd:5
+
# Logical (shifted reg)
# Add/subtract (shifted reg)
# Add/subtract (extended reg)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 11/67] target/arm: Convert disas_logic_reg to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (9 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 10/67] target/arm: Convert XPAC[ID] " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 17:38 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 12/67] target/arm: Convert disas_add_sub_ext_reg " Richard Henderson
` (56 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS (shifted reg).
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 117 ++++++++++++---------------------
target/arm/tcg/a64.decode | 9 +++
2 files changed, 51 insertions(+), 75 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index d92fe68299..ecc8899dd8 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7805,96 +7805,65 @@ static bool do_xpac(DisasContext *s, int rd, NeonGenOne64OpEnvFn *fn)
TRANS_FEAT(XPACI, aa64_pauth, do_xpac, a->rd, gen_helper_xpaci)
TRANS_FEAT(XPACD, aa64_pauth, do_xpac, a->rd, gen_helper_xpacd)
-/* Logical (shifted register)
- * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
- * +----+-----+-----------+-------+---+------+--------+------+------+
- * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
- * +----+-----+-----------+-------+---+------+--------+------+------+
- */
-static void disas_logic_reg(DisasContext *s, uint32_t insn)
+static bool do_logic_reg(DisasContext *s, arg_logic_shift *a,
+ ArithTwoOp *fn, ArithTwoOp *inv_fn, bool setflags)
{
TCGv_i64 tcg_rd, tcg_rn, tcg_rm;
- unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;
- sf = extract32(insn, 31, 1);
- opc = extract32(insn, 29, 2);
- shift_type = extract32(insn, 22, 2);
- invert = extract32(insn, 21, 1);
- rm = extract32(insn, 16, 5);
- shift_amount = extract32(insn, 10, 6);
- rn = extract32(insn, 5, 5);
- rd = extract32(insn, 0, 5);
-
- if (!sf && (shift_amount & (1 << 5))) {
- unallocated_encoding(s);
- return;
+ if (!a->sf && (a->sa & (1 << 5))) {
+ return false;
}
- tcg_rd = cpu_reg(s, rd);
+ tcg_rd = cpu_reg(s, a->rd);
+ tcg_rn = cpu_reg(s, a->rn);
- if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) {
- /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
- * register-register MOV and MVN, so it is worth special casing.
- */
- tcg_rm = cpu_reg(s, rm);
- if (invert) {
+ tcg_rm = read_cpu_reg(s, a->rm, a->sf);
+ if (a->sa) {
+ shift_reg_imm(tcg_rm, tcg_rm, a->sf, a->st, a->sa);
+ }
+
+ (a->n ? inv_fn : fn)(tcg_rd, tcg_rn, tcg_rm);
+ if (!a->sf) {
+ tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+ }
+ if (setflags) {
+ gen_logic_CC(a->sf, tcg_rd);
+ }
+ return true;
+}
+
+static bool trans_ORR_r(DisasContext *s, arg_logic_shift *a)
+{
+ /*
+ * Unshifted ORR and ORN with WZR/XZR is the standard encoding for
+ * register-register MOV and MVN, so it is worth special casing.
+ */
+ if (a->sa == 0 && a->st == 0 && a->rn == 31) {
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ TCGv_i64 tcg_rm = cpu_reg(s, a->rm);
+
+ if (a->n) {
tcg_gen_not_i64(tcg_rd, tcg_rm);
- if (!sf) {
+ if (!a->sf) {
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
} else {
- if (sf) {
+ if (a->sf) {
tcg_gen_mov_i64(tcg_rd, tcg_rm);
} else {
tcg_gen_ext32u_i64(tcg_rd, tcg_rm);
}
}
- return;
+ return true;
}
- tcg_rm = read_cpu_reg(s, rm, sf);
-
- if (shift_amount) {
- shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount);
- }
-
- tcg_rn = cpu_reg(s, rn);
-
- switch (opc | (invert << 2)) {
- case 0: /* AND */
- case 3: /* ANDS */
- tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- case 1: /* ORR */
- tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- case 2: /* EOR */
- tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- case 4: /* BIC */
- case 7: /* BICS */
- tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- case 5: /* ORN */
- tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- case 6: /* EON */
- tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm);
- break;
- default:
- assert(FALSE);
- break;
- }
-
- if (!sf) {
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
- }
-
- if (opc == 3) {
- gen_logic_CC(sf, tcg_rd);
- }
+ return do_logic_reg(s, a, tcg_gen_or_i64, tcg_gen_orc_i64, false);
}
+TRANS(AND_r, do_logic_reg, a, tcg_gen_and_i64, tcg_gen_andc_i64, false)
+TRANS(ANDS_r, do_logic_reg, a, tcg_gen_and_i64, tcg_gen_andc_i64, true)
+TRANS(EOR_r, do_logic_reg, a, tcg_gen_xor_i64, tcg_gen_eqv_i64, false)
+
/*
* Add/subtract (extended register)
*
@@ -8411,11 +8380,9 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
/* Add/sub (shifted register) */
disas_add_sub_reg(s, insn);
}
- } else {
- /* Logical (shifted register) */
- disas_logic_reg(s, insn);
+ return;
}
- return;
+ goto do_unallocated;
}
switch (op2) {
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 0e04ab6ce4..53629119b2 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -716,6 +716,15 @@ XPACI 1 10 11010110 00001 010000 11111 rd:5
XPACD 1 10 11010110 00001 010001 11111 rd:5
# Logical (shifted reg)
+
+&logic_shift rd rn rm sf sa st n
+@logic_shift sf:1 .. ..... st:2 n:1 rm:5 sa:6 rn:5 rd:5
+
+AND_r . 00 01010 .. . ..... ...... ..... ..... @logic_shift
+ORR_r . 01 01010 .. . ..... ...... ..... ..... @logic_shift
+EOR_r . 10 01010 .. . ..... ...... ..... ..... @logic_shift
+ANDS_r . 11 01010 .. . ..... ...... ..... ..... @logic_shift
+
# Add/subtract (shifted reg)
# Add/subtract (extended reg)
# Add/subtract (carry)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 11/67] target/arm: Convert disas_logic_reg to decodetree
2024-12-01 15:05 ` [PATCH 11/67] target/arm: Convert disas_logic_reg " Richard Henderson
@ 2024-12-05 17:38 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-05 17:38 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This includes AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS (shifted reg).
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 12/67] target/arm: Convert disas_add_sub_ext_reg to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (10 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 11/67] target/arm: Convert disas_logic_reg " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 17:42 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 13/67] target/arm: Convert disas_add_sub_reg " Richard Henderson
` (55 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes ADD, SUB, ADDS, SUBS (extended register).
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 65 +++++++++++-----------------------
target/arm/tcg/a64.decode | 9 +++++
2 files changed, 29 insertions(+), 45 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index ecc8899dd8..8f777875fe 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7864,57 +7864,27 @@ TRANS(AND_r, do_logic_reg, a, tcg_gen_and_i64, tcg_gen_andc_i64, false)
TRANS(ANDS_r, do_logic_reg, a, tcg_gen_and_i64, tcg_gen_andc_i64, true)
TRANS(EOR_r, do_logic_reg, a, tcg_gen_xor_i64, tcg_gen_eqv_i64, false)
-/*
- * Add/subtract (extended register)
- *
- * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
- * +--+--+--+-----------+-----+--+-------+------+------+----+----+
- * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
- * +--+--+--+-----------+-----+--+-------+------+------+----+----+
- *
- * sf: 0 -> 32bit, 1 -> 64bit
- * op: 0 -> add , 1 -> sub
- * S: 1 -> set flags
- * opt: 00
- * option: extension type (see DecodeRegExtend)
- * imm3: optional shift to Rm
- *
- * Rd = Rn + LSL(extend(Rm), amount)
- */
-static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
+static bool do_addsub_ext(DisasContext *s, arg_addsub_ext *a,
+ bool sub_op, bool setflags)
{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int imm3 = extract32(insn, 10, 3);
- int option = extract32(insn, 13, 3);
- int rm = extract32(insn, 16, 5);
- int opt = extract32(insn, 22, 2);
- bool setflags = extract32(insn, 29, 1);
- bool sub_op = extract32(insn, 30, 1);
- bool sf = extract32(insn, 31, 1);
+ TCGv_i64 tcg_rm, tcg_rn, tcg_rd, tcg_result;
- TCGv_i64 tcg_rm, tcg_rn; /* temps */
- TCGv_i64 tcg_rd;
- TCGv_i64 tcg_result;
-
- if (imm3 > 4 || opt != 0) {
- unallocated_encoding(s);
- return;
+ if (a->sa > 4) {
+ return false;
}
/* non-flag setting ops may use SP */
if (!setflags) {
- tcg_rd = cpu_reg_sp(s, rd);
+ tcg_rd = cpu_reg_sp(s, a->rd);
} else {
- tcg_rd = cpu_reg(s, rd);
+ tcg_rd = cpu_reg(s, a->rd);
}
- tcg_rn = read_cpu_reg_sp(s, rn, sf);
+ tcg_rn = read_cpu_reg_sp(s, a->rn, a->sf);
- tcg_rm = read_cpu_reg(s, rm, sf);
- ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
+ tcg_rm = read_cpu_reg(s, a->rm, a->sf);
+ ext_and_shift_reg(tcg_rm, tcg_rm, a->st, a->sa);
tcg_result = tcg_temp_new_i64();
-
if (!setflags) {
if (sub_op) {
tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
@@ -7923,19 +7893,25 @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
}
} else {
if (sub_op) {
- gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
+ gen_sub_CC(a->sf, tcg_result, tcg_rn, tcg_rm);
} else {
- gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
+ gen_add_CC(a->sf, tcg_result, tcg_rn, tcg_rm);
}
}
- if (sf) {
+ if (a->sf) {
tcg_gen_mov_i64(tcg_rd, tcg_result);
} else {
tcg_gen_ext32u_i64(tcg_rd, tcg_result);
}
+ return true;
}
+TRANS(ADD_ext, do_addsub_ext, a, false, false)
+TRANS(SUB_ext, do_addsub_ext, a, true, false)
+TRANS(ADDS_ext, do_addsub_ext, a, false, true)
+TRANS(SUBS_ext, do_addsub_ext, a, true, true)
+
/*
* Add/subtract (shifted register)
*
@@ -8374,8 +8350,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
if (!op1) {
if (op2 & 8) {
if (op2 & 1) {
- /* Add/sub (extended register) */
- disas_add_sub_ext_reg(s, insn);
+ goto do_unallocated;
} else {
/* Add/sub (shifted register) */
disas_add_sub_reg(s, insn);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 53629119b2..b4ccad34fb 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -727,6 +727,15 @@ ANDS_r . 11 01010 .. . ..... ...... ..... ..... @logic_shift
# Add/subtract (shifted reg)
# Add/subtract (extended reg)
+
+&addsub_ext rd rn rm sf sa st
+@addsub_ext sf:1 .. ........ rm:5 st:3 sa:3 rn:5 rd:5 &addsub_ext
+
+ADD_ext . 00 01011001 ..... ... ... ..... ..... @addsub_ext
+SUB_ext . 10 01011001 ..... ... ... ..... ..... @addsub_ext
+ADDS_ext . 01 01011001 ..... ... ... ..... ..... @addsub_ext
+SUBS_ext . 11 01011001 ..... ... ... ..... ..... @addsub_ext
+
# Add/subtract (carry)
# Rotate right into flags
# Evaluate into flags
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 13/67] target/arm: Convert disas_add_sub_reg to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (11 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 12/67] target/arm: Convert disas_add_sub_ext_reg " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 17:45 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 14/67] target/arm: Convert disas_data_proc_3src " Richard Henderson
` (54 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes ADD, SUB, ADDS, SUBS (shifted register).
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 64 ++++++++++------------------------
target/arm/tcg/a64.decode | 11 +++++-
2 files changed, 28 insertions(+), 47 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 8f777875fe..d570bbb696 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7912,47 +7912,22 @@ TRANS(SUB_ext, do_addsub_ext, a, true, false)
TRANS(ADDS_ext, do_addsub_ext, a, false, true)
TRANS(SUBS_ext, do_addsub_ext, a, true, true)
-/*
- * Add/subtract (shifted register)
- *
- * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
- * +--+--+--+-----------+-----+--+-------+---------+------+------+
- * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
- * +--+--+--+-----------+-----+--+-------+---------+------+------+
- *
- * sf: 0 -> 32bit, 1 -> 64bit
- * op: 0 -> add , 1 -> sub
- * S: 1 -> set flags
- * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
- * imm6: Shift amount to apply to Rm before the add/sub
- */
-static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
+static bool do_addsub_reg(DisasContext *s, arg_addsub_shift *a,
+ bool sub_op, bool setflags)
{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int imm6 = extract32(insn, 10, 6);
- int rm = extract32(insn, 16, 5);
- int shift_type = extract32(insn, 22, 2);
- bool setflags = extract32(insn, 29, 1);
- bool sub_op = extract32(insn, 30, 1);
- bool sf = extract32(insn, 31, 1);
+ TCGv_i64 tcg_rd, tcg_rn, tcg_rm, tcg_result;
- TCGv_i64 tcg_rd = cpu_reg(s, rd);
- TCGv_i64 tcg_rn, tcg_rm;
- TCGv_i64 tcg_result;
-
- if ((shift_type == 3) || (!sf && (imm6 > 31))) {
- unallocated_encoding(s);
- return;
+ if (a->st == 3 || (!a->sf && (a->sa & 32))) {
+ return false;
}
- tcg_rn = read_cpu_reg(s, rn, sf);
- tcg_rm = read_cpu_reg(s, rm, sf);
+ tcg_rd = cpu_reg(s, a->rd);
+ tcg_rn = read_cpu_reg(s, a->rn, a->sf);
+ tcg_rm = read_cpu_reg(s, a->rm, a->sf);
- shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6);
+ shift_reg_imm(tcg_rm, tcg_rm, a->sf, a->st, a->sa);
tcg_result = tcg_temp_new_i64();
-
if (!setflags) {
if (sub_op) {
tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
@@ -7961,19 +7936,25 @@ static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
}
} else {
if (sub_op) {
- gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
+ gen_sub_CC(a->sf, tcg_result, tcg_rn, tcg_rm);
} else {
- gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
+ gen_add_CC(a->sf, tcg_result, tcg_rn, tcg_rm);
}
}
- if (sf) {
+ if (a->sf) {
tcg_gen_mov_i64(tcg_rd, tcg_result);
} else {
tcg_gen_ext32u_i64(tcg_rd, tcg_result);
}
+ return true;
}
+TRANS(ADD_r, do_addsub_reg, a, false, false)
+TRANS(SUB_r, do_addsub_reg, a, true, false)
+TRANS(ADDS_r, do_addsub_reg, a, false, true)
+TRANS(SUBS_r, do_addsub_reg, a, true, true)
+
/* Data-processing (3 source)
*
* 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
@@ -8348,15 +8329,6 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
int op3 = extract32(insn, 10, 6);
if (!op1) {
- if (op2 & 8) {
- if (op2 & 1) {
- goto do_unallocated;
- } else {
- /* Add/sub (shifted register) */
- disas_add_sub_reg(s, insn);
- }
- return;
- }
goto do_unallocated;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index b4ccad34fb..4d422a7191 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -718,7 +718,7 @@ XPACD 1 10 11010110 00001 010001 11111 rd:5
# Logical (shifted reg)
&logic_shift rd rn rm sf sa st n
-@logic_shift sf:1 .. ..... st:2 n:1 rm:5 sa:6 rn:5 rd:5
+@logic_shift sf:1 .. ..... st:2 n:1 rm:5 sa:6 rn:5 rd:5 &logic_shift
AND_r . 00 01010 .. . ..... ...... ..... ..... @logic_shift
ORR_r . 01 01010 .. . ..... ...... ..... ..... @logic_shift
@@ -726,6 +726,15 @@ EOR_r . 10 01010 .. . ..... ...... ..... ..... @logic_shift
ANDS_r . 11 01010 .. . ..... ...... ..... ..... @logic_shift
# Add/subtract (shifted reg)
+
+&addsub_shift rd rn rm sf sa st
+@addsub_shift sf:1 .. ..... st:2 . rm:5 sa:6 rn:5 rd:5 &addsub_shift
+
+ADD_r . 00 01011 .. 0 ..... ...... ..... ..... @addsub_shift
+SUB_r . 10 01011 .. 0 ..... ...... ..... ..... @addsub_shift
+ADDS_r . 01 01011 .. 0 ..... ...... ..... ..... @addsub_shift
+SUBS_r . 11 01011 .. 0 ..... ...... ..... ..... @addsub_shift
+
# Add/subtract (extended reg)
&addsub_ext rd rn rm sf sa st
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 13/67] target/arm: Convert disas_add_sub_reg to decodetree
2024-12-01 15:05 ` [PATCH 13/67] target/arm: Convert disas_add_sub_reg " Richard Henderson
@ 2024-12-05 17:45 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-05 17:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:15, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This includes ADD, SUB, ADDS, SUBS (shifted register).
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index b4ccad34fb..4d422a7191 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -718,7 +718,7 @@ XPACD 1 10 11010110 00001 010001 11111 rd:5
> # Logical (shifted reg)
>
> &logic_shift rd rn rm sf sa st n
> -@logic_shift sf:1 .. ..... st:2 n:1 rm:5 sa:6 rn:5 rd:5
> +@logic_shift sf:1 .. ..... st:2 n:1 rm:5 sa:6 rn:5 rd:5 &logic_shift
I think this change needed to be in some previous patch.
>
> AND_r . 00 01010 .. . ..... ...... ..... ..... @logic_shift
> ORR_r . 01 01010 .. . ..... ...... ..... ..... @logic_shift
> @@ -726,6 +726,15 @@ EOR_r . 10 01010 .. . ..... ...... ..... ..... @logic_shift
> ANDS_r . 11 01010 .. . ..... ...... ..... ..... @logic_shift
>
> # Add/subtract (shifted reg)
> +
> +&addsub_shift rd rn rm sf sa st
> +@addsub_shift sf:1 .. ..... st:2 . rm:5 sa:6 rn:5 rd:5 &addsub_shift
> +
> +ADD_r . 00 01011 .. 0 ..... ...... ..... ..... @addsub_shift
> +SUB_r . 10 01011 .. 0 ..... ...... ..... ..... @addsub_shift
> +ADDS_r . 01 01011 .. 0 ..... ...... ..... ..... @addsub_shift
> +SUBS_r . 11 01011 .. 0 ..... ...... ..... ..... @addsub_shift
> +
> # Add/subtract (extended reg)
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 14/67] target/arm: Convert disas_data_proc_3src to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (12 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 13/67] target/arm: Convert disas_add_sub_reg " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 17:55 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 15/67] target/arm: Convert disas_adc_sbc " Richard Henderson
` (53 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes MADD, MSUB, SMADDL, SMSUBL, UMADDL, UMSUBL, SMULH, UMULH.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 119 ++++++++++++---------------------
target/arm/tcg/a64.decode | 16 +++++
2 files changed, 59 insertions(+), 76 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index d570bbb696..99ff787c61 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7955,98 +7955,68 @@ TRANS(SUB_r, do_addsub_reg, a, true, false)
TRANS(ADDS_r, do_addsub_reg, a, false, true)
TRANS(SUBS_r, do_addsub_reg, a, true, true)
-/* Data-processing (3 source)
- *
- * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
- * +--+------+-----------+------+------+----+------+------+------+
- * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
- * +--+------+-----------+------+------+----+------+------+------+
- */
-static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
+static bool do_mulh(DisasContext *s, arg_rrr *a,
+ void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int ra = extract32(insn, 10, 5);
- int rm = extract32(insn, 16, 5);
- int op_id = (extract32(insn, 29, 3) << 4) |
- (extract32(insn, 21, 3) << 1) |
- extract32(insn, 15, 1);
- bool sf = extract32(insn, 31, 1);
- bool is_sub = extract32(op_id, 0, 1);
- bool is_high = extract32(op_id, 2, 1);
- bool is_signed = false;
- TCGv_i64 tcg_op1;
- TCGv_i64 tcg_op2;
- TCGv_i64 tcg_tmp;
+ TCGv_i64 discard = tcg_temp_new_i64();
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
+ TCGv_i64 tcg_rm = cpu_reg(s, a->rm);
- /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
- switch (op_id) {
- case 0x42: /* SMADDL */
- case 0x43: /* SMSUBL */
- case 0x44: /* SMULH */
- is_signed = true;
- break;
- case 0x0: /* MADD (32bit) */
- case 0x1: /* MSUB (32bit) */
- case 0x40: /* MADD (64bit) */
- case 0x41: /* MSUB (64bit) */
- case 0x4a: /* UMADDL */
- case 0x4b: /* UMSUBL */
- case 0x4c: /* UMULH */
- break;
- default:
- unallocated_encoding(s);
- return;
- }
+ fn(discard, tcg_rd, tcg_rn, tcg_rm);
+ return true;
+}
- if (is_high) {
- TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */
- TCGv_i64 tcg_rd = cpu_reg(s, rd);
- TCGv_i64 tcg_rn = cpu_reg(s, rn);
- TCGv_i64 tcg_rm = cpu_reg(s, rm);
+TRANS(SMULH, do_mulh, a, tcg_gen_muls2_i64)
+TRANS(UMULH, do_mulh, a, tcg_gen_mulu2_i64)
- if (is_signed) {
- tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
- } else {
- tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
- }
- return;
- }
+static bool do_muladd(DisasContext *s, arg_rrrr *a,
+ bool sf, bool is_sub, MemOp mop)
+{
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ TCGv_i64 tcg_op1, tcg_op2;
- tcg_op1 = tcg_temp_new_i64();
- tcg_op2 = tcg_temp_new_i64();
- tcg_tmp = tcg_temp_new_i64();
-
- if (op_id < 0x42) {
- tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn));
- tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm));
+ if (mop == MO_64) {
+ tcg_op1 = cpu_reg(s, a->rn);
+ tcg_op2 = cpu_reg(s, a->rm);
} else {
- if (is_signed) {
- tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn));
- tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm));
- } else {
- tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn));
- tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm));
- }
+ tcg_op1 = tcg_temp_new_i64();
+ tcg_op2 = tcg_temp_new_i64();
+ tcg_gen_ext_i64(tcg_op1, cpu_reg(s, a->rn), mop);
+ tcg_gen_ext_i64(tcg_op2, cpu_reg(s, a->rm), mop);
}
- if (ra == 31 && !is_sub) {
+ if (a->ra == 31 && !is_sub) {
/* Special-case MADD with rA == XZR; it is the standard MUL alias */
- tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2);
+ tcg_gen_mul_i64(tcg_rd, tcg_op1, tcg_op2);
} else {
+ TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+ TCGv_i64 tcg_ra = cpu_reg(s, a->ra);
+
tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2);
if (is_sub) {
- tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
+ tcg_gen_sub_i64(tcg_rd, tcg_ra, tcg_tmp);
} else {
- tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
+ tcg_gen_add_i64(tcg_rd, tcg_ra, tcg_tmp);
}
}
if (!sf) {
- tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd));
+ tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
+ return true;
}
+TRANS(MADD_w, do_muladd, a, false, false, MO_64)
+TRANS(MSUB_w, do_muladd, a, false, true, MO_64)
+TRANS(MADD_x, do_muladd, a, true, false, MO_64)
+TRANS(MSUB_x, do_muladd, a, true, true, MO_64)
+
+TRANS(SMADDL, do_muladd, a, true, false, MO_SL)
+TRANS(SMSUBL, do_muladd, a, true, true, MO_SL)
+TRANS(UMADDL, do_muladd, a, true, false, MO_UL)
+TRANS(UMSUBL, do_muladd, a, true, true, MO_UL)
+
/* Add/subtract (with carry)
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
* +--+--+--+------------------------+------+-------------+------+-----+
@@ -8364,13 +8334,10 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
disas_cond_select(s, insn);
break;
- case 0x8 ... 0xf: /* (3 source) */
- disas_data_proc_3src(s, insn);
- break;
-
default:
do_unallocated:
case 0x6: /* Data-processing */
+ case 0x8 ... 0xf: /* (3 source) */
unallocated_encoding(s);
break;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 4d422a7191..c6609749ae 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -753,6 +753,22 @@ SUBS_ext . 11 01011001 ..... ... ... ..... ..... @addsub_ext
# Conditional select
# Data Processing (3-source)
+&rrrr rd rn rm ra
+@rrrr . .. ........ rm:5 . ra:5 rn:5 rd:5 &rrrr
+
+MADD_w 0 00 11011000 ..... 0 ..... ..... ..... @rrrr
+MSUB_w 0 00 11011000 ..... 1 ..... ..... ..... @rrrr
+MADD_x 1 00 11011000 ..... 0 ..... ..... ..... @rrrr
+MSUB_x 1 00 11011000 ..... 1 ..... ..... ..... @rrrr
+
+SMADDL 1 00 11011001 ..... 0 ..... ..... ..... @rrrr
+SMSUBL 1 00 11011001 ..... 1 ..... ..... ..... @rrrr
+UMADDL 1 00 11011101 ..... 0 ..... ..... ..... @rrrr
+UMSUBL 1 00 11011101 ..... 1 ..... ..... ..... @rrrr
+
+SMULH 1 00 11011010 ..... 0 11111 ..... ..... @rrr
+UMULH 1 00 11011110 ..... 0 11111 ..... ..... @rrr
+
### Cryptographic AES
AESE 01001110 00 10100 00100 10 ..... ..... @r2r_q1e0
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 14/67] target/arm: Convert disas_data_proc_3src to decodetree
2024-12-01 15:05 ` [PATCH 14/67] target/arm: Convert disas_data_proc_3src " Richard Henderson
@ 2024-12-05 17:55 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-05 17:55 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:08, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This includes MADD, MSUB, SMADDL, SMSUBL, UMADDL, UMSUBL, SMULH, UMULH.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 15/67] target/arm: Convert disas_adc_sbc to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (13 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 14/67] target/arm: Convert disas_data_proc_3src " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 17:47 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 16/67] target/arm: Convert RMIF " Richard Henderson
` (52 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes ADC, SBC, ADCS, SBCS.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 43 +++++++++++++---------------------
target/arm/tcg/a64.decode | 6 +++++
2 files changed, 22 insertions(+), 27 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 99ff787c61..d7747fcf57 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8017,42 +8017,34 @@ TRANS(SMSUBL, do_muladd, a, true, true, MO_SL)
TRANS(UMADDL, do_muladd, a, true, false, MO_UL)
TRANS(UMSUBL, do_muladd, a, true, true, MO_UL)
-/* Add/subtract (with carry)
- * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
- * +--+--+--+------------------------+------+-------------+------+-----+
- * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
- * +--+--+--+------------------------+------+-------------+------+-----+
- */
-
-static void disas_adc_sbc(DisasContext *s, uint32_t insn)
+static bool do_adc_sbc(DisasContext *s, arg_rrr_sf *a,
+ bool is_sub, bool setflags)
{
- unsigned int sf, op, setflags, rm, rn, rd;
TCGv_i64 tcg_y, tcg_rn, tcg_rd;
- sf = extract32(insn, 31, 1);
- op = extract32(insn, 30, 1);
- setflags = extract32(insn, 29, 1);
- rm = extract32(insn, 16, 5);
- rn = extract32(insn, 5, 5);
- rd = extract32(insn, 0, 5);
+ tcg_rd = cpu_reg(s, a->rd);
+ tcg_rn = cpu_reg(s, a->rn);
- tcg_rd = cpu_reg(s, rd);
- tcg_rn = cpu_reg(s, rn);
-
- if (op) {
+ if (is_sub) {
tcg_y = tcg_temp_new_i64();
- tcg_gen_not_i64(tcg_y, cpu_reg(s, rm));
+ tcg_gen_not_i64(tcg_y, cpu_reg(s, a->rm));
} else {
- tcg_y = cpu_reg(s, rm);
+ tcg_y = cpu_reg(s, a->rm);
}
if (setflags) {
- gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y);
+ gen_adc_CC(a->sf, tcg_rd, tcg_rn, tcg_y);
} else {
- gen_adc(sf, tcg_rd, tcg_rn, tcg_y);
+ gen_adc(a->sf, tcg_rd, tcg_rn, tcg_y);
}
+ return true;
}
+TRANS(ADC, do_adc_sbc, a, false, false)
+TRANS(SBC, do_adc_sbc, a, true, false)
+TRANS(ADCS, do_adc_sbc, a, false, true)
+TRANS(SBCS, do_adc_sbc, a, true, true)
+
/*
* Rotate right into flags
* 31 30 29 21 15 10 5 4 0
@@ -8305,10 +8297,6 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
switch (op2) {
case 0x0:
switch (op3) {
- case 0x00: /* Add/subtract (with carry) */
- disas_adc_sbc(s, insn);
- break;
-
case 0x01: /* Rotate right into flags */
case 0x21:
disas_rotate_right_into_flags(s, insn);
@@ -8322,6 +8310,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
break;
default:
+ case 0x00: /* Add/subtract (with carry) */
goto do_unallocated;
}
break;
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index c6609749ae..34bff988f7 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -746,6 +746,12 @@ ADDS_ext . 01 01011001 ..... ... ... ..... ..... @addsub_ext
SUBS_ext . 11 01011001 ..... ... ... ..... ..... @addsub_ext
# Add/subtract (carry)
+
+ADC . 00 11010000 ..... 000000 ..... ..... @rrr_sf
+ADCS . 01 11010000 ..... 000000 ..... ..... @rrr_sf
+SBC . 10 11010000 ..... 000000 ..... ..... @rrr_sf
+SBCS . 11 11010000 ..... 000000 ..... ..... @rrr_sf
+
# Rotate right into flags
# Evaluate into flags
# Conditional compare (regster)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 16/67] target/arm: Convert RMIF to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (14 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 15/67] target/arm: Convert disas_adc_sbc " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 9:58 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 17/67] target/arm: Convert SETF8, SETF16 " Richard Henderson
` (51 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 32 +++++++++-----------------------
target/arm/tcg/a64.decode | 3 +++
2 files changed, 12 insertions(+), 23 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index d7747fcf57..1af41e22eb 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8045,30 +8045,18 @@ TRANS(SBC, do_adc_sbc, a, true, false)
TRANS(ADCS, do_adc_sbc, a, false, true)
TRANS(SBCS, do_adc_sbc, a, true, true)
-/*
- * Rotate right into flags
- * 31 30 29 21 15 10 5 4 0
- * +--+--+--+-----------------+--------+-----------+------+--+------+
- * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
- * +--+--+--+-----------------+--------+-----------+------+--+------+
- */
-static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn)
+static bool trans_RMIF(DisasContext *s, arg_RMIF *a)
{
- int mask = extract32(insn, 0, 4);
- int o2 = extract32(insn, 4, 1);
- int rn = extract32(insn, 5, 5);
- int imm6 = extract32(insn, 15, 6);
- int sf_op_s = extract32(insn, 29, 3);
+ int mask = a->mask;
TCGv_i64 tcg_rn;
TCGv_i32 nzcv;
- if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) {
- unallocated_encoding(s);
- return;
+ if (!dc_isar_feature(aa64_condm_4, s)) {
+ return false;
}
- tcg_rn = read_cpu_reg(s, rn, 1);
- tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6);
+ tcg_rn = read_cpu_reg(s, a->rn, 1);
+ tcg_gen_rotri_i64(tcg_rn, tcg_rn, a->imm);
nzcv = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(nzcv, tcg_rn);
@@ -8086,6 +8074,7 @@ static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn)
if (mask & 1) { /* V */
tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0);
}
+ return true;
}
/*
@@ -8297,11 +8286,6 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
switch (op2) {
case 0x0:
switch (op3) {
- case 0x01: /* Rotate right into flags */
- case 0x21:
- disas_rotate_right_into_flags(s, insn);
- break;
-
case 0x02: /* Evaluate into flags */
case 0x12:
case 0x22:
@@ -8311,6 +8295,8 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
default:
case 0x00: /* Add/subtract (with carry) */
+ case 0x01: /* Rotate right into flags */
+ case 0x21:
goto do_unallocated;
}
break;
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 34bff988f7..d13983dffe 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -753,6 +753,9 @@ SBC . 10 11010000 ..... 000000 ..... ..... @rrr_sf
SBCS . 11 11010000 ..... 000000 ..... ..... @rrr_sf
# Rotate right into flags
+
+RMIF 1 01 11010000 imm:6 00001 rn:5 0 mask:4
+
# Evaluate into flags
# Conditional compare (regster)
# Conditional compare (immediate)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 17/67] target/arm: Convert SETF8, SETF16 to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (15 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 16/67] target/arm: Convert RMIF " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 20:28 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 18/67] target/arm: Convert CCMP, CCMN " Richard Henderson
` (50 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 48 +++++-----------------------------
target/arm/tcg/a64.decode | 4 +++
2 files changed, 11 insertions(+), 41 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 1af41e22eb..774689641d 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8077,38 +8077,21 @@ static bool trans_RMIF(DisasContext *s, arg_RMIF *a)
return true;
}
-/*
- * Evaluate into flags
- * 31 30 29 21 15 14 10 5 4 0
- * +--+--+--+-----------------+---------+----+---------+------+--+------+
- * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
- * +--+--+--+-----------------+---------+----+---------+------+--+------+
- */
-static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn)
+static bool do_setf(DisasContext *s, int rn, int shift)
{
- int o3_mask = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int o2 = extract32(insn, 15, 6);
- int sz = extract32(insn, 14, 1);
- int sf_op_s = extract32(insn, 29, 3);
- TCGv_i32 tmp;
- int shift;
+ TCGv_i32 tmp = tcg_temp_new_i32();
- if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd ||
- !dc_isar_feature(aa64_condm_4, s)) {
- unallocated_encoding(s);
- return;
- }
- shift = sz ? 16 : 24; /* SETF16 or SETF8 */
-
- tmp = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn));
tcg_gen_shli_i32(cpu_NF, tmp, shift);
tcg_gen_shli_i32(cpu_VF, tmp, shift - 1);
tcg_gen_mov_i32(cpu_ZF, cpu_NF);
tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF);
+ return true;
}
+TRANS_FEAT(SETF8, aa64_condm_4, do_setf, a->rn, 24)
+TRANS_FEAT(SETF16, aa64_condm_4, do_setf, a->rn, 16)
+
/* Conditional compare (immediate / register)
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
@@ -8277,30 +8260,12 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
{
int op1 = extract32(insn, 28, 1);
int op2 = extract32(insn, 21, 4);
- int op3 = extract32(insn, 10, 6);
if (!op1) {
goto do_unallocated;
}
switch (op2) {
- case 0x0:
- switch (op3) {
- case 0x02: /* Evaluate into flags */
- case 0x12:
- case 0x22:
- case 0x32:
- disas_evaluate_into_flags(s, insn);
- break;
-
- default:
- case 0x00: /* Add/subtract (with carry) */
- case 0x01: /* Rotate right into flags */
- case 0x21:
- goto do_unallocated;
- }
- break;
-
case 0x2: /* Conditional compare */
disas_cc(s, insn); /* both imm and reg forms */
break;
@@ -8311,6 +8276,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
default:
do_unallocated:
+ case 0x0:
case 0x6: /* Data-processing */
case 0x8 ... 0xf: /* (3 source) */
unallocated_encoding(s);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index d13983dffe..1228c41679 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -757,6 +757,10 @@ SBCS . 11 11010000 ..... 000000 ..... ..... @rrr_sf
RMIF 1 01 11010000 imm:6 00001 rn:5 0 mask:4
# Evaluate into flags
+
+SETF8 0 01 11010000 00000 000010 rn:5 01101
+SETF16 0 01 11010000 00000 010010 rn:5 01101
+
# Conditional compare (regster)
# Conditional compare (immediate)
# Conditional select
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 18/67] target/arm: Convert CCMP, CCMN to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (16 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 17/67] target/arm: Convert SETF8, SETF16 " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 20:32 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 19/67] target/arm: Convert disas_cond_select " Richard Henderson
` (49 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 66 +++++++++++-----------------------
target/arm/tcg/a64.decode | 6 ++--
2 files changed, 25 insertions(+), 47 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 774689641d..56a445a3c2 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8092,68 +8092,46 @@ static bool do_setf(DisasContext *s, int rn, int shift)
TRANS_FEAT(SETF8, aa64_condm_4, do_setf, a->rn, 24)
TRANS_FEAT(SETF16, aa64_condm_4, do_setf, a->rn, 16)
-/* Conditional compare (immediate / register)
- * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
- * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
- * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
- * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
- * [1] y [0] [0]
- */
-static void disas_cc(DisasContext *s, uint32_t insn)
+/* CCMP, CCMN */
+static bool trans_CCMP(DisasContext *s, arg_CCMP *a)
{
- unsigned int sf, op, y, cond, rn, nzcv, is_imm;
- TCGv_i32 tcg_t0, tcg_t1, tcg_t2;
- TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
+ TCGv_i32 tcg_t0 = tcg_temp_new_i32();
+ TCGv_i32 tcg_t1 = tcg_temp_new_i32();
+ TCGv_i32 tcg_t2 = tcg_temp_new_i32();
+ TCGv_i64 tcg_tmp = tcg_temp_new_i64();
+ TCGv_i64 tcg_rn, tcg_y;
DisasCompare c;
-
- if (!extract32(insn, 29, 1)) {
- unallocated_encoding(s);
- return;
- }
- if (insn & (1 << 10 | 1 << 4)) {
- unallocated_encoding(s);
- return;
- }
- sf = extract32(insn, 31, 1);
- op = extract32(insn, 30, 1);
- is_imm = extract32(insn, 11, 1);
- y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */
- cond = extract32(insn, 12, 4);
- rn = extract32(insn, 5, 5);
- nzcv = extract32(insn, 0, 4);
+ unsigned nzcv;
/* Set T0 = !COND. */
- tcg_t0 = tcg_temp_new_i32();
- arm_test_cc(&c, cond);
+ arm_test_cc(&c, a->cond);
tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0);
/* Load the arguments for the new comparison. */
- if (is_imm) {
- tcg_y = tcg_temp_new_i64();
- tcg_gen_movi_i64(tcg_y, y);
+ if (a->imm) {
+ tcg_y = tcg_constant_i64(a->y);
} else {
- tcg_y = cpu_reg(s, y);
+ tcg_y = cpu_reg(s, a->y);
}
- tcg_rn = cpu_reg(s, rn);
+ tcg_rn = cpu_reg(s, a->rn);
/* Set the flags for the new comparison. */
- tcg_tmp = tcg_temp_new_i64();
- if (op) {
- gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y);
+ if (a->op) {
+ gen_sub_CC(a->sf, tcg_tmp, tcg_rn, tcg_y);
} else {
- gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y);
+ gen_add_CC(a->sf, tcg_tmp, tcg_rn, tcg_y);
}
- /* If COND was false, force the flags to #nzcv. Compute two masks
+ /*
+ * If COND was false, force the flags to #nzcv. Compute two masks
* to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
* For tcg hosts that support ANDC, we can make do with just T1.
* In either case, allow the tcg optimizer to delete any unused mask.
*/
- tcg_t1 = tcg_temp_new_i32();
- tcg_t2 = tcg_temp_new_i32();
tcg_gen_neg_i32(tcg_t1, tcg_t0);
tcg_gen_subi_i32(tcg_t2, tcg_t0, 1);
+ nzcv = a->nzcv;
if (nzcv & 8) { /* N */
tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1);
} else {
@@ -8190,6 +8168,7 @@ static void disas_cc(DisasContext *s, uint32_t insn)
tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2);
}
}
+ return true;
}
/* Conditional select
@@ -8266,10 +8245,6 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
}
switch (op2) {
- case 0x2: /* Conditional compare */
- disas_cc(s, insn); /* both imm and reg forms */
- break;
-
case 0x4: /* Conditional select */
disas_cond_select(s, insn);
break;
@@ -8277,6 +8252,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
default:
do_unallocated:
case 0x0:
+ case 0x2: /* Conditional compare */
case 0x6: /* Data-processing */
case 0x8 ... 0xf: /* (3 source) */
unallocated_encoding(s);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 1228c41679..b339adee6f 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -761,8 +761,10 @@ RMIF 1 01 11010000 imm:6 00001 rn:5 0 mask:4
SETF8 0 01 11010000 00000 000010 rn:5 01101
SETF16 0 01 11010000 00000 010010 rn:5 01101
-# Conditional compare (regster)
-# Conditional compare (immediate)
+# Conditional compare
+
+CCMP sf:1 op:1 1 11010010 y:5 cond:4 imm:1 0 rn:5 0 nzcv:4
+
# Conditional select
# Data Processing (3-source)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 19/67] target/arm: Convert disas_cond_select to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (17 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 18/67] target/arm: Convert CCMP, CCMN " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 20:34 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 20/67] target/arm: Introduce fp_access_check_scalar_hsd Richard Henderson
` (48 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes CSEL, CSINC, CSINV, CSNEG. Remove disas_data_proc_reg,
as these were the last insns decoded by that function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 84 ++++++----------------------------
target/arm/tcg/a64.decode | 3 ++
2 files changed, 17 insertions(+), 70 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 56a445a3c2..9c6365f5ef 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8171,39 +8171,17 @@ static bool trans_CCMP(DisasContext *s, arg_CCMP *a)
return true;
}
-/* Conditional select
- * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
- * +----+----+---+-----------------+------+------+-----+------+------+
- * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
- * +----+----+---+-----------------+------+------+-----+------+------+
- */
-static void disas_cond_select(DisasContext *s, uint32_t insn)
+static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
{
- unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
- TCGv_i64 tcg_rd, zero;
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ TCGv_i64 zero = tcg_constant_i64(0);
DisasCompare64 c;
- if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
- /* S == 1 or op2<1> == 1 */
- unallocated_encoding(s);
- return;
- }
- sf = extract32(insn, 31, 1);
- else_inv = extract32(insn, 30, 1);
- rm = extract32(insn, 16, 5);
- cond = extract32(insn, 12, 4);
- else_inc = extract32(insn, 10, 1);
- rn = extract32(insn, 5, 5);
- rd = extract32(insn, 0, 5);
+ a64_test_cc(&c, a->cond);
- tcg_rd = cpu_reg(s, rd);
-
- a64_test_cc(&c, cond);
- zero = tcg_constant_i64(0);
-
- if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
+ if (a->rn == 31 && a->rm == 31 && (a->else_inc ^ a->else_inv)) {
/* CSET & CSETM. */
- if (else_inv) {
+ if (a->else_inv) {
tcg_gen_negsetcond_i64(tcg_invert_cond(c.cond),
tcg_rd, c.value, zero);
} else {
@@ -8211,53 +8189,23 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
tcg_rd, c.value, zero);
}
} else {
- TCGv_i64 t_true = cpu_reg(s, rn);
- TCGv_i64 t_false = read_cpu_reg(s, rm, 1);
- if (else_inv && else_inc) {
+ TCGv_i64 t_true = cpu_reg(s, a->rn);
+ TCGv_i64 t_false = read_cpu_reg(s, a->rm, 1);
+
+ if (a->else_inv && a->else_inc) {
tcg_gen_neg_i64(t_false, t_false);
- } else if (else_inv) {
+ } else if (a->else_inv) {
tcg_gen_not_i64(t_false, t_false);
- } else if (else_inc) {
+ } else if (a->else_inc) {
tcg_gen_addi_i64(t_false, t_false, 1);
}
tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
}
- if (!sf) {
+ if (!a->sf) {
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
-}
-
-/*
- * Data processing - register
- * 31 30 29 28 25 21 20 16 10 0
- * +--+---+--+---+-------+-----+-------+-------+---------+
- * | |op0| |op1| 1 0 1 | op2 | | op3 | |
- * +--+---+--+---+-------+-----+-------+-------+---------+
- */
-static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
-{
- int op1 = extract32(insn, 28, 1);
- int op2 = extract32(insn, 21, 4);
-
- if (!op1) {
- goto do_unallocated;
- }
-
- switch (op2) {
- case 0x4: /* Conditional select */
- disas_cond_select(s, insn);
- break;
-
- default:
- do_unallocated:
- case 0x0:
- case 0x2: /* Conditional compare */
- case 0x6: /* Data-processing */
- case 0x8 ... 0xf: /* (3 source) */
- unallocated_encoding(s);
- break;
- }
+ return true;
}
static void handle_fp_compare(DisasContext *s, int size,
@@ -11212,10 +11160,6 @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype)
static void disas_a64_legacy(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 25, 4)) {
- case 0x5:
- case 0xd: /* Data processing - register */
- disas_data_proc_reg(s, insn);
- break;
case 0x7:
case 0xf: /* Data processing - SIMD and floating point */
disas_data_proc_simd_fp(s, insn);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index b339adee6f..3bc2767106 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -766,6 +766,9 @@ SETF16 0 01 11010000 00000 010010 rn:5 01101
CCMP sf:1 op:1 1 11010010 y:5 cond:4 imm:1 0 rn:5 0 nzcv:4
# Conditional select
+
+CSEL sf:1 else_inv:1 011010100 rm:5 cond:4 0 else_inc:1 rn:5 rd:5
+
# Data Processing (3-source)
&rrrr rd rn rm ra
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 20/67] target/arm: Introduce fp_access_check_scalar_hsd
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (18 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 19/67] target/arm: Convert disas_cond_select " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 20:37 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 21/67] target/arm: Introduce fp_access_check_vector_hsd Richard Henderson
` (47 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Provide a simple way to check for float64, float32,
and float16 support, as well as the fpu enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 62 ++++++++++++++++++----------------
1 file changed, 32 insertions(+), 30 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 9c6365f5ef..4e47b8a804 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1239,6 +1239,27 @@ static bool fp_access_check(DisasContext *s)
return true;
}
+/*
+ * Return <0 for non-supported element sizes, with MO_16 controlled by
+ * FEAT_FP16; return 0 for fp disabled; otherwise return >0 for success.
+ */
+static int fp_access_check_scalar_hsd(DisasContext *s, MemOp esz)
+{
+ switch (esz) {
+ case MO_64:
+ case MO_32:
+ break;
+ case MO_16:
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ return fp_access_check(s);
+}
+
/*
* Check that SVE access is enabled. If it is, return true.
* If not, emit code to generate an appropriate exception and return false.
@@ -6628,22 +6649,10 @@ static bool trans_FCSEL(DisasContext *s, arg_FCSEL *a)
{
TCGv_i64 t_true, t_false;
DisasCompare64 c;
+ int check = fp_access_check_scalar_hsd(s, a->esz);
- switch (a->esz) {
- case MO_32:
- case MO_64:
- break;
- case MO_16:
- if (!dc_isar_feature(aa64_fp16, s)) {
- return false;
- }
- break;
- default:
- return false;
- }
-
- if (!fp_access_check(s)) {
- return true;
+ if (check <= 0) {
+ return check == 0;
}
/* Zero extend sreg & hreg inputs to 64 bits now. */
@@ -6894,22 +6903,15 @@ TRANS(FMINV_s, do_fp_reduction, a, gen_helper_vfp_mins)
static bool trans_FMOVI_s(DisasContext *s, arg_FMOVI_s *a)
{
- switch (a->esz) {
- case MO_32:
- case MO_64:
- break;
- case MO_16:
- if (!dc_isar_feature(aa64_fp16, s)) {
- return false;
- }
- break;
- default:
- return false;
- }
- if (fp_access_check(s)) {
- uint64_t imm = vfp_expand_imm(a->esz, a->imm);
- write_fp_dreg(s, a->rd, tcg_constant_i64(imm));
+ int check = fp_access_check_scalar_hsd(s, a->esz);
+ uint64_t imm;
+
+ if (check <= 0) {
+ return check == 0;
}
+
+ imm = vfp_expand_imm(a->esz, a->imm);
+ write_fp_dreg(s, a->rd, tcg_constant_i64(imm));
return true;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 21/67] target/arm: Introduce fp_access_check_vector_hsd
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (19 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 20/67] target/arm: Introduce fp_access_check_scalar_hsd Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 20:37 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 22/67] target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree Richard Henderson
` (46 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Provide a simple way to check for float64, float32, and float16
support vs vector width, as well as the fpu enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 135 +++++++++++++--------------------
1 file changed, 54 insertions(+), 81 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 4e47b8a804..4611ae4ade 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1260,6 +1260,28 @@ static int fp_access_check_scalar_hsd(DisasContext *s, MemOp esz)
return fp_access_check(s);
}
+/* Likewise, but vector MO_64 must have two elements. */
+static int fp_access_check_vector_hsd(DisasContext *s, bool is_q, MemOp esz)
+{
+ switch (esz) {
+ case MO_64:
+ if (!is_q) {
+ return -1;
+ }
+ break;
+ case MO_32:
+ break;
+ case MO_16:
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ return fp_access_check(s);
+}
+
/*
* Check that SVE access is enabled. If it is, return true.
* If not, emit code to generate an appropriate exception and return false.
@@ -5420,27 +5442,14 @@ static bool do_fp3_vector(DisasContext *s, arg_qrrr_e *a, int data,
gen_helper_gvec_3_ptr * const fns[3])
{
MemOp esz = a->esz;
+ int check = fp_access_check_vector_hsd(s, a->q, esz);
- switch (esz) {
- case MO_64:
- if (!a->q) {
- return false;
- }
- break;
- case MO_32:
- break;
- case MO_16:
- if (!dc_isar_feature(aa64_fp16, s)) {
- return false;
- }
- break;
- default:
- return false;
- }
- if (fp_access_check(s)) {
- gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm,
- esz == MO_16, data, fns[esz - 1]);
+ if (check <= 0) {
+ return check == 0;
}
+
+ gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm,
+ esz == MO_16, data, fns[esz - 1]);
return true;
}
@@ -5768,34 +5777,24 @@ TRANS_FEAT(FCADD_270, aa64_fcma, do_fp3_vector, a, 1, f_vector_fcadd)
static bool trans_FCMLA_v(DisasContext *s, arg_FCMLA_v *a)
{
- gen_helper_gvec_4_ptr *fn;
+ static gen_helper_gvec_4_ptr * const fn[] = {
+ [MO_16] = gen_helper_gvec_fcmlah,
+ [MO_32] = gen_helper_gvec_fcmlas,
+ [MO_64] = gen_helper_gvec_fcmlad,
+ };
+ int check;
if (!dc_isar_feature(aa64_fcma, s)) {
return false;
}
- switch (a->esz) {
- case MO_64:
- if (!a->q) {
- return false;
- }
- fn = gen_helper_gvec_fcmlad;
- break;
- case MO_32:
- fn = gen_helper_gvec_fcmlas;
- break;
- case MO_16:
- if (!dc_isar_feature(aa64_fp16, s)) {
- return false;
- }
- fn = gen_helper_gvec_fcmlah;
- break;
- default:
- return false;
- }
- if (fp_access_check(s)) {
- gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
- a->esz == MO_16, a->rot, fn);
+
+ check = fp_access_check_vector_hsd(s, a->q, a->esz);
+ if (check <= 0) {
+ return check == 0;
}
+
+ gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
+ a->esz == MO_16, a->rot, fn[a->esz]);
return true;
}
@@ -6337,27 +6336,14 @@ static bool do_fp3_vector_idx(DisasContext *s, arg_qrrx_e *a,
gen_helper_gvec_3_ptr * const fns[3])
{
MemOp esz = a->esz;
+ int check = fp_access_check_vector_hsd(s, a->q, esz);
- switch (esz) {
- case MO_64:
- if (!a->q) {
- return false;
- }
- break;
- case MO_32:
- break;
- case MO_16:
- if (!dc_isar_feature(aa64_fp16, s)) {
- return false;
- }
- break;
- default:
- g_assert_not_reached();
- }
- if (fp_access_check(s)) {
- gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm,
- esz == MO_16, a->idx, fns[esz - 1]);
+ if (check <= 0) {
+ return check == 0;
}
+
+ gen_gvec_op3_fpst(s, a->q, a->rd, a->rn, a->rm,
+ esz == MO_16, a->idx, fns[esz - 1]);
return true;
}
@@ -6383,28 +6369,15 @@ static bool do_fmla_vector_idx(DisasContext *s, arg_qrrx_e *a, bool neg)
gen_helper_gvec_fmla_idx_d,
};
MemOp esz = a->esz;
+ int check = fp_access_check_vector_hsd(s, a->q, esz);
- switch (esz) {
- case MO_64:
- if (!a->q) {
- return false;
- }
- break;
- case MO_32:
- break;
- case MO_16:
- if (!dc_isar_feature(aa64_fp16, s)) {
- return false;
- }
- break;
- default:
- g_assert_not_reached();
- }
- if (fp_access_check(s)) {
- gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
- esz == MO_16, (a->idx << 1) | neg,
- fns[esz - 1]);
+ if (check <= 0) {
+ return check == 0;
}
+
+ gen_gvec_op4_fpst(s, a->q, a->rd, a->rn, a->rm, a->rd,
+ esz == MO_16, (a->idx << 1) | neg,
+ fns[esz - 1]);
return true;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 22/67] target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (20 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 21/67] target/arm: Introduce fp_access_check_vector_hsd Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 21:21 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 23/67] target/arm: Convert FMOV, FABS, FNEG (scalar) " Richard Henderson
` (45 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 287 +++++++++++++--------------------
target/arm/tcg/a64.decode | 8 +
2 files changed, 116 insertions(+), 179 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 4611ae4ade..2d3566e45c 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -6888,6 +6888,110 @@ static bool trans_FMOVI_s(DisasContext *s, arg_FMOVI_s *a)
return true;
}
+/*
+ * Floating point compare, conditional compare
+ */
+
+static void handle_fp_compare(DisasContext *s, int size,
+ unsigned int rn, unsigned int rm,
+ bool cmp_with_zero, bool signal_all_nans)
+{
+ TCGv_i64 tcg_flags = tcg_temp_new_i64();
+ TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+
+ if (size == MO_64) {
+ TCGv_i64 tcg_vn, tcg_vm;
+
+ tcg_vn = read_fp_dreg(s, rn);
+ if (cmp_with_zero) {
+ tcg_vm = tcg_constant_i64(0);
+ } else {
+ tcg_vm = read_fp_dreg(s, rm);
+ }
+ if (signal_all_nans) {
+ gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+ } else {
+ gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+ }
+ } else {
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
+
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
+ if (cmp_with_zero) {
+ tcg_gen_movi_i32(tcg_vm, 0);
+ } else {
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
+ }
+
+ switch (size) {
+ case MO_32:
+ if (signal_all_nans) {
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+ } else {
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+ }
+ break;
+ case MO_16:
+ if (signal_all_nans) {
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+ } else {
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+
+ gen_set_nzcv(tcg_flags);
+}
+
+/* FCMP, FCMPE */
+static bool trans_FCMP(DisasContext *s, arg_FCMP *a)
+{
+ int check;
+
+ if (a->z && a->rm != 0) {
+ return false;
+ }
+ check = fp_access_check_scalar_hsd(s, a->esz);
+ if (check <= 0) {
+ return check == 0;
+ }
+
+ handle_fp_compare(s, a->esz, a->rn, a->rm, a->z, a->e);
+ return true;
+}
+
+/* FCCMP, FCCMPE */
+static bool trans_FCCMP(DisasContext *s, arg_FCCMP *a)
+{
+ TCGLabel *label_continue = NULL;
+ int check = fp_access_check_scalar_hsd(s, a->esz);
+
+ if (check <= 0) {
+ return check == 0;
+ }
+
+ if (a->cond < 0x0e) { /* not always */
+ TCGLabel *label_match = gen_new_label();
+ label_continue = gen_new_label();
+ arm_gen_test_cc(a->cond, label_match);
+ /* nomatch: */
+ gen_set_nzcv(tcg_constant_i64(a->nzcv << 28));
+ tcg_gen_br(label_continue);
+ gen_set_label(label_match);
+ }
+
+ handle_fp_compare(s, a->esz, a->rn, a->rm, false, a->e);
+
+ if (label_continue) {
+ gen_set_label(label_continue);
+ }
+ return true;
+}
+
/*
* Advanced SIMD Modified Immediate
*/
@@ -8183,174 +8287,6 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
return true;
}
-static void handle_fp_compare(DisasContext *s, int size,
- unsigned int rn, unsigned int rm,
- bool cmp_with_zero, bool signal_all_nans)
-{
- TCGv_i64 tcg_flags = tcg_temp_new_i64();
- TCGv_ptr fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
-
- if (size == MO_64) {
- TCGv_i64 tcg_vn, tcg_vm;
-
- tcg_vn = read_fp_dreg(s, rn);
- if (cmp_with_zero) {
- tcg_vm = tcg_constant_i64(0);
- } else {
- tcg_vm = read_fp_dreg(s, rm);
- }
- if (signal_all_nans) {
- gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
- } else {
- gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
- }
- } else {
- TCGv_i32 tcg_vn = tcg_temp_new_i32();
- TCGv_i32 tcg_vm = tcg_temp_new_i32();
-
- read_vec_element_i32(s, tcg_vn, rn, 0, size);
- if (cmp_with_zero) {
- tcg_gen_movi_i32(tcg_vm, 0);
- } else {
- read_vec_element_i32(s, tcg_vm, rm, 0, size);
- }
-
- switch (size) {
- case MO_32:
- if (signal_all_nans) {
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
- } else {
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
- }
- break;
- case MO_16:
- if (signal_all_nans) {
- gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
- } else {
- gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
- }
- break;
- default:
- g_assert_not_reached();
- }
- }
-
- gen_set_nzcv(tcg_flags);
-}
-
-/* Floating point compare
- * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
- * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
- * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
- * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
- */
-static void disas_fp_compare(DisasContext *s, uint32_t insn)
-{
- unsigned int mos, type, rm, op, rn, opc, op2r;
- int size;
-
- mos = extract32(insn, 29, 3);
- type = extract32(insn, 22, 2);
- rm = extract32(insn, 16, 5);
- op = extract32(insn, 14, 2);
- rn = extract32(insn, 5, 5);
- opc = extract32(insn, 3, 2);
- op2r = extract32(insn, 0, 3);
-
- if (mos || op || op2r) {
- unallocated_encoding(s);
- return;
- }
-
- switch (type) {
- case 0:
- size = MO_32;
- break;
- case 1:
- size = MO_64;
- break;
- case 3:
- size = MO_16;
- if (dc_isar_feature(aa64_fp16, s)) {
- break;
- }
- /* fallthru */
- default:
- unallocated_encoding(s);
- return;
- }
-
- if (!fp_access_check(s)) {
- return;
- }
-
- handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
-}
-
-/* Floating point conditional compare
- * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
- * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
- * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
- * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
- */
-static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
-{
- unsigned int mos, type, rm, cond, rn, op, nzcv;
- TCGLabel *label_continue = NULL;
- int size;
-
- mos = extract32(insn, 29, 3);
- type = extract32(insn, 22, 2);
- rm = extract32(insn, 16, 5);
- cond = extract32(insn, 12, 4);
- rn = extract32(insn, 5, 5);
- op = extract32(insn, 4, 1);
- nzcv = extract32(insn, 0, 4);
-
- if (mos) {
- unallocated_encoding(s);
- return;
- }
-
- switch (type) {
- case 0:
- size = MO_32;
- break;
- case 1:
- size = MO_64;
- break;
- case 3:
- size = MO_16;
- if (dc_isar_feature(aa64_fp16, s)) {
- break;
- }
- /* fallthru */
- default:
- unallocated_encoding(s);
- return;
- }
-
- if (!fp_access_check(s)) {
- return;
- }
-
- if (cond < 0x0e) { /* not always */
- TCGLabel *label_match = gen_new_label();
- label_continue = gen_new_label();
- arm_gen_test_cc(cond, label_match);
- /* nomatch: */
- gen_set_nzcv(tcg_constant_i64(nzcv << 28));
- tcg_gen_br(label_continue);
- gen_set_label(label_match);
- }
-
- handle_fp_compare(s, size, rn, rm, false, op);
-
- if (cond < 0x0e) {
- gen_set_label(label_continue);
- }
-}
-
/* Floating-point data-processing (1 source) - half precision */
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
{
@@ -9107,16 +9043,9 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
disas_fp_fixed_conv(s, insn);
} else {
switch (extract32(insn, 10, 2)) {
- case 1:
- /* Floating point conditional compare */
- disas_fp_ccomp(s, insn);
- break;
- case 2:
- /* Floating point data-processing (2 source) */
- unallocated_encoding(s); /* in decodetree */
- break;
- case 3:
- /* Floating point conditional select */
+ case 1: /* Floating point conditional compare */
+ case 2: /* Floating point data-processing (2 source) */
+ case 3: /* Floating point conditional select */
unallocated_encoding(s); /* in decodetree */
break;
case 0:
@@ -9127,7 +9056,7 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
break;
case 1: /* [15:12] == xx10 */
/* Floating point compare */
- disas_fp_compare(s, insn);
+ unallocated_encoding(s); /* in decodetree */
break;
case 2: /* [15:12] == x100 */
/* Floating point data-processing (1 source) */
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 3bc2767106..928e69da69 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1325,6 +1325,14 @@ FMINV_s 0110 1110 10 11000 01111 10 ..... ..... @rr_q1e2
FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=%esz_hsd
+# Floating-point Compare
+
+FCMP 00011110 .. 1 rm:5 001000 rn:5 e:1 z:1 000 esz=%esz_hsd
+
+# Floating-point Conditional Compare
+
+FCCMP 00011110 .. 1 rm:5 cond:4 01 rn:5 e:1 nzcv:4 esz=%esz_hsd
+
# Advanced SIMD Modified Immediate / Shift by Immediate
%abcdefgh 16:3 5:5
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 22/67] target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree
2024-12-01 15:05 ` [PATCH 22/67] target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree Richard Henderson
@ 2024-12-05 21:21 ` Peter Maydell
2024-12-05 21:27 ` Peter Maydell
0 siblings, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-05 21:21 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:17, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 287 +++++++++++++--------------------
> target/arm/tcg/a64.decode | 8 +
> 2 files changed, 116 insertions(+), 179 deletions(-)
> +/* FCMP, FCMPE */
> +static bool trans_FCMP(DisasContext *s, arg_FCMP *a)
> +{
> + int check;
> +
> + if (a->z && a->rm != 0) {
> + return false;
We did not check this case before, and the pseudocode in the
Arm ARM doesn't check it either (there's a comment for the rm
field that says "ignored when opc<0> == '1'").
> + }
> + check = fp_access_check_scalar_hsd(s, a->esz);
> + if (check <= 0) {
> + return check == 0;
> + }
> +
> + handle_fp_compare(s, a->esz, a->rn, a->rm, a->z, a->e);
> + return true;
> +}
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 22/67] target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree
2024-12-05 21:21 ` Peter Maydell
@ 2024-12-05 21:27 ` Peter Maydell
2024-12-06 1:31 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-05 21:27 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Thu, 5 Dec 2024 at 21:21, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Sun, 1 Dec 2024 at 15:17, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> > ---
> > target/arm/tcg/translate-a64.c | 287 +++++++++++++--------------------
> > target/arm/tcg/a64.decode | 8 +
> > 2 files changed, 116 insertions(+), 179 deletions(-)
>
>
> > +/* FCMP, FCMPE */
> > +static bool trans_FCMP(DisasContext *s, arg_FCMP *a)
> > +{
> > + int check;
> > +
> > + if (a->z && a->rm != 0) {
> > + return false;
>
> We did not check this case before, and the pseudocode in the
> Arm ARM doesn't check it either (there's a comment for the rm
> field that says "ignored when opc<0> == '1'").
...this probably falls under the "RES0 UNPREDICTABLE" handling,
but "ignore the field" is permitted for that. If we really want
to change our choice of UNPREDICTABLE here I think we should do
it separately from this refactoring.
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 22/67] target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree
2024-12-05 21:27 ` Peter Maydell
@ 2024-12-06 1:31 ` Richard Henderson
0 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-06 1:31 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 12/5/24 15:27, Peter Maydell wrote:
> On Thu, 5 Dec 2024 at 21:21, Peter Maydell <peter.maydell@linaro.org> wrote:
>>
>> On Sun, 1 Dec 2024 at 15:17, Richard Henderson
>> <richard.henderson@linaro.org> wrote:
>>>
>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>> target/arm/tcg/translate-a64.c | 287 +++++++++++++--------------------
>>> target/arm/tcg/a64.decode | 8 +
>>> 2 files changed, 116 insertions(+), 179 deletions(-)
>>
>>
>>> +/* FCMP, FCMPE */
>>> +static bool trans_FCMP(DisasContext *s, arg_FCMP *a)
>>> +{
>>> + int check;
>>> +
>>> + if (a->z && a->rm != 0) {
>>> + return false;
>>
>> We did not check this case before, and the pseudocode in the
>> Arm ARM doesn't check it either (there's a comment for the rm
>> field that says "ignored when opc<0> == '1'").
>
> ...this probably falls under the "RES0 UNPREDICTABLE" handling,
> but "ignore the field" is permitted for that. If we really want
> to change our choice of UNPREDICTABLE here I think we should do
> it separately from this refactoring.
Fair. I've removed it for now.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 23/67] target/arm: Convert FMOV, FABS, FNEG (scalar) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (21 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 22/67] target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 21:12 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt* Richard Henderson
` (44 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 104 ++++++++++++++++++++++-----------
target/arm/tcg/a64.decode | 7 +++
2 files changed, 78 insertions(+), 33 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 2d3566e45c..87731e0be4 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8287,6 +8287,67 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
return true;
}
+typedef struct FPScalar1Int {
+ void (*gen_h)(TCGv_i32, TCGv_i32);
+ void (*gen_s)(TCGv_i32, TCGv_i32);
+ void (*gen_d)(TCGv_i64, TCGv_i64);
+} FPScalar1Int;
+
+static bool do_fp1_scalar_int(DisasContext *s, arg_rr_e *a,
+ const FPScalar1Int *f)
+{
+ switch (a->esz) {
+ case MO_64:
+ if (fp_access_check(s)) {
+ TCGv_i64 t = read_fp_dreg(s, a->rn);
+ f->gen_d(t, t);
+ write_fp_dreg(s, a->rd, t);
+ }
+ break;
+ case MO_32:
+ if (fp_access_check(s)) {
+ TCGv_i32 t = read_fp_sreg(s, a->rn);
+ f->gen_s(t, t);
+ write_fp_sreg(s, a->rd, t);
+ }
+ break;
+ case MO_16:
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ return false;
+ }
+ if (fp_access_check(s)) {
+ TCGv_i32 t = read_fp_hreg(s, a->rn);
+ f->gen_h(t, t);
+ write_fp_sreg(s, a->rd, t);
+ }
+ break;
+ default:
+ return false;
+ }
+ return true;
+}
+
+static const FPScalar1Int f_scalar_fmov = {
+ tcg_gen_mov_i32,
+ tcg_gen_mov_i32,
+ tcg_gen_mov_i64,
+};
+TRANS(FMOV_s, do_fp1_scalar_int, a, &f_scalar_fmov)
+
+static const FPScalar1Int f_scalar_fabs = {
+ gen_vfp_absh,
+ gen_vfp_abss,
+ gen_vfp_absd,
+};
+TRANS(FABS_s, do_fp1_scalar_int, a, &f_scalar_fabs)
+
+static const FPScalar1Int f_scalar_fneg = {
+ gen_vfp_negh,
+ gen_vfp_negs,
+ gen_vfp_negd,
+};
+TRANS(FNEG_s, do_fp1_scalar_int, a, &f_scalar_fneg)
+
/* Floating-point data-processing (1 source) - half precision */
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
{
@@ -8295,15 +8356,6 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
TCGv_i32 tcg_res = tcg_temp_new_i32();
switch (opcode) {
- case 0x0: /* FMOV */
- tcg_gen_mov_i32(tcg_res, tcg_op);
- break;
- case 0x1: /* FABS */
- gen_vfp_absh(tcg_res, tcg_op);
- break;
- case 0x2: /* FNEG */
- gen_vfp_negh(tcg_res, tcg_op);
- break;
case 0x3: /* FSQRT */
fpst = fpstatus_ptr(FPST_FPCR_F16);
gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
@@ -8331,6 +8383,9 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
break;
default:
+ case 0x0: /* FMOV */
+ case 0x1: /* FABS */
+ case 0x2: /* FNEG */
g_assert_not_reached();
}
@@ -8349,15 +8404,6 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
tcg_res = tcg_temp_new_i32();
switch (opcode) {
- case 0x0: /* FMOV */
- tcg_gen_mov_i32(tcg_res, tcg_op);
- goto done;
- case 0x1: /* FABS */
- gen_vfp_abss(tcg_res, tcg_op);
- goto done;
- case 0x2: /* FNEG */
- gen_vfp_negs(tcg_res, tcg_op);
- goto done;
case 0x3: /* FSQRT */
gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env);
goto done;
@@ -8393,6 +8439,9 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
gen_fpst = gen_helper_frint64_s;
break;
default:
+ case 0x0: /* FMOV */
+ case 0x1: /* FABS */
+ case 0x2: /* FNEG */
g_assert_not_reached();
}
@@ -8417,22 +8466,10 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
TCGv_ptr fpst;
int rmode = -1;
- switch (opcode) {
- case 0x0: /* FMOV */
- gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0);
- return;
- }
-
tcg_op = read_fp_dreg(s, rn);
tcg_res = tcg_temp_new_i64();
switch (opcode) {
- case 0x1: /* FABS */
- gen_vfp_absd(tcg_res, tcg_op);
- goto done;
- case 0x2: /* FNEG */
- gen_vfp_negd(tcg_res, tcg_op);
- goto done;
case 0x3: /* FSQRT */
gen_helper_vfp_sqrtd(tcg_res, tcg_op, tcg_env);
goto done;
@@ -8465,6 +8502,9 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
gen_fpst = gen_helper_frint64_d;
break;
default:
+ case 0x0: /* FMOV */
+ case 0x1: /* FABS */
+ case 0x2: /* FNEG */
g_assert_not_reached();
}
@@ -10881,13 +10921,11 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x7b: /* FCVTZU */
gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
break;
- case 0x6f: /* FNEG */
- tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
- break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
default:
+ case 0x6f: /* FNEG */
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 928e69da69..fca64c63c3 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -47,6 +47,7 @@
@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
+@rr_hsd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_hsd
@rrr_b ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=0
@rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1
@@ -1321,6 +1322,12 @@ FMAXV_s 0110 1110 00 11000 01111 10 ..... ..... @rr_q1e2
FMINV_h 0.00 1110 10 11000 01111 10 ..... ..... @qrr_h
FMINV_s 0110 1110 10 11000 01111 10 ..... ..... @rr_q1e2
+# Floating-point data processing (1 source)
+
+FMOV_s 00011110 .. 1 000000 10000 ..... ..... @rr_hsd
+FABS_s 00011110 .. 1 000001 10000 ..... ..... @rr_hsd
+FNEG_s 00011110 .. 1 000010 10000 ..... ..... @rr_hsd
+
# Floating-point Immediate
FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=%esz_hsd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 23/67] target/arm: Convert FMOV, FABS, FNEG (scalar) to decodetree
2024-12-01 15:05 ` [PATCH 23/67] target/arm: Convert FMOV, FABS, FNEG (scalar) " Richard Henderson
@ 2024-12-05 21:12 ` Peter Maydell
2024-12-06 1:52 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-05 21:12 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:16, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 104 ++++++++++++++++++++++-----------
> target/arm/tcg/a64.decode | 7 +++
> 2 files changed, 78 insertions(+), 33 deletions(-)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 2d3566e45c..87731e0be4 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -8287,6 +8287,67 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a)
> return true;
> }
>
> +typedef struct FPScalar1Int {
> + void (*gen_h)(TCGv_i32, TCGv_i32);
> + void (*gen_s)(TCGv_i32, TCGv_i32);
> + void (*gen_d)(TCGv_i64, TCGv_i64);
> +} FPScalar1Int;
> +
> +static bool do_fp1_scalar_int(DisasContext *s, arg_rr_e *a,
> + const FPScalar1Int *f)
> +{
> + switch (a->esz) {
> + case MO_64:
> + if (fp_access_check(s)) {
> + TCGv_i64 t = read_fp_dreg(s, a->rn);
> + f->gen_d(t, t);
> + write_fp_dreg(s, a->rd, t);
> + }
> + break;
> + case MO_32:
> + if (fp_access_check(s)) {
> + TCGv_i32 t = read_fp_sreg(s, a->rn);
> + f->gen_s(t, t);
> + write_fp_sreg(s, a->rd, t);
> + }
> + break;
> + case MO_16:
> + if (!dc_isar_feature(aa64_fp16, s)) {
> + return false;
> + }
> + if (fp_access_check(s)) {
> + TCGv_i32 t = read_fp_hreg(s, a->rn);
> + f->gen_h(t, t);
> + write_fp_sreg(s, a->rd, t);
> + }
> + break;
> + default:
> + return false;
> + }
> + return true;
> +}
> +
> +static const FPScalar1Int f_scalar_fmov = {
> + tcg_gen_mov_i32,
> + tcg_gen_mov_i32,
> + tcg_gen_mov_i64,
> +};
> +TRANS(FMOV_s, do_fp1_scalar_int, a, &f_scalar_fmov)
> +
> +static const FPScalar1Int f_scalar_fabs = {
> + gen_vfp_absh,
> + gen_vfp_abss,
> + gen_vfp_absd,
> +};
> +TRANS(FABS_s, do_fp1_scalar_int, a, &f_scalar_fabs)
> +
> +static const FPScalar1Int f_scalar_fneg = {
> + gen_vfp_negh,
> + gen_vfp_negs,
> + gen_vfp_negd,
> +};
> +TRANS(FNEG_s, do_fp1_scalar_int, a, &f_scalar_fneg)
> +
> /* Floating-point data-processing (1 source) - half precision */
> static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
> {
> @@ -8295,15 +8356,6 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
> TCGv_i32 tcg_res = tcg_temp_new_i32();
>
> switch (opcode) {
> - case 0x0: /* FMOV */
> - tcg_gen_mov_i32(tcg_res, tcg_op);
> - break;
> - case 0x1: /* FABS */
> - gen_vfp_absh(tcg_res, tcg_op);
> - break;
> - case 0x2: /* FNEG */
> - gen_vfp_negh(tcg_res, tcg_op);
> - break;
> case 0x3: /* FSQRT */
> fpst = fpstatus_ptr(FPST_FPCR_F16);
> gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
> @@ -8331,6 +8383,9 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
> gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
> break;
> default:
> + case 0x0: /* FMOV */
> + case 0x1: /* FABS */
> + case 0x2: /* FNEG */
> g_assert_not_reached();
> }
>
In these changes to the "handle this op" functions we make the
function assert if it's passed an op we've converted. But shouldn't
there also be a change which makes the calling function disas_fp_1src()
call unallocated_encoding() for the ops ?
> @@ -8349,15 +8404,6 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
> tcg_res = tcg_temp_new_i32();
>
> switch (opcode) {
> - case 0x0: /* FMOV */
> - tcg_gen_mov_i32(tcg_res, tcg_op);
> - goto done;
> - case 0x1: /* FABS */
> - gen_vfp_abss(tcg_res, tcg_op);
> - goto done;
> - case 0x2: /* FNEG */
> - gen_vfp_negs(tcg_res, tcg_op);
> - goto done;
> case 0x3: /* FSQRT */
> gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env);
> goto done;
> @@ -8393,6 +8439,9 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
> gen_fpst = gen_helper_frint64_s;
> break;
> default:
> + case 0x0: /* FMOV */
> + case 0x1: /* FABS */
> + case 0x2: /* FNEG */
> g_assert_not_reached();
> }
>
> @@ -8417,22 +8466,10 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
> TCGv_ptr fpst;
> int rmode = -1;
>
> - switch (opcode) {
> - case 0x0: /* FMOV */
> - gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0);
> - return;
> - }
> -
> tcg_op = read_fp_dreg(s, rn);
> tcg_res = tcg_temp_new_i64();
>
> switch (opcode) {
> - case 0x1: /* FABS */
> - gen_vfp_absd(tcg_res, tcg_op);
> - goto done;
> - case 0x2: /* FNEG */
> - gen_vfp_negd(tcg_res, tcg_op);
> - goto done;
> case 0x3: /* FSQRT */
> gen_helper_vfp_sqrtd(tcg_res, tcg_op, tcg_env);
> goto done;
> @@ -8465,6 +8502,9 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
> gen_fpst = gen_helper_frint64_d;
> break;
> default:
> + case 0x0: /* FMOV */
> + case 0x1: /* FABS */
> + case 0x2: /* FNEG */
> g_assert_not_reached();
> }
>
> @@ -10881,13 +10921,11 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
> case 0x7b: /* FCVTZU */
> gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
> break;
> - case 0x6f: /* FNEG */
> - tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
> - break;
> case 0x7d: /* FRSQRTE */
> gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
> break;
> default:
> + case 0x6f: /* FNEG */
> g_assert_not_reached();
> }
What's this change about? This bit of decode is not in the area that
corresponds to the new patterns you add to a64.decode.
Is this a bug in our existing decode where we decode something that
should be undef? I think that 0x6f here corresponds to the decode
table in section C4.1.96.6 ("Advanced SIMD scalar two-register
miscellaneous FP16"), where it is U:a:opcode == 1 1 01111. But
in that table that encoding is marked unallocated. A similar
thing is true for case 0x2f FABS and case 07f FSQRT. All three
of these should have set only_in_vector to true and not had the
code handling in the is_scalar branch of the function.
We should fix that bug in a separate patch before we do the
decodetree conversion, I think.
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index 928e69da69..fca64c63c3 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -47,6 +47,7 @@
> @rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
> @rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
> @rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
> +@rr_hsd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_hsd
>
> @rrr_b ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=0
> @rrr_h ........ ... rm:5 ...... rn:5 rd:5 &rrr_e esz=1
> @@ -1321,6 +1322,12 @@ FMAXV_s 0110 1110 00 11000 01111 10 ..... ..... @rr_q1e2
> FMINV_h 0.00 1110 10 11000 01111 10 ..... ..... @qrr_h
> FMINV_s 0110 1110 10 11000 01111 10 ..... ..... @rr_q1e2
>
> +# Floating-point data processing (1 source)
> +
> +FMOV_s 00011110 .. 1 000000 10000 ..... ..... @rr_hsd
> +FABS_s 00011110 .. 1 000001 10000 ..... ..... @rr_hsd
> +FNEG_s 00011110 .. 1 000010 10000 ..... ..... @rr_hsd
> +
> # Floating-point Immediate
>
> FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=%esz_hsd
> --
> 2.43.0
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 23/67] target/arm: Convert FMOV, FABS, FNEG (scalar) to decodetree
2024-12-05 21:12 ` Peter Maydell
@ 2024-12-06 1:52 ` Richard Henderson
2024-12-06 2:34 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-06 1:52 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 12/5/24 15:12, Peter Maydell wrote:
>> @@ -8295,15 +8356,6 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
>> TCGv_i32 tcg_res = tcg_temp_new_i32();
>>
>> switch (opcode) {
>> - case 0x0: /* FMOV */
>> - tcg_gen_mov_i32(tcg_res, tcg_op);
>> - break;
>> - case 0x1: /* FABS */
>> - gen_vfp_absh(tcg_res, tcg_op);
>> - break;
>> - case 0x2: /* FNEG */
>> - gen_vfp_negh(tcg_res, tcg_op);
>> - break;
>> case 0x3: /* FSQRT */
>> fpst = fpstatus_ptr(FPST_FPCR_F16);
>> gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
>> @@ -8331,6 +8383,9 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
>> gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
>> break;
>> default:
>> + case 0x0: /* FMOV */
>> + case 0x1: /* FABS */
>> + case 0x2: /* FNEG */
>> g_assert_not_reached();
>> }
>>
>
> In these changes to the "handle this op" functions we make the
> function assert if it's passed an op we've converted. But shouldn't
> there also be a change which makes the calling function disas_fp_1src()
> call unallocated_encoding() for the ops ?
Yes. I missed that because the line is
case 0x0 ... 0x3:
without the usual set of comments.
>> @@ -10881,13 +10921,11 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
>> case 0x7b: /* FCVTZU */
>> gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
>> break;
>> - case 0x6f: /* FNEG */
>> - tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
>> - break;
>> case 0x7d: /* FRSQRTE */
>> gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
>> break;
>> default:
>> + case 0x6f: /* FNEG */
>> g_assert_not_reached();
>> }
>
> What's this change about? This bit of decode is not in the area that
> corresponds to the new patterns you add to a64.decode.
>
> Is this a bug in our existing decode where we decode something that
> should be undef? I think that 0x6f here corresponds to the decode
> table in section C4.1.96.6 ("Advanced SIMD scalar two-register
> miscellaneous FP16"), where it is U:a:opcode == 1 1 01111. But
> in that table that encoding is marked unallocated. A similar
> thing is true for case 0x2f FABS and case 07f FSQRT. All three
> of these should have set only_in_vector to true and not had the
> code handling in the is_scalar branch of the function.
>
> We should fix that bug in a separate patch before we do the
> decodetree conversion, I think.
You're right. I had thought there was something weird here, in that FNEG was present but
not FABS. The only scalar FNEG is in fp data-processing 1-src.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 23/67] target/arm: Convert FMOV, FABS, FNEG (scalar) to decodetree
2024-12-06 1:52 ` Richard Henderson
@ 2024-12-06 2:34 ` Richard Henderson
0 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-06 2:34 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 12/5/24 19:52, Richard Henderson wrote:
> On 12/5/24 15:12, Peter Maydell wrote:
>>> @@ -8295,15 +8356,6 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int
>>> rd, int rn)
>>> TCGv_i32 tcg_res = tcg_temp_new_i32();
>>>
>>> switch (opcode) {
>>> - case 0x0: /* FMOV */
>>> - tcg_gen_mov_i32(tcg_res, tcg_op);
>>> - break;
>>> - case 0x1: /* FABS */
>>> - gen_vfp_absh(tcg_res, tcg_op);
>>> - break;
>>> - case 0x2: /* FNEG */
>>> - gen_vfp_negh(tcg_res, tcg_op);
>>> - break;
>>> case 0x3: /* FSQRT */
>>> fpst = fpstatus_ptr(FPST_FPCR_F16);
>>> gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
>>> @@ -8331,6 +8383,9 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int
>>> rd, int rn)
>>> gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
>>> break;
>>> default:
>>> + case 0x0: /* FMOV */
>>> + case 0x1: /* FABS */
>>> + case 0x2: /* FNEG */
>>> g_assert_not_reached();
>>> }
>>>
>>
>> In these changes to the "handle this op" functions we make the
>> function assert if it's passed an op we've converted. But shouldn't
>> there also be a change which makes the calling function disas_fp_1src()
>> call unallocated_encoding() for the ops ?
>
> Yes. I missed that because the line is
>
> case 0x0 ... 0x3:
>
> without the usual set of comments.
The next two patches have the same problem. All fixed now.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt*
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (22 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 23/67] target/arm: Convert FMOV, FABS, FNEG (scalar) " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-05 20:44 ` Peter Maydell
2024-12-05 21:20 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 25/67] target/arm: Remove helper_sqrt_f16 Richard Henderson
` (43 subsequent siblings)
67 siblings, 2 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Pass fpstatus not env, like most other fp helpers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 6 +++---
target/arm/tcg/translate-a64.c | 15 +++++++--------
target/arm/tcg/translate-vfp.c | 6 +++---
target/arm/vfp_helper.c | 12 ++++++------
4 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 58919b670e..0a697e752b 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -133,9 +133,9 @@ DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, ptr)
DEF_HELPER_3(vfp_minnumh, f16, f16, f16, ptr)
DEF_HELPER_3(vfp_minnums, f32, f32, f32, ptr)
DEF_HELPER_3(vfp_minnumd, f64, f64, f64, ptr)
-DEF_HELPER_2(vfp_sqrth, f16, f16, env)
-DEF_HELPER_2(vfp_sqrts, f32, f32, env)
-DEF_HELPER_2(vfp_sqrtd, f64, f64, env)
+DEF_HELPER_2(vfp_sqrth, f16, f16, ptr)
+DEF_HELPER_2(vfp_sqrts, f32, f32, ptr)
+DEF_HELPER_2(vfp_sqrtd, f64, f64, ptr)
DEF_HELPER_3(vfp_cmph, void, f16, f16, env)
DEF_HELPER_3(vfp_cmps, void, f32, f32, env)
DEF_HELPER_3(vfp_cmpd, void, f64, f64, env)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 87731e0be4..c976c15b08 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8405,8 +8405,8 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
switch (opcode) {
case 0x3: /* FSQRT */
- gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env);
- goto done;
+ gen_fpst = gen_helper_vfp_sqrts;
+ break;
case 0x6: /* BFCVT */
gen_fpst = gen_helper_bfcvt;
break;
@@ -8454,7 +8454,6 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
gen_fpst(tcg_res, tcg_op, fpst);
}
- done:
write_fp_sreg(s, rd, tcg_res);
}
@@ -8471,8 +8470,8 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
switch (opcode) {
case 0x3: /* FSQRT */
- gen_helper_vfp_sqrtd(tcg_res, tcg_op, tcg_env);
- goto done;
+ gen_fpst = gen_helper_vfp_sqrtd;
+ break;
case 0x8: /* FRINTN */
case 0x9: /* FRINTP */
case 0xa: /* FRINTM */
@@ -8517,7 +8516,6 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
gen_fpst(tcg_res, tcg_op, fpst);
}
- done:
write_fp_dreg(s, rd, tcg_res);
}
@@ -9460,7 +9458,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
gen_vfp_negd(tcg_rd, tcg_rn);
break;
case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, tcg_env);
+ gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, tcg_fpstatus);
break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
@@ -10403,6 +10401,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
return;
case 0x7f: /* FSQRT */
+ need_fpstatus = true;
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
@@ -10632,7 +10631,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
gen_vfp_negs(tcg_res, tcg_op);
break;
case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env);
+ gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index b6fa28a7bf..c160a86e70 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -2424,17 +2424,17 @@ DO_VFP_2OP(VNEG, dp, gen_vfp_negd, aa32_fpdp_v2)
static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm)
{
- gen_helper_vfp_sqrth(vd, vm, tcg_env);
+ gen_helper_vfp_sqrth(vd, vm, fpstatus_ptr(FPST_FPCR_F16));
}
static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
{
- gen_helper_vfp_sqrts(vd, vm, tcg_env);
+ gen_helper_vfp_sqrts(vd, vm, fpstatus_ptr(FPST_FPCR));
}
static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
{
- gen_helper_vfp_sqrtd(vd, vm, tcg_env);
+ gen_helper_vfp_sqrtd(vd, vm, fpstatus_ptr(FPST_FPCR));
}
DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 62638d2b1f..f24992c798 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -314,19 +314,19 @@ VFP_BINOP(minnum)
VFP_BINOP(maxnum)
#undef VFP_BINOP
-dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env)
+dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, void *fpstp)
{
- return float16_sqrt(a, &env->vfp.fp_status_f16);
+ return float16_sqrt(a, fpstp);
}
-float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
+float32 VFP_HELPER(sqrt, s)(float32 a, void *fpstp)
{
- return float32_sqrt(a, &env->vfp.fp_status);
+ return float32_sqrt(a, fpstp);
}
-float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
+float64 VFP_HELPER(sqrt, d)(float64 a, void *fpstp)
{
- return float64_sqrt(a, &env->vfp.fp_status);
+ return float64_sqrt(a, fpstp);
}
static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt*
2024-12-01 15:05 ` [PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt* Richard Henderson
@ 2024-12-05 20:44 ` Peter Maydell
2024-12-06 2:01 ` Richard Henderson
2024-12-05 21:20 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-05 20:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Pass fpstatus not env, like most other fp helpers.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
I have a patch pretty similar to this in my work-in-progress
FEAT_AFP series, because there I wanted it as part of splitting
env->vfp.fp_status into separate A32 and A64 fp_status fields...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* Re: [PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt*
2024-12-05 20:44 ` Peter Maydell
@ 2024-12-06 2:01 ` Richard Henderson
0 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-06 2:01 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 12/5/24 14:44, Peter Maydell wrote:
> On Sun, 1 Dec 2024 at 15:11, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Pass fpstatus not env, like most other fp helpers.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>
> I have a patch pretty similar to this in my work-in-progress
> FEAT_AFP series, because there I wanted it as part of splitting
> env->vfp.fp_status into separate A32 and A64 fp_status fields...
I thought that might be the case. I have additional changes in this area for SME2. I'll
send those out separately this evening, just so we can compare notes.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread
* Re: [PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt*
2024-12-01 15:05 ` [PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt* Richard Henderson
2024-12-05 20:44 ` Peter Maydell
@ 2024-12-05 21:20 ` Philippe Mathieu-Daudé
2024-12-05 21:38 ` Peter Maydell
1 sibling, 1 reply; 147+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-12-05 21:20 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 1/12/24 16:05, Richard Henderson wrote:
> Pass fpstatus not env, like most other fp helpers.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.h | 6 +++---
> target/arm/tcg/translate-a64.c | 15 +++++++--------
> target/arm/tcg/translate-vfp.c | 6 +++---
> target/arm/vfp_helper.c | 12 ++++++------
> 4 files changed, 19 insertions(+), 20 deletions(-)
> @@ -10403,6 +10401,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
> handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
> return;
> case 0x7f: /* FSQRT */
> + need_fpstatus = true;
Should this change be in a different patch?
> if (size == 3 && !is_q) {
> unallocated_encoding(s);
> return;
> }
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt*
2024-12-05 21:20 ` Philippe Mathieu-Daudé
@ 2024-12-05 21:38 ` Peter Maydell
2024-12-05 21:40 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-05 21:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: Richard Henderson, qemu-devel, qemu-arm
On Thu, 5 Dec 2024 at 21:21, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> On 1/12/24 16:05, Richard Henderson wrote:
> > Pass fpstatus not env, like most other fp helpers.
> >
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> > ---
> > target/arm/helper.h | 6 +++---
> > target/arm/tcg/translate-a64.c | 15 +++++++--------
> > target/arm/tcg/translate-vfp.c | 6 +++---
> > target/arm/vfp_helper.c | 12 ++++++------
> > 4 files changed, 19 insertions(+), 20 deletions(-)
>
>
> > @@ -10403,6 +10401,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
> > handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
> > return;
> > case 0x7f: /* FSQRT */
> > + need_fpstatus = true;
>
> Should this change be in a different patch?
No, this is correct. It tells the common code in this function
that it needs to set up tcg_fpstatus, because in the next change
in a later switch() in this function:
case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env);
+ gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_fpstatus);
break;
we will now want to use it.
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt*
2024-12-05 21:38 ` Peter Maydell
@ 2024-12-05 21:40 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 147+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-12-05 21:40 UTC (permalink / raw)
To: Peter Maydell; +Cc: Richard Henderson, qemu-devel, qemu-arm
On 5/12/24 22:38, Peter Maydell wrote:
> On Thu, 5 Dec 2024 at 21:21, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>>
>> On 1/12/24 16:05, Richard Henderson wrote:
>>> Pass fpstatus not env, like most other fp helpers.
>>>
>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>> target/arm/helper.h | 6 +++---
>>> target/arm/tcg/translate-a64.c | 15 +++++++--------
>>> target/arm/tcg/translate-vfp.c | 6 +++---
>>> target/arm/vfp_helper.c | 12 ++++++------
>>> 4 files changed, 19 insertions(+), 20 deletions(-)
>>
>>
>>> @@ -10403,6 +10401,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>>> handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
>>> return;
>>> case 0x7f: /* FSQRT */
>>> + need_fpstatus = true;
>>
>> Should this change be in a different patch?
>
> No, this is correct. It tells the common code in this function
> that it needs to set up tcg_fpstatus, because in the next change
> in a later switch() in this function:
>
> case 0x7f: /* FSQRT */
> - gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env);
> + gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_fpstatus);
> break;
>
> we will now want to use it.
Oh now I see, not obvious. Thanks for the explanation!
Phil.
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 25/67] target/arm: Remove helper_sqrt_f16
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (23 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 24/67] target/arm: Pass fpstatus to vfp_sqrt* Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-04 8:51 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 26/67] target/arm: Convert FSQRT (scalar) to decodetree Richard Henderson
` (42 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This function is identical with helper_vfp_sqrth.
Replace all uses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/helper-a64.h | 1 -
target/arm/tcg/helper-a64.c | 11 -----------
target/arm/tcg/translate-a64.c | 4 ++--
3 files changed, 2 insertions(+), 14 deletions(-)
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
index 481007bf39..203b7b7ac8 100644
--- a/target/arm/tcg/helper-a64.h
+++ b/target/arm/tcg/helper-a64.h
@@ -80,7 +80,6 @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
-DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
DEF_HELPER_2(exception_return, void, env, i64)
DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64)
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 8f42a28d07..3f4d7b9aba 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -915,17 +915,6 @@ illegal_return:
"resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc);
}
-/*
- * Square Root and Reciprocal square root
- */
-
-uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
-{
- float_status *s = fpstp;
-
- return float16_sqrt(a, s);
-}
-
void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
{
uintptr_t ra = GETPC();
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index c976c15b08..4d945f2d5b 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8358,7 +8358,7 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
switch (opcode) {
case 0x3: /* FSQRT */
fpst = fpstatus_ptr(FPST_FPCR_F16);
- gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
+ gen_helper_vfp_sqrth(tcg_res, tcg_op, fpst);
break;
case 0x8: /* FRINTN */
case 0x9: /* FRINTP */
@@ -10977,7 +10977,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x7f: /* FSQRT */
- gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
+ gen_helper_vfp_sqrth(tcg_res, tcg_op, tcg_fpstatus);
break;
default:
g_assert_not_reached();
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 26/67] target/arm: Convert FSQRT (scalar) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (24 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 25/67] target/arm: Remove helper_sqrt_f16 Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 13:19 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 27/67] target/arm: Convert FRINT[NPMSAXI] " Richard Henderson
` (41 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 70 +++++++++++++++++++++++++++++-----
target/arm/tcg/a64.decode | 1 +
2 files changed, 61 insertions(+), 10 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 4d945f2d5b..750db921cd 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8348,6 +8348,63 @@ static const FPScalar1Int f_scalar_fneg = {
};
TRANS(FNEG_s, do_fp1_scalar_int, a, &f_scalar_fneg)
+typedef struct FPScalar1 {
+ void (*gen_h)(TCGv_i32, TCGv_i32, TCGv_ptr);
+ void (*gen_s)(TCGv_i32, TCGv_i32, TCGv_ptr);
+ void (*gen_d)(TCGv_i64, TCGv_i64, TCGv_ptr);
+} FPScalar1;
+
+static bool do_fp1_scalar(DisasContext *s, arg_rr_e *a,
+ const FPScalar1 *f, int rmode)
+{
+ TCGv_i32 tcg_rmode = NULL;
+ TCGv_ptr fpst;
+ TCGv_i64 t64;
+ TCGv_i32 t32;
+ int check = fp_access_check_scalar_hsd(s, a->esz);
+
+ if (check <= 0) {
+ return check == 0;
+ }
+
+ fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ if (rmode >= 0) {
+ tcg_rmode = gen_set_rmode(rmode, fpst);
+ }
+
+ switch (a->esz) {
+ case MO_64:
+ t64 = read_fp_dreg(s, a->rn);
+ f->gen_d(t64, t64, fpst);
+ write_fp_dreg(s, a->rd, t64);
+ break;
+ case MO_32:
+ t32 = read_fp_sreg(s, a->rn);
+ f->gen_s(t32, t32, fpst);
+ write_fp_sreg(s, a->rd, t32);
+ break;
+ case MO_16:
+ t32 = read_fp_hreg(s, a->rn);
+ f->gen_h(t32, t32, fpst);
+ write_fp_sreg(s, a->rd, t32);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (rmode >= 0) {
+ gen_restore_rmode(tcg_rmode, fpst);
+ }
+ return true;
+}
+
+static const FPScalar1 f_scalar_fsqrt = {
+ gen_helper_vfp_sqrth,
+ gen_helper_vfp_sqrts,
+ gen_helper_vfp_sqrtd,
+};
+TRANS(FSQRT_s, do_fp1_scalar, a, &f_scalar_fsqrt, -1)
+
/* Floating-point data-processing (1 source) - half precision */
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
{
@@ -8356,10 +8413,6 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
TCGv_i32 tcg_res = tcg_temp_new_i32();
switch (opcode) {
- case 0x3: /* FSQRT */
- fpst = fpstatus_ptr(FPST_FPCR_F16);
- gen_helper_vfp_sqrth(tcg_res, tcg_op, fpst);
- break;
case 0x8: /* FRINTN */
case 0x9: /* FRINTP */
case 0xa: /* FRINTM */
@@ -8386,6 +8439,7 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
case 0x0: /* FMOV */
case 0x1: /* FABS */
case 0x2: /* FNEG */
+ case 0x3: /* FSQRT */
g_assert_not_reached();
}
@@ -8404,9 +8458,6 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
tcg_res = tcg_temp_new_i32();
switch (opcode) {
- case 0x3: /* FSQRT */
- gen_fpst = gen_helper_vfp_sqrts;
- break;
case 0x6: /* BFCVT */
gen_fpst = gen_helper_bfcvt;
break;
@@ -8442,6 +8493,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
case 0x0: /* FMOV */
case 0x1: /* FABS */
case 0x2: /* FNEG */
+ case 0x3: /* FSQRT */
g_assert_not_reached();
}
@@ -8469,9 +8521,6 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
tcg_res = tcg_temp_new_i64();
switch (opcode) {
- case 0x3: /* FSQRT */
- gen_fpst = gen_helper_vfp_sqrtd;
- break;
case 0x8: /* FRINTN */
case 0x9: /* FRINTP */
case 0xa: /* FRINTM */
@@ -8504,6 +8553,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
case 0x0: /* FMOV */
case 0x1: /* FABS */
case 0x2: /* FNEG */
+ case 0x3: /* FSQRT */
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index fca64c63c3..9e5ea14683 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1327,6 +1327,7 @@ FMINV_s 0110 1110 10 11000 01111 10 ..... ..... @rr_q1e2
FMOV_s 00011110 .. 1 000000 10000 ..... ..... @rr_hsd
FABS_s 00011110 .. 1 000001 10000 ..... ..... @rr_hsd
FNEG_s 00011110 .. 1 000010 10000 ..... ..... @rr_hsd
+FSQRT_s 00011110 .. 1 000011 10000 ..... ..... @rr_hsd
# Floating-point Immediate
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 27/67] target/arm: Convert FRINT[NPMSAXI] (scalar) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (25 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 26/67] target/arm: Convert FSQRT (scalar) to decodetree Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 13:23 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 28/67] target/arm: Convert BFCVT " Richard Henderson
` (40 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove handle_fp_1src_half as these were the last insns
decoded by that function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 107 ++++++++++-----------------------
target/arm/tcg/a64.decode | 8 +++
2 files changed, 39 insertions(+), 76 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 750db921cd..e8842012ea 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8405,46 +8405,24 @@ static const FPScalar1 f_scalar_fsqrt = {
};
TRANS(FSQRT_s, do_fp1_scalar, a, &f_scalar_fsqrt, -1)
-/* Floating-point data-processing (1 source) - half precision */
-static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
-{
- TCGv_ptr fpst = NULL;
- TCGv_i32 tcg_op = read_fp_hreg(s, rn);
- TCGv_i32 tcg_res = tcg_temp_new_i32();
+static const FPScalar1 f_scalar_frint = {
+ gen_helper_advsimd_rinth,
+ gen_helper_rints,
+ gen_helper_rintd,
+};
+TRANS(FRINTN_s, do_fp1_scalar, a, &f_scalar_frint, FPROUNDING_TIEEVEN)
+TRANS(FRINTP_s, do_fp1_scalar, a, &f_scalar_frint, FPROUNDING_POSINF)
+TRANS(FRINTM_s, do_fp1_scalar, a, &f_scalar_frint, FPROUNDING_NEGINF)
+TRANS(FRINTZ_s, do_fp1_scalar, a, &f_scalar_frint, FPROUNDING_ZERO)
+TRANS(FRINTA_s, do_fp1_scalar, a, &f_scalar_frint, FPROUNDING_TIEAWAY)
+TRANS(FRINTI_s, do_fp1_scalar, a, &f_scalar_frint, -1)
- switch (opcode) {
- case 0x8: /* FRINTN */
- case 0x9: /* FRINTP */
- case 0xa: /* FRINTM */
- case 0xb: /* FRINTZ */
- case 0xc: /* FRINTA */
- {
- TCGv_i32 tcg_rmode;
-
- fpst = fpstatus_ptr(FPST_FPCR_F16);
- tcg_rmode = gen_set_rmode(opcode & 7, fpst);
- gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
- gen_restore_rmode(tcg_rmode, fpst);
- break;
- }
- case 0xe: /* FRINTX */
- fpst = fpstatus_ptr(FPST_FPCR_F16);
- gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst);
- break;
- case 0xf: /* FRINTI */
- fpst = fpstatus_ptr(FPST_FPCR_F16);
- gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
- break;
- default:
- case 0x0: /* FMOV */
- case 0x1: /* FABS */
- case 0x2: /* FNEG */
- case 0x3: /* FSQRT */
- g_assert_not_reached();
- }
-
- write_fp_sreg(s, rd, tcg_res);
-}
+static const FPScalar1 f_scalar_frintx = {
+ gen_helper_advsimd_rinth_exact,
+ gen_helper_rints_exact,
+ gen_helper_rintd_exact,
+};
+TRANS(FRINTX_s, do_fp1_scalar, a, &f_scalar_frintx, -1)
/* Floating-point data-processing (1 source) - single precision */
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
@@ -8461,20 +8439,6 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
case 0x6: /* BFCVT */
gen_fpst = gen_helper_bfcvt;
break;
- case 0x8: /* FRINTN */
- case 0x9: /* FRINTP */
- case 0xa: /* FRINTM */
- case 0xb: /* FRINTZ */
- case 0xc: /* FRINTA */
- rmode = opcode & 7;
- gen_fpst = gen_helper_rints;
- break;
- case 0xe: /* FRINTX */
- gen_fpst = gen_helper_rints_exact;
- break;
- case 0xf: /* FRINTI */
- gen_fpst = gen_helper_rints;
- break;
case 0x10: /* FRINT32Z */
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_s;
@@ -8494,6 +8458,13 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
case 0x1: /* FABS */
case 0x2: /* FNEG */
case 0x3: /* FSQRT */
+ case 0x8: /* FRINTN */
+ case 0x9: /* FRINTP */
+ case 0xa: /* FRINTM */
+ case 0xb: /* FRINTZ */
+ case 0xc: /* FRINTA */
+ case 0xf: /* FRINTI */
+ case 0xe: /* FRINTX */
g_assert_not_reached();
}
@@ -8521,20 +8492,6 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
tcg_res = tcg_temp_new_i64();
switch (opcode) {
- case 0x8: /* FRINTN */
- case 0x9: /* FRINTP */
- case 0xa: /* FRINTM */
- case 0xb: /* FRINTZ */
- case 0xc: /* FRINTA */
- rmode = opcode & 7;
- gen_fpst = gen_helper_rintd;
- break;
- case 0xe: /* FRINTX */
- gen_fpst = gen_helper_rintd_exact;
- break;
- case 0xf: /* FRINTI */
- gen_fpst = gen_helper_rintd;
- break;
case 0x10: /* FRINT32Z */
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_d;
@@ -8554,6 +8511,13 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
case 0x1: /* FABS */
case 0x2: /* FNEG */
case 0x3: /* FSQRT */
+ case 0x8: /* FRINTN */
+ case 0x9: /* FRINTP */
+ case 0xa: /* FRINTM */
+ case 0xb: /* FRINTZ */
+ case 0xc: /* FRINTA */
+ case 0xf: /* FRINTI */
+ case 0xe: /* FRINTX */
g_assert_not_reached();
}
@@ -8691,15 +8655,6 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
handle_fp_1src_double(s, opcode, rd, rn);
break;
case 3:
- if (!dc_isar_feature(aa64_fp16, s)) {
- goto do_unallocated;
- }
-
- if (!fp_access_check(s)) {
- return;
- }
- handle_fp_1src_half(s, opcode, rd, rn);
- break;
default:
goto do_unallocated;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 9e5ea14683..fbfdf96eb3 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1329,6 +1329,14 @@ FABS_s 00011110 .. 1 000001 10000 ..... ..... @rr_hsd
FNEG_s 00011110 .. 1 000010 10000 ..... ..... @rr_hsd
FSQRT_s 00011110 .. 1 000011 10000 ..... ..... @rr_hsd
+FRINTN_s 00011110 .. 1 001000 10000 ..... ..... @rr_hsd
+FRINTP_s 00011110 .. 1 001001 10000 ..... ..... @rr_hsd
+FRINTM_s 00011110 .. 1 001010 10000 ..... ..... @rr_hsd
+FRINTZ_s 00011110 .. 1 001011 10000 ..... ..... @rr_hsd
+FRINTA_s 00011110 .. 1 001100 10000 ..... ..... @rr_hsd
+FRINTX_s 00011110 .. 1 001110 10000 ..... ..... @rr_hsd
+FRINTI_s 00011110 .. 1 001111 10000 ..... ..... @rr_hsd
+
# Floating-point Immediate
FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=%esz_hsd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 27/67] target/arm: Convert FRINT[NPMSAXI] (scalar) to decodetree
2024-12-01 15:05 ` [PATCH 27/67] target/arm: Convert FRINT[NPMSAXI] " Richard Henderson
@ 2024-12-06 13:23 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 13:23 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:13, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Remove handle_fp_1src_half as these were the last insns
> decoded by that function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 107 ++++++++++-----------------------
> target/arm/tcg/a64.decode | 8 +++
> 2 files changed, 39 insertions(+), 76 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 28/67] target/arm: Convert BFCVT to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (26 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 27/67] target/arm: Convert FRINT[NPMSAXI] " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-03 14:05 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 29/67] target/arm: Convert FRINT{32, 64}[ZX] (scalar) " Richard Henderson
` (39 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 24 ++++++------------------
target/arm/tcg/a64.decode | 3 +++
2 files changed, 9 insertions(+), 18 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index e8842012ea..b713c7d184 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8424,6 +8424,11 @@ static const FPScalar1 f_scalar_frintx = {
};
TRANS(FRINTX_s, do_fp1_scalar, a, &f_scalar_frintx, -1)
+static const FPScalar1 f_scalar_bfcvt = {
+ .gen_s = gen_helper_bfcvt,
+};
+TRANS_FEAT(BFCVT_s, aa64_bf16, do_fp1_scalar, a, &f_scalar_bfcvt, -1)
+
/* Floating-point data-processing (1 source) - single precision */
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
{
@@ -8436,9 +8441,6 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
tcg_res = tcg_temp_new_i32();
switch (opcode) {
- case 0x6: /* BFCVT */
- gen_fpst = gen_helper_bfcvt;
- break;
case 0x10: /* FRINT32Z */
rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_s;
@@ -8458,6 +8460,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
case 0x1: /* FABS */
case 0x2: /* FNEG */
case 0x3: /* FSQRT */
+ case 0x6: /* BFCVT */
case 0x8: /* FRINTN */
case 0x9: /* FRINTP */
case 0xa: /* FRINTM */
@@ -8661,21 +8664,6 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
break;
case 0x6:
- switch (type) {
- case 1: /* BFCVT */
- if (!dc_isar_feature(aa64_bf16, s)) {
- goto do_unallocated;
- }
- if (!fp_access_check(s)) {
- return;
- }
- handle_fp_1src_single(s, opcode, rd, rn);
- break;
- default:
- goto do_unallocated;
- }
- break;
-
default:
do_unallocated:
unallocated_encoding(s);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index fbfdf96eb3..476989c1b4 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -45,6 +45,7 @@
&qrrrr_e q rd rn rm ra esz
@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
+@rr_s ........ ... ..... ...... rn:5 rd:5 &rr_e esz=2
@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
@rr_hsd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_hsd
@@ -1337,6 +1338,8 @@ FRINTA_s 00011110 .. 1 001100 10000 ..... ..... @rr_hsd
FRINTX_s 00011110 .. 1 001110 10000 ..... ..... @rr_hsd
FRINTI_s 00011110 .. 1 001111 10000 ..... ..... @rr_hsd
+BFCVT_s 00011110 10 1 000110 10000 ..... ..... @rr_s
+
# Floating-point Immediate
FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=%esz_hsd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 28/67] target/arm: Convert BFCVT to decodetree
2024-12-01 15:05 ` [PATCH 28/67] target/arm: Convert BFCVT " Richard Henderson
@ 2024-12-03 14:05 ` Peter Maydell
2024-12-03 15:28 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-03 14:05 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 24 ++++++------------------
> target/arm/tcg/a64.decode | 3 +++
> 2 files changed, 9 insertions(+), 18 deletions(-)
>
> @@ -8661,21 +8664,6 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
> break;
>
> case 0x6:
> - switch (type) {
> - case 1: /* BFCVT */
Here we decode BFCVT when the 'ftype' field (bits [23:22]) is 0b01...
> - if (!dc_isar_feature(aa64_bf16, s)) {
> - goto do_unallocated;
> - }
> - if (!fp_access_check(s)) {
> - return;
> - }
> - handle_fp_1src_single(s, opcode, rd, rn);
> - break;
> - default:
> - goto do_unallocated;
> - }
> - break;
> -
> default:
> do_unallocated:
> unallocated_encoding(s);
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index fbfdf96eb3..476989c1b4 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -45,6 +45,7 @@
> &qrrrr_e q rd rn rm ra esz
>
> @rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
> +@rr_s ........ ... ..... ...... rn:5 rd:5 &rr_e esz=2
> @rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
> @rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
> @rr_hsd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_hsd
> @@ -1337,6 +1338,8 @@ FRINTA_s 00011110 .. 1 001100 10000 ..... ..... @rr_hsd
> FRINTX_s 00011110 .. 1 001110 10000 ..... ..... @rr_hsd
> FRINTI_s 00011110 .. 1 001111 10000 ..... ..... @rr_hsd
>
> +BFCVT_s 00011110 10 1 000110 10000 ..... ..... @rr_s
...but this decode pattern has them as 0b10.
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1338,7 +1338,7 @@ FRINTA_s 00011110 .. 1 001100 10000 .....
..... @rr_hsd
FRINTX_s 00011110 .. 1 001110 10000 ..... ..... @rr_hsd
FRINTI_s 00011110 .. 1 001111 10000 ..... ..... @rr_hsd
-BFCVT_s 00011110 10 1 000110 10000 ..... ..... @rr_s
+BFCVT_s 00011110 01 1 000110 10000 ..... ..... @rr_s
# Floating-point Immediate
should fix this.
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 28/67] target/arm: Convert BFCVT to decodetree
2024-12-03 14:05 ` Peter Maydell
@ 2024-12-03 15:28 ` Richard Henderson
0 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-03 15:28 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 12/3/24 08:05, Peter Maydell wrote:
> On Sun, 1 Dec 2024 at 15:11, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/tcg/translate-a64.c | 24 ++++++------------------
>> target/arm/tcg/a64.decode | 3 +++
>> 2 files changed, 9 insertions(+), 18 deletions(-)
>>
>> @@ -8661,21 +8664,6 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
>> break;
>>
>> case 0x6:
>> - switch (type) {
>> - case 1: /* BFCVT */
>
> Here we decode BFCVT when the 'ftype' field (bits [23:22]) is 0b01...
>
>> - if (!dc_isar_feature(aa64_bf16, s)) {
>> - goto do_unallocated;
>> - }
>> - if (!fp_access_check(s)) {
>> - return;
>> - }
>> - handle_fp_1src_single(s, opcode, rd, rn);
>> - break;
>> - default:
>> - goto do_unallocated;
>> - }
>> - break;
>> -
>> default:
>> do_unallocated:
>> unallocated_encoding(s);
>> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
>> index fbfdf96eb3..476989c1b4 100644
>> --- a/target/arm/tcg/a64.decode
>> +++ b/target/arm/tcg/a64.decode
>> @@ -45,6 +45,7 @@
>> &qrrrr_e q rd rn rm ra esz
>>
>> @rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
>> +@rr_s ........ ... ..... ...... rn:5 rd:5 &rr_e esz=2
>> @rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
>> @rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
>> @rr_hsd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_hsd
>> @@ -1337,6 +1338,8 @@ FRINTA_s 00011110 .. 1 001100 10000 ..... ..... @rr_hsd
>> FRINTX_s 00011110 .. 1 001110 10000 ..... ..... @rr_hsd
>> FRINTI_s 00011110 .. 1 001111 10000 ..... ..... @rr_hsd
>>
>> +BFCVT_s 00011110 10 1 000110 10000 ..... ..... @rr_s
>
> ...but this decode pattern has them as 0b10.
>
>
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -1338,7 +1338,7 @@ FRINTA_s 00011110 .. 1 001100 10000 .....
> ..... @rr_hsd
> FRINTX_s 00011110 .. 1 001110 10000 ..... ..... @rr_hsd
> FRINTI_s 00011110 .. 1 001111 10000 ..... ..... @rr_hsd
>
> -BFCVT_s 00011110 10 1 000110 10000 ..... ..... @rr_s
> +BFCVT_s 00011110 01 1 000110 10000 ..... ..... @rr_s
>
> # Floating-point Immediate
>
> should fix this.
Yep, thanks. Fixed.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 29/67] target/arm: Convert FRINT{32, 64}[ZX] (scalar) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (27 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 28/67] target/arm: Convert BFCVT " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 13:25 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 30/67] target/arm: Convert FCVT " Richard Henderson
` (38 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove handle_fp_1src_single and handle_fp_1src_double as
these were the last insns decoded by those functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 150 ++++-----------------------------
target/arm/tcg/a64.decode | 5 ++
2 files changed, 21 insertions(+), 134 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index b713c7d184..679bdd826c 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8429,112 +8429,23 @@ static const FPScalar1 f_scalar_bfcvt = {
};
TRANS_FEAT(BFCVT_s, aa64_bf16, do_fp1_scalar, a, &f_scalar_bfcvt, -1)
-/* Floating-point data-processing (1 source) - single precision */
-static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
-{
- void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr);
- TCGv_i32 tcg_op, tcg_res;
- TCGv_ptr fpst;
- int rmode = -1;
+static const FPScalar1 f_scalar_frint32 = {
+ NULL,
+ gen_helper_frint32_s,
+ gen_helper_frint32_d,
+};
+TRANS_FEAT(FRINT32Z_s, aa64_frint, do_fp1_scalar, a,
+ &f_scalar_frint32, FPROUNDING_ZERO)
+TRANS_FEAT(FRINT32X_s, aa64_frint, do_fp1_scalar, a, &f_scalar_frint32, -1)
- tcg_op = read_fp_sreg(s, rn);
- tcg_res = tcg_temp_new_i32();
-
- switch (opcode) {
- case 0x10: /* FRINT32Z */
- rmode = FPROUNDING_ZERO;
- gen_fpst = gen_helper_frint32_s;
- break;
- case 0x11: /* FRINT32X */
- gen_fpst = gen_helper_frint32_s;
- break;
- case 0x12: /* FRINT64Z */
- rmode = FPROUNDING_ZERO;
- gen_fpst = gen_helper_frint64_s;
- break;
- case 0x13: /* FRINT64X */
- gen_fpst = gen_helper_frint64_s;
- break;
- default:
- case 0x0: /* FMOV */
- case 0x1: /* FABS */
- case 0x2: /* FNEG */
- case 0x3: /* FSQRT */
- case 0x6: /* BFCVT */
- case 0x8: /* FRINTN */
- case 0x9: /* FRINTP */
- case 0xa: /* FRINTM */
- case 0xb: /* FRINTZ */
- case 0xc: /* FRINTA */
- case 0xf: /* FRINTI */
- case 0xe: /* FRINTX */
- g_assert_not_reached();
- }
-
- fpst = fpstatus_ptr(FPST_FPCR);
- if (rmode >= 0) {
- TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
- gen_fpst(tcg_res, tcg_op, fpst);
- gen_restore_rmode(tcg_rmode, fpst);
- } else {
- gen_fpst(tcg_res, tcg_op, fpst);
- }
-
- write_fp_sreg(s, rd, tcg_res);
-}
-
-/* Floating-point data-processing (1 source) - double precision */
-static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
-{
- void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr);
- TCGv_i64 tcg_op, tcg_res;
- TCGv_ptr fpst;
- int rmode = -1;
-
- tcg_op = read_fp_dreg(s, rn);
- tcg_res = tcg_temp_new_i64();
-
- switch (opcode) {
- case 0x10: /* FRINT32Z */
- rmode = FPROUNDING_ZERO;
- gen_fpst = gen_helper_frint32_d;
- break;
- case 0x11: /* FRINT32X */
- gen_fpst = gen_helper_frint32_d;
- break;
- case 0x12: /* FRINT64Z */
- rmode = FPROUNDING_ZERO;
- gen_fpst = gen_helper_frint64_d;
- break;
- case 0x13: /* FRINT64X */
- gen_fpst = gen_helper_frint64_d;
- break;
- default:
- case 0x0: /* FMOV */
- case 0x1: /* FABS */
- case 0x2: /* FNEG */
- case 0x3: /* FSQRT */
- case 0x8: /* FRINTN */
- case 0x9: /* FRINTP */
- case 0xa: /* FRINTM */
- case 0xb: /* FRINTZ */
- case 0xc: /* FRINTA */
- case 0xf: /* FRINTI */
- case 0xe: /* FRINTX */
- g_assert_not_reached();
- }
-
- fpst = fpstatus_ptr(FPST_FPCR);
- if (rmode >= 0) {
- TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
- gen_fpst(tcg_res, tcg_op, fpst);
- gen_restore_rmode(tcg_rmode, fpst);
- } else {
- gen_fpst(tcg_res, tcg_op, fpst);
- }
-
- write_fp_dreg(s, rd, tcg_res);
-}
+static const FPScalar1 f_scalar_frint64 = {
+ NULL,
+ gen_helper_frint64_s,
+ gen_helper_frint64_d,
+};
+TRANS_FEAT(FRINT64Z_s, aa64_frint, do_fp1_scalar, a,
+ &f_scalar_frint64, FPROUNDING_ZERO)
+TRANS_FEAT(FRINT64X_s, aa64_frint, do_fp1_scalar, a, &f_scalar_frint64, -1)
static void handle_fp_fcvt(DisasContext *s, int opcode,
int rd, int rn, int dtype, int ntype)
@@ -8635,35 +8546,6 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
break;
}
- case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
- if (type > 1 || !dc_isar_feature(aa64_frint, s)) {
- goto do_unallocated;
- }
- /* fall through */
- case 0x0 ... 0x3:
- case 0x8 ... 0xc:
- case 0xe ... 0xf:
- /* 32-to-32 and 64-to-64 ops */
- switch (type) {
- case 0:
- if (!fp_access_check(s)) {
- return;
- }
- handle_fp_1src_single(s, opcode, rd, rn);
- break;
- case 1:
- if (!fp_access_check(s)) {
- return;
- }
- handle_fp_1src_double(s, opcode, rd, rn);
- break;
- case 3:
- default:
- goto do_unallocated;
- }
- break;
-
- case 0x6:
default:
do_unallocated:
unallocated_encoding(s);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 476989c1b4..e828834c16 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1340,6 +1340,11 @@ FRINTI_s 00011110 .. 1 001111 10000 ..... ..... @rr_hsd
BFCVT_s 00011110 10 1 000110 10000 ..... ..... @rr_s
+FRINT32Z_s 00011110 0. 1 010000 10000 ..... ..... @rr_sd
+FRINT32X_s 00011110 0. 1 010001 10000 ..... ..... @rr_sd
+FRINT64Z_s 00011110 0. 1 010010 10000 ..... ..... @rr_sd
+FRINT64X_s 00011110 0. 1 010011 10000 ..... ..... @rr_sd
+
# Floating-point Immediate
FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=%esz_hsd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 29/67] target/arm: Convert FRINT{32, 64}[ZX] (scalar) to decodetree
2024-12-01 15:05 ` [PATCH 29/67] target/arm: Convert FRINT{32, 64}[ZX] (scalar) " Richard Henderson
@ 2024-12-06 13:25 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 13:25 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:07, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Remove handle_fp_1src_single and handle_fp_1src_double as
> these were the last insns decoded by those functions.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 150 ++++-----------------------------
> target/arm/tcg/a64.decode | 5 ++
> 2 files changed, 21 insertions(+), 134 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 30/67] target/arm: Convert FCVT (scalar) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (28 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 29/67] target/arm: Convert FRINT{32, 64}[ZX] (scalar) " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 13:32 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 31/67] target/arm: Convert handle_fpfpcvt " Richard Henderson
` (37 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove handle_fp_fcvt and disas_fp_1src as these were
the last insns decoded by those functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 159 ++++++++++++++-------------------
target/arm/tcg/a64.decode | 7 ++
2 files changed, 74 insertions(+), 92 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 679bdd826c..dacc3269b9 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8447,110 +8447,85 @@ TRANS_FEAT(FRINT64Z_s, aa64_frint, do_fp1_scalar, a,
&f_scalar_frint64, FPROUNDING_ZERO)
TRANS_FEAT(FRINT64X_s, aa64_frint, do_fp1_scalar, a, &f_scalar_frint64, -1)
-static void handle_fp_fcvt(DisasContext *s, int opcode,
- int rd, int rn, int dtype, int ntype)
+static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *a)
{
- switch (ntype) {
- case 0x0:
- {
- TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
- if (dtype == 1) {
- /* Single to double */
- TCGv_i64 tcg_rd = tcg_temp_new_i64();
- gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, tcg_env);
- write_fp_dreg(s, rd, tcg_rd);
- } else {
- /* Single to half */
- TCGv_i32 tcg_rd = tcg_temp_new_i32();
- TCGv_i32 ahp = get_ahp_flag();
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+ if (fp_access_check(s)) {
+ TCGv_i32 tcg_rn = read_fp_sreg(s, a->rn);
+ TCGv_i64 tcg_rd = tcg_temp_new_i64();
- gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp);
- /* write_fp_sreg is OK here because top half of tcg_rd is zero */
- write_fp_sreg(s, rd, tcg_rd);
- }
- break;
- }
- case 0x1:
- {
- TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
- TCGv_i32 tcg_rd = tcg_temp_new_i32();
- if (dtype == 0) {
- /* Double to single */
- gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, tcg_env);
- } else {
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
- TCGv_i32 ahp = get_ahp_flag();
- /* Double to half */
- gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp);
- /* write_fp_sreg is OK here because top half of tcg_rd is zero */
- }
- write_fp_sreg(s, rd, tcg_rd);
- break;
- }
- case 0x3:
- {
- TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
- TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_FPCR);
- TCGv_i32 tcg_ahp = get_ahp_flag();
- tcg_gen_ext16u_i32(tcg_rn, tcg_rn);
- if (dtype == 0) {
- /* Half to single */
- TCGv_i32 tcg_rd = tcg_temp_new_i32();
- gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
- write_fp_sreg(s, rd, tcg_rd);
- } else {
- /* Half to double */
- TCGv_i64 tcg_rd = tcg_temp_new_i64();
- gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
- write_fp_dreg(s, rd, tcg_rd);
- }
- break;
- }
- default:
- g_assert_not_reached();
+ gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, tcg_env);
+ write_fp_dreg(s, a->rd, tcg_rd);
}
+ return true;
}
-/* Floating point data-processing (1 source)
- * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
- * +---+---+---+-----------+------+---+--------+-----------+------+------+
- * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
- * +---+---+---+-----------+------+---+--------+-----------+------+------+
- */
-static void disas_fp_1src(DisasContext *s, uint32_t insn)
+static bool trans_FCVT_s_hs(DisasContext *s, arg_rr *a)
{
- int mos = extract32(insn, 29, 3);
- int type = extract32(insn, 22, 2);
- int opcode = extract32(insn, 15, 6);
- int rn = extract32(insn, 5, 5);
- int rd = extract32(insn, 0, 5);
+ if (fp_access_check(s)) {
+ TCGv_i32 tmp = read_fp_sreg(s, a->rn);
+ TCGv_i32 ahp = get_ahp_flag();
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
- if (mos) {
- goto do_unallocated;
+ gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
+ /* write_fp_sreg is OK here because top half of result is zero */
+ write_fp_sreg(s, a->rd, tmp);
}
+ return true;
+}
- switch (opcode) {
- case 0x4: case 0x5: case 0x7:
- {
- /* FCVT between half, single and double precision */
- int dtype = extract32(opcode, 0, 2);
- if (type == 2 || dtype == type) {
- goto do_unallocated;
- }
- if (!fp_access_check(s)) {
- return;
- }
+static bool trans_FCVT_s_sd(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn);
+ TCGv_i32 tcg_rd = tcg_temp_new_i32();
- handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
- break;
+ gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, tcg_env);
+ write_fp_sreg(s, a->rd, tcg_rd);
}
+ return true;
+}
- default:
- do_unallocated:
- unallocated_encoding(s);
- break;
+static bool trans_FCVT_s_hd(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn);
+ TCGv_i32 tcg_rd = tcg_temp_new_i32();
+ TCGv_i32 ahp = get_ahp_flag();
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+
+ gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp);
+ /* write_fp_sreg is OK here because top half of tcg_rd is zero */
+ write_fp_sreg(s, a->rd, tcg_rd);
}
+ return true;
+}
+
+static bool trans_FCVT_s_sh(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i32 tcg_rn = read_fp_hreg(s, a->rn);
+ TCGv_i32 tcg_rd = tcg_temp_new_i32();
+ TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_i32 tcg_ahp = get_ahp_flag();
+
+ gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
+ write_fp_sreg(s, a->rd, tcg_rd);
+ }
+ return true;
+}
+
+static bool trans_FCVT_s_dh(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i32 tcg_rn = read_fp_hreg(s, a->rn);
+ TCGv_i64 tcg_rd = tcg_temp_new_i64();
+ TCGv_ptr tcg_fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_i32 tcg_ahp = get_ahp_flag();
+
+ gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
+ write_fp_dreg(s, a->rd, tcg_rd);
+ }
+ return true;
}
/* Handle floating point <=> fixed point conversions. Note that we can
@@ -8973,7 +8948,7 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
break;
case 2: /* [15:12] == x100 */
/* Floating point data-processing (1 source) */
- disas_fp_1src(s, insn);
+ unallocated_encoding(s); /* in decodetree */
break;
case 3: /* [15:12] == 1000 */
unallocated_encoding(s);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index e828834c16..769aac51e9 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1345,6 +1345,13 @@ FRINT32X_s 00011110 0. 1 010001 10000 ..... ..... @rr_sd
FRINT64Z_s 00011110 0. 1 010010 10000 ..... ..... @rr_sd
FRINT64X_s 00011110 0. 1 010011 10000 ..... ..... @rr_sd
+FCVT_s_ds 00011110 00 1 000101 10000 ..... ..... @rr
+FCVT_s_hs 00011110 00 1 000111 10000 ..... ..... @rr
+FCVT_s_sd 00011110 01 1 000100 10000 ..... ..... @rr
+FCVT_s_hd 00011110 01 1 000111 10000 ..... ..... @rr
+FCVT_s_sh 00011110 11 1 000100 10000 ..... ..... @rr
+FCVT_s_dh 00011110 11 1 000101 10000 ..... ..... @rr
+
# Floating-point Immediate
FMOVI_s 0001 1110 .. 1 imm:8 100 00000 rd:5 esz=%esz_hsd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 30/67] target/arm: Convert FCVT (scalar) to decodetree
2024-12-01 15:05 ` [PATCH 30/67] target/arm: Convert FCVT " Richard Henderson
@ 2024-12-06 13:32 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 13:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:10, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Remove handle_fp_fcvt and disas_fp_1src as these were
> the last insns decoded by those functions.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 159 ++++++++++++++-------------------
> target/arm/tcg/a64.decode | 7 ++
> 2 files changed, 74 insertions(+), 92 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 31/67] target/arm: Convert handle_fpfpcvt to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (29 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 30/67] target/arm: Convert FCVT " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 13:48 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 32/67] target/arm: Convert FJCVTZS " Richard Henderson
` (36 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes SCVTF, UCVTF, FCVT{N,P,M,Z,A}{S,U}.
Remove disas_fp_fixed_conv as those were the last insns
decoded by that function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 391 ++++++++++++++-------------------
target/arm/tcg/a64.decode | 40 ++++
2 files changed, 209 insertions(+), 222 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index dacc3269b9..68bef0963b 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8528,227 +8528,196 @@ static bool trans_FCVT_s_dh(DisasContext *s, arg_rr *a)
return true;
}
-/* Handle floating point <=> fixed point conversions. Note that we can
- * also deal with fp <=> integer conversions as a special case (scale == 64)
- * OPTME: consider handling that special case specially or at least skipping
- * the call to scalbn in the helpers for zero shifts.
- */
-static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
- bool itof, int rmode, int scale, int sf, int type)
+static bool do_cvtf_scalar(DisasContext *s, MemOp esz, int rd, int shift,
+ TCGv_i64 tcg_int, bool is_signed)
{
- bool is_signed = !(opcode & 1);
TCGv_ptr tcg_fpstatus;
TCGv_i32 tcg_shift, tcg_single;
TCGv_i64 tcg_double;
- tcg_fpstatus = fpstatus_ptr(type == 3 ? FPST_FPCR_F16 : FPST_FPCR);
+ tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ tcg_shift = tcg_constant_i32(shift);
- tcg_shift = tcg_constant_i32(64 - scale);
-
- if (itof) {
- TCGv_i64 tcg_int = cpu_reg(s, rn);
- if (!sf) {
- TCGv_i64 tcg_extend = tcg_temp_new_i64();
-
- if (is_signed) {
- tcg_gen_ext32s_i64(tcg_extend, tcg_int);
- } else {
- tcg_gen_ext32u_i64(tcg_extend, tcg_int);
- }
-
- tcg_int = tcg_extend;
+ switch (esz) {
+ case MO_64:
+ tcg_double = tcg_temp_new_i64();
+ if (is_signed) {
+ gen_helper_vfp_sqtod(tcg_double, tcg_int, tcg_shift, tcg_fpstatus);
+ } else {
+ gen_helper_vfp_uqtod(tcg_double, tcg_int, tcg_shift, tcg_fpstatus);
}
+ write_fp_dreg(s, rd, tcg_double);
+ break;
- switch (type) {
- case 1: /* float64 */
- tcg_double = tcg_temp_new_i64();
- if (is_signed) {
- gen_helper_vfp_sqtod(tcg_double, tcg_int,
- tcg_shift, tcg_fpstatus);
- } else {
- gen_helper_vfp_uqtod(tcg_double, tcg_int,
- tcg_shift, tcg_fpstatus);
- }
- write_fp_dreg(s, rd, tcg_double);
- break;
-
- case 0: /* float32 */
- tcg_single = tcg_temp_new_i32();
- if (is_signed) {
- gen_helper_vfp_sqtos(tcg_single, tcg_int,
- tcg_shift, tcg_fpstatus);
- } else {
- gen_helper_vfp_uqtos(tcg_single, tcg_int,
- tcg_shift, tcg_fpstatus);
- }
- write_fp_sreg(s, rd, tcg_single);
- break;
-
- case 3: /* float16 */
- tcg_single = tcg_temp_new_i32();
- if (is_signed) {
- gen_helper_vfp_sqtoh(tcg_single, tcg_int,
- tcg_shift, tcg_fpstatus);
- } else {
- gen_helper_vfp_uqtoh(tcg_single, tcg_int,
- tcg_shift, tcg_fpstatus);
- }
- write_fp_sreg(s, rd, tcg_single);
- break;
-
- default:
- g_assert_not_reached();
+ case MO_32:
+ tcg_single = tcg_temp_new_i32();
+ if (is_signed) {
+ gen_helper_vfp_sqtos(tcg_single, tcg_int, tcg_shift, tcg_fpstatus);
+ } else {
+ gen_helper_vfp_uqtos(tcg_single, tcg_int, tcg_shift, tcg_fpstatus);
}
- } else {
- TCGv_i64 tcg_int = cpu_reg(s, rd);
- TCGv_i32 tcg_rmode;
+ write_fp_sreg(s, rd, tcg_single);
+ break;
- if (extract32(opcode, 2, 1)) {
- /* There are too many rounding modes to all fit into rmode,
- * so FCVTA[US] is a special case.
- */
- rmode = FPROUNDING_TIEAWAY;
+ case MO_16:
+ tcg_single = tcg_temp_new_i32();
+ if (is_signed) {
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int, tcg_shift, tcg_fpstatus);
+ } else {
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int, tcg_shift, tcg_fpstatus);
}
+ write_fp_sreg(s, rd, tcg_single);
+ break;
- tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
-
- switch (type) {
- case 1: /* float64 */
- tcg_double = read_fp_dreg(s, rn);
- if (is_signed) {
- if (!sf) {
- gen_helper_vfp_tosld(tcg_int, tcg_double,
- tcg_shift, tcg_fpstatus);
- } else {
- gen_helper_vfp_tosqd(tcg_int, tcg_double,
- tcg_shift, tcg_fpstatus);
- }
- } else {
- if (!sf) {
- gen_helper_vfp_tould(tcg_int, tcg_double,
- tcg_shift, tcg_fpstatus);
- } else {
- gen_helper_vfp_touqd(tcg_int, tcg_double,
- tcg_shift, tcg_fpstatus);
- }
- }
- if (!sf) {
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
- }
- break;
-
- case 0: /* float32 */
- tcg_single = read_fp_sreg(s, rn);
- if (sf) {
- if (is_signed) {
- gen_helper_vfp_tosqs(tcg_int, tcg_single,
- tcg_shift, tcg_fpstatus);
- } else {
- gen_helper_vfp_touqs(tcg_int, tcg_single,
- tcg_shift, tcg_fpstatus);
- }
- } else {
- TCGv_i32 tcg_dest = tcg_temp_new_i32();
- if (is_signed) {
- gen_helper_vfp_tosls(tcg_dest, tcg_single,
- tcg_shift, tcg_fpstatus);
- } else {
- gen_helper_vfp_touls(tcg_dest, tcg_single,
- tcg_shift, tcg_fpstatus);
- }
- tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
- }
- break;
-
- case 3: /* float16 */
- tcg_single = read_fp_sreg(s, rn);
- if (sf) {
- if (is_signed) {
- gen_helper_vfp_tosqh(tcg_int, tcg_single,
- tcg_shift, tcg_fpstatus);
- } else {
- gen_helper_vfp_touqh(tcg_int, tcg_single,
- tcg_shift, tcg_fpstatus);
- }
- } else {
- TCGv_i32 tcg_dest = tcg_temp_new_i32();
- if (is_signed) {
- gen_helper_vfp_toslh(tcg_dest, tcg_single,
- tcg_shift, tcg_fpstatus);
- } else {
- gen_helper_vfp_toulh(tcg_dest, tcg_single,
- tcg_shift, tcg_fpstatus);
- }
- tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
- }
- break;
-
- default:
- g_assert_not_reached();
- }
-
- gen_restore_rmode(tcg_rmode, tcg_fpstatus);
+ default:
+ g_assert_not_reached();
}
+ return true;
}
-/* Floating point <-> fixed point conversions
- * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
- * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
- * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
- * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
- */
-static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
+static bool do_cvtf_g(DisasContext *s, arg_fcvt *a, bool is_signed)
{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int scale = extract32(insn, 10, 6);
- int opcode = extract32(insn, 16, 3);
- int rmode = extract32(insn, 19, 2);
- int type = extract32(insn, 22, 2);
- bool sbit = extract32(insn, 29, 1);
- bool sf = extract32(insn, 31, 1);
- bool itof;
+ TCGv_i64 tcg_int;
+ int check = fp_access_check_scalar_hsd(s, a->esz);
- if (sbit || (!sf && scale < 32)) {
- unallocated_encoding(s);
- return;
+ if (check <= 0) {
+ return check == 0;
}
- switch (type) {
- case 0: /* float32 */
- case 1: /* float64 */
- break;
- case 3: /* float16 */
- if (dc_isar_feature(aa64_fp16, s)) {
- break;
+ if (a->sf) {
+ tcg_int = cpu_reg(s, a->rn);
+ } else {
+ tcg_int = read_cpu_reg(s, a->rn, true);
+ if (is_signed) {
+ tcg_gen_ext32s_i64(tcg_int, tcg_int);
+ } else {
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
}
- /* fallthru */
- default:
- unallocated_encoding(s);
- return;
}
-
- switch ((rmode << 3) | opcode) {
- case 0x2: /* SCVTF */
- case 0x3: /* UCVTF */
- itof = true;
- break;
- case 0x18: /* FCVTZS */
- case 0x19: /* FCVTZU */
- itof = false;
- break;
- default:
- unallocated_encoding(s);
- return;
- }
-
- if (!fp_access_check(s)) {
- return;
- }
-
- handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type);
+ return do_cvtf_scalar(s, a->esz, a->rd, a->shift, tcg_int, is_signed);
}
+TRANS(SCVTF_g, do_cvtf_g, a, true)
+TRANS(UCVTF_g, do_cvtf_g, a, false)
+
+static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
+ TCGv_i64 tcg_out, int shift, int rn,
+ ARMFPRounding rmode)
+{
+ TCGv_ptr tcg_fpstatus;
+ TCGv_i32 tcg_shift, tcg_rmode, tcg_single;
+
+ tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ tcg_shift = tcg_constant_i32(shift);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
+
+ switch (esz) {
+ case MO_64:
+ read_vec_element(s, tcg_out, rn, 0, MO_64);
+ switch (out) {
+ case MO_64 | MO_SIGN:
+ gen_helper_vfp_tosqd(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
+ break;
+ case MO_64:
+ gen_helper_vfp_touqd(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
+ break;
+ case MO_32 | MO_SIGN:
+ gen_helper_vfp_tosld(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
+ break;
+ case MO_32:
+ gen_helper_vfp_tould(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ case MO_32:
+ tcg_single = read_fp_sreg(s, rn);
+ switch (out) {
+ case MO_64 | MO_SIGN:
+ gen_helper_vfp_tosqs(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
+ break;
+ case MO_64:
+ gen_helper_vfp_touqs(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
+ break;
+ case MO_32 | MO_SIGN:
+ gen_helper_vfp_tosls(tcg_single, tcg_single,
+ tcg_shift, tcg_fpstatus);
+ tcg_gen_extu_i32_i64(tcg_out, tcg_single);
+ break;
+ case MO_32:
+ gen_helper_vfp_touls(tcg_single, tcg_single,
+ tcg_shift, tcg_fpstatus);
+ tcg_gen_extu_i32_i64(tcg_out, tcg_single);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ case MO_16:
+ tcg_single = read_fp_hreg(s, rn);
+ switch (out) {
+ case MO_64 | MO_SIGN:
+ gen_helper_vfp_tosqh(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
+ break;
+ case MO_64:
+ gen_helper_vfp_touqh(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
+ break;
+ case MO_32 | MO_SIGN:
+ gen_helper_vfp_toslh(tcg_single, tcg_single,
+ tcg_shift, tcg_fpstatus);
+ tcg_gen_extu_i32_i64(tcg_out, tcg_single);
+ break;
+ case MO_32:
+ gen_helper_vfp_toulh(tcg_single, tcg_single,
+ tcg_shift, tcg_fpstatus);
+ tcg_gen_extu_i32_i64(tcg_out, tcg_single);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
+}
+
+static bool do_fcvt_g(DisasContext *s, arg_fcvt *a,
+ ARMFPRounding rmode, bool is_signed)
+{
+ TCGv_i64 tcg_int;
+ int check = fp_access_check_scalar_hsd(s, a->esz);
+
+ if (check <= 0) {
+ return check == 0;
+ }
+
+ tcg_int = cpu_reg(s, a->rd);
+ do_fcvt_scalar(s, (a->sf ? MO_64 : MO_32) | (is_signed ? MO_SIGN : 0),
+ a->esz, tcg_int, a->shift, a->rn, rmode);
+
+ if (!a->sf) {
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
+ }
+ return true;
+}
+
+TRANS(FCVTNS_g, do_fcvt_g, a, FPROUNDING_TIEEVEN, true)
+TRANS(FCVTNU_g, do_fcvt_g, a, FPROUNDING_TIEEVEN, false)
+TRANS(FCVTPS_g, do_fcvt_g, a, FPROUNDING_POSINF, true)
+TRANS(FCVTPU_g, do_fcvt_g, a, FPROUNDING_POSINF, false)
+TRANS(FCVTMS_g, do_fcvt_g, a, FPROUNDING_NEGINF, true)
+TRANS(FCVTMU_g, do_fcvt_g, a, FPROUNDING_NEGINF, false)
+TRANS(FCVTZS_g, do_fcvt_g, a, FPROUNDING_ZERO, true)
+TRANS(FCVTZU_g, do_fcvt_g, a, FPROUNDING_ZERO, false)
+TRANS(FCVTAS_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, true)
+TRANS(FCVTAU_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, false)
+
static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
{
/* FMOV: gpr to or from float, double, or top half of quad fp reg,
@@ -8848,33 +8817,11 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
switch (opcode) {
case 2: /* SCVTF */
case 3: /* UCVTF */
- itof = true;
- /* fallthru */
case 4: /* FCVTAS */
case 5: /* FCVTAU */
- if (rmode != 0) {
- goto do_unallocated;
- }
- /* fallthru */
case 0: /* FCVT[NPMZ]S */
case 1: /* FCVT[NPMZ]U */
- switch (type) {
- case 0: /* float32 */
- case 1: /* float64 */
- break;
- case 3: /* float16 */
- if (!dc_isar_feature(aa64_fp16, s)) {
- goto do_unallocated;
- }
- break;
- default:
- goto do_unallocated;
- }
- if (!fp_access_check(s)) {
- return;
- }
- handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
- break;
+ goto do_unallocated;
default:
switch (sf << 7 | type << 5 | rmode << 3 | opcode) {
@@ -8928,7 +8875,7 @@ static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
unallocated_encoding(s); /* in decodetree */
} else if (extract32(insn, 21, 1) == 0) {
/* Floating point to fixed point conversions */
- disas_fp_fixed_conv(s, insn);
+ unallocated_encoding(s); /* in decodetree */
} else {
switch (extract32(insn, 10, 2)) {
case 1: /* Floating point conditional compare */
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 769aac51e9..427924ad95 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1323,6 +1323,46 @@ FMAXV_s 0110 1110 00 11000 01111 10 ..... ..... @rr_q1e2
FMINV_h 0.00 1110 10 11000 01111 10 ..... ..... @qrr_h
FMINV_s 0110 1110 10 11000 01111 10 ..... ..... @rr_q1e2
+# Conversion between floating-point and fixed-point (general register)
+
+&fcvt rd rn esz sf shift
+%fcvt_shift32 10:5 !function=rsub_32
+%fcvt_shift64 10:6 !function=rsub_64
+
+@fcvt32 0 ....... .. ...... 1..... rn:5 rd:5 \
+ &fcvt sf=0 esz=%esz_hsd shift=%fcvt_shift32
+@fcvt64 1 ....... .. ...... ...... rn:5 rd:5 \
+ &fcvt sf=1 esz=%esz_hsd shift=%fcvt_shift64
+
+SCVTF_g . 0011110 .. 000010 ...... ..... ..... @fcvt32
+SCVTF_g . 0011110 .. 000010 ...... ..... ..... @fcvt64
+UCVTF_g . 0011110 .. 000011 ...... ..... ..... @fcvt32
+UCVTF_g . 0011110 .. 000011 ...... ..... ..... @fcvt64
+
+FCVTZS_g . 0011110 .. 011000 ...... ..... ..... @fcvt32
+FCVTZS_g . 0011110 .. 011000 ...... ..... ..... @fcvt64
+FCVTZU_g . 0011110 .. 011001 ...... ..... ..... @fcvt32
+FCVTZU_g . 0011110 .. 011001 ...... ..... ..... @fcvt64
+
+# Conversion between floating-point and integer (general register)
+
+@icvt sf:1 ....... .. ...... ...... rn:5 rd:5 \
+ &fcvt esz=%esz_hsd shift=0
+
+SCVTF_g . 0011110 .. 100010 000000 ..... ..... @icvt
+UCVTF_g . 0011110 .. 100011 000000 ..... ..... @icvt
+
+FCVTNS_g . 0011110 .. 100000 000000 ..... ..... @icvt
+FCVTNU_g . 0011110 .. 100001 000000 ..... ..... @icvt
+FCVTPS_g . 0011110 .. 101000 000000 ..... ..... @icvt
+FCVTPU_g . 0011110 .. 101001 000000 ..... ..... @icvt
+FCVTMS_g . 0011110 .. 110000 000000 ..... ..... @icvt
+FCVTMU_g . 0011110 .. 110001 000000 ..... ..... @icvt
+FCVTZS_g . 0011110 .. 111000 000000 ..... ..... @icvt
+FCVTZU_g . 0011110 .. 111001 000000 ..... ..... @icvt
+FCVTAS_g . 0011110 .. 100100 000000 ..... ..... @icvt
+FCVTAU_g . 0011110 .. 100101 000000 ..... ..... @icvt
+
# Floating-point data processing (1 source)
FMOV_s 00011110 .. 1 000000 10000 ..... ..... @rr_hsd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 31/67] target/arm: Convert handle_fpfpcvt to decodetree
2024-12-01 15:05 ` [PATCH 31/67] target/arm: Convert handle_fpfpcvt " Richard Henderson
@ 2024-12-06 13:48 ` Peter Maydell
2024-12-06 15:10 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 13:48 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:08, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This includes SCVTF, UCVTF, FCVT{N,P,M,Z,A}{S,U}.
> Remove disas_fp_fixed_conv as those were the last insns
> decoded by that function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> +static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
> + TCGv_i64 tcg_out, int shift, int rn,
> + ARMFPRounding rmode)
> +{
> + TCGv_ptr tcg_fpstatus;
> + TCGv_i32 tcg_shift, tcg_rmode, tcg_single;
> +
> + tcg_fpstatus = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
> + tcg_shift = tcg_constant_i32(shift);
> + tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
> +
> + switch (esz) {
> + case MO_64:
> + read_vec_element(s, tcg_out, rn, 0, MO_64);
> + switch (out) {
> + case MO_64 | MO_SIGN:
> + gen_helper_vfp_tosqd(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
> + break;
> + case MO_64:
> + gen_helper_vfp_touqd(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
> + break;
> + case MO_32 | MO_SIGN:
> + gen_helper_vfp_tosld(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
> + break;
> + case MO_32:
> + gen_helper_vfp_tould(tcg_out, tcg_out, tcg_shift, tcg_fpstatus);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> +
> + case MO_32:
> + tcg_single = read_fp_sreg(s, rn);
> + switch (out) {
> + case MO_64 | MO_SIGN:
> + gen_helper_vfp_tosqs(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
> + break;
> + case MO_64:
> + gen_helper_vfp_touqs(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
> + break;
> + case MO_32 | MO_SIGN:
> + gen_helper_vfp_tosls(tcg_single, tcg_single,
> + tcg_shift, tcg_fpstatus);
> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> + break;
> + case MO_32:
> + gen_helper_vfp_touls(tcg_single, tcg_single,
> + tcg_shift, tcg_fpstatus);
> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> +
> + case MO_16:
> + tcg_single = read_fp_hreg(s, rn);
> + switch (out) {
> + case MO_64 | MO_SIGN:
> + gen_helper_vfp_tosqh(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
> + break;
> + case MO_64:
> + gen_helper_vfp_touqh(tcg_out, tcg_single, tcg_shift, tcg_fpstatus);
> + break;
> + case MO_32 | MO_SIGN:
> + gen_helper_vfp_toslh(tcg_single, tcg_single,
> + tcg_shift, tcg_fpstatus);
> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> + break;
> + case MO_32:
> + gen_helper_vfp_toulh(tcg_single, tcg_single,
> + tcg_shift, tcg_fpstatus);
> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + break;
> +
> + default:
> + g_assert_not_reached();
> + }
> +
> + gen_restore_rmode(tcg_rmode, tcg_fpstatus);
> +}
> +
> +static bool do_fcvt_g(DisasContext *s, arg_fcvt *a,
> + ARMFPRounding rmode, bool is_signed)
> +{
> + TCGv_i64 tcg_int;
> + int check = fp_access_check_scalar_hsd(s, a->esz);
> +
> + if (check <= 0) {
> + return check == 0;
> + }
> +
> + tcg_int = cpu_reg(s, a->rd);
> + do_fcvt_scalar(s, (a->sf ? MO_64 : MO_32) | (is_signed ? MO_SIGN : 0),
> + a->esz, tcg_int, a->shift, a->rn, rmode);
> +
> + if (!a->sf) {
> + tcg_gen_ext32u_i64(tcg_int, tcg_int);
For the MO_16 and MO_32 input cases we already did a
zero-extend-to-64-bits inside do_fcvt_scalar().
Maybe we should put the tcg_gen_ext32u_i64() also
inside do_fcvt_scalar() in the cases of MO_64 input
MO_32 output which are the only ones that actually need it?
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 31/67] target/arm: Convert handle_fpfpcvt to decodetree
2024-12-06 13:48 ` Peter Maydell
@ 2024-12-06 15:10 ` Richard Henderson
0 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-06 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 12/6/24 07:48, Peter Maydell wrote:
>> +static bool do_fcvt_g(DisasContext *s, arg_fcvt *a,
>> + ARMFPRounding rmode, bool is_signed)
>> +{
>> + TCGv_i64 tcg_int;
>> + int check = fp_access_check_scalar_hsd(s, a->esz);
>> +
>> + if (check <= 0) {
>> + return check == 0;
>> + }
>> +
>> + tcg_int = cpu_reg(s, a->rd);
>> + do_fcvt_scalar(s, (a->sf ? MO_64 : MO_32) | (is_signed ? MO_SIGN : 0),
>> + a->esz, tcg_int, a->shift, a->rn, rmode);
>> +
>> + if (!a->sf) {
>> + tcg_gen_ext32u_i64(tcg_int, tcg_int);
>
> For the MO_16 and MO_32 input cases we already did a
> zero-extend-to-64-bits inside do_fcvt_scalar().
> Maybe we should put the tcg_gen_ext32u_i64() also
> inside do_fcvt_scalar() in the cases of MO_64 input
> MO_32 output which are the only ones that actually need it?
I thought about that.
(0) In that case the duplicate zero-extend will be optimized away.
(1) I thought it was clearer to retain the !sf test here rather
than rely on a zero-extend elsewhere.
(2) In the scalar vector case, the best method for Vd.H is to clear
the entire vector and only then store the 0th element directly
from the bottom bits of either TCGv_{i32,i64}.
Otherwise we wind up with two zero-extends which cannot be folded:
tcg_gen_ext16u_i32 + tcg_gen_extu_i32_i64 or
tcg_gen_extu_i32_i64 + tcg_gen_ext16u_i64.
Fixing this duplication would require new tcg ops to
extend-and-change-type.
While Vd.S does not suffer the same fate, it's easiest to use
the same method as Vd.H. See patch 55.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 32/67] target/arm: Convert FJCVTZS to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (30 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 31/67] target/arm: Convert handle_fpfpcvt " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 13:51 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 33/67] target/arm: Convert handle_fmov " Richard Henderson
` (35 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 41 +++++++++++++++++-----------------
target/arm/tcg/a64.decode | 2 ++
2 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 68bef0963b..90e1567ad1 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8718,6 +8718,26 @@ TRANS(FCVTZU_g, do_fcvt_g, a, FPROUNDING_ZERO, false)
TRANS(FCVTAS_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, true)
TRANS(FCVTAU_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, false)
+static bool trans_FJCVTZS(DisasContext *s, arg_FJCVTZS *a)
+{
+ if (!dc_isar_feature(aa64_jscvt, s)) {
+ return false;
+ }
+ if (fp_access_check(s)) {
+ TCGv_i64 t = read_fp_dreg(s, a->rn);
+ TCGv_ptr fpstatus = fpstatus_ptr(FPST_FPCR);
+
+ gen_helper_fjcvtzs(t, t, fpstatus);
+
+ tcg_gen_ext32u_i64(cpu_reg(s, a->rd), t);
+ tcg_gen_extrh_i64_i32(cpu_ZF, t);
+ tcg_gen_movi_i32(cpu_CF, 0);
+ tcg_gen_movi_i32(cpu_NF, 0);
+ tcg_gen_movi_i32(cpu_VF, 0);
+ }
+ return true;
+}
+
static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
{
/* FMOV: gpr to or from float, double, or top half of quad fp reg,
@@ -8779,20 +8799,6 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
}
}
-static void handle_fjcvtzs(DisasContext *s, int rd, int rn)
-{
- TCGv_i64 t = read_fp_dreg(s, rn);
- TCGv_ptr fpstatus = fpstatus_ptr(FPST_FPCR);
-
- gen_helper_fjcvtzs(t, t, fpstatus);
-
- tcg_gen_ext32u_i64(cpu_reg(s, rd), t);
- tcg_gen_extrh_i64_i32(cpu_ZF, t);
- tcg_gen_movi_i32(cpu_CF, 0);
- tcg_gen_movi_i32(cpu_NF, 0);
- tcg_gen_movi_i32(cpu_VF, 0);
-}
-
/* Floating point <-> integer conversions
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
@@ -8847,13 +8853,6 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
break;
case 0b00111110: /* FJCVTZS */
- if (!dc_isar_feature(aa64_jscvt, s)) {
- goto do_unallocated;
- } else if (fp_access_check(s)) {
- handle_fjcvtzs(s, rd, rn);
- }
- break;
-
default:
do_unallocated:
unallocated_encoding(s);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 427924ad95..7b83d06d0d 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1363,6 +1363,8 @@ FCVTZU_g . 0011110 .. 111001 000000 ..... ..... @icvt
FCVTAS_g . 0011110 .. 100100 000000 ..... ..... @icvt
FCVTAU_g . 0011110 .. 100101 000000 ..... ..... @icvt
+FJCVTZS 0 0011110 01 111110 000000 ..... ..... @rr
+
# Floating-point data processing (1 source)
FMOV_s 00011110 .. 1 000000 10000 ..... ..... @rr_hsd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 33/67] target/arm: Convert handle_fmov to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (31 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 32/67] target/arm: Convert FJCVTZS " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 14:21 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 34/67] target/arm: Convert SQABS, SQNEG " Richard Henderson
` (34 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove disas_fp_int_conv and disas_data_proc_fp as these
were the last insns decoded by those functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 232 ++++++++++-----------------------
target/arm/tcg/a64.decode | 14 ++
2 files changed, 86 insertions(+), 160 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 90e1567ad1..e0b5dd76b0 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8738,175 +8738,87 @@ static bool trans_FJCVTZS(DisasContext *s, arg_FJCVTZS *a)
return true;
}
-static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
+static bool trans_FMOV_hx(DisasContext *s, arg_rr *a)
{
- /* FMOV: gpr to or from float, double, or top half of quad fp reg,
- * without conversion.
- */
-
- if (itof) {
- TCGv_i64 tcg_rn = cpu_reg(s, rn);
- TCGv_i64 tmp;
-
- switch (type) {
- case 0:
- /* 32 bit */
- tmp = tcg_temp_new_i64();
- tcg_gen_ext32u_i64(tmp, tcg_rn);
- write_fp_dreg(s, rd, tmp);
- break;
- case 1:
- /* 64 bit */
- write_fp_dreg(s, rd, tcg_rn);
- break;
- case 2:
- /* 64 bit to top half. */
- tcg_gen_st_i64(tcg_rn, tcg_env, fp_reg_hi_offset(s, rd));
- clear_vec_high(s, true, rd);
- break;
- case 3:
- /* 16 bit */
- tmp = tcg_temp_new_i64();
- tcg_gen_ext16u_i64(tmp, tcg_rn);
- write_fp_dreg(s, rd, tmp);
- break;
- default:
- g_assert_not_reached();
- }
- } else {
- TCGv_i64 tcg_rd = cpu_reg(s, rd);
-
- switch (type) {
- case 0:
- /* 32 bit */
- tcg_gen_ld32u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_32));
- break;
- case 1:
- /* 64 bit */
- tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_64));
- break;
- case 2:
- /* 64 bits from top half */
- tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_hi_offset(s, rn));
- break;
- case 3:
- /* 16 bit */
- tcg_gen_ld16u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_16));
- break;
- default:
- g_assert_not_reached();
- }
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ return false;
}
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
+ write_fp_dreg(s, a->rd, tmp);
+ }
+ return true;
}
-/* Floating point <-> integer conversions
- * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
- * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
- * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
- * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
- */
-static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
+static bool trans_FMOV_sw(DisasContext *s, arg_rr *a)
{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int opcode = extract32(insn, 16, 3);
- int rmode = extract32(insn, 19, 2);
- int type = extract32(insn, 22, 2);
- bool sbit = extract32(insn, 29, 1);
- bool sf = extract32(insn, 31, 1);
- bool itof = false;
-
- if (sbit) {
- goto do_unallocated;
- }
-
- switch (opcode) {
- case 2: /* SCVTF */
- case 3: /* UCVTF */
- case 4: /* FCVTAS */
- case 5: /* FCVTAU */
- case 0: /* FCVT[NPMZ]S */
- case 1: /* FCVT[NPMZ]U */
- goto do_unallocated;
-
- default:
- switch (sf << 7 | type << 5 | rmode << 3 | opcode) {
- case 0b01100110: /* FMOV half <-> 32-bit int */
- case 0b01100111:
- case 0b11100110: /* FMOV half <-> 64-bit int */
- case 0b11100111:
- if (!dc_isar_feature(aa64_fp16, s)) {
- goto do_unallocated;
- }
- /* fallthru */
- case 0b00000110: /* FMOV 32-bit */
- case 0b00000111:
- case 0b10100110: /* FMOV 64-bit */
- case 0b10100111:
- case 0b11001110: /* FMOV top half of 128-bit */
- case 0b11001111:
- if (!fp_access_check(s)) {
- return;
- }
- itof = opcode & 1;
- handle_fmov(s, rd, rn, type, itof);
- break;
-
- case 0b00111110: /* FJCVTZS */
- default:
- do_unallocated:
- unallocated_encoding(s);
- return;
- }
- break;
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ tcg_gen_ext32u_i64(tmp, tcg_rn);
+ write_fp_dreg(s, a->rd, tmp);
}
+ return true;
}
-/* FP-specific subcases of table C3-6 (SIMD and FP data processing)
- * 31 30 29 28 25 24 0
- * +---+---+---+---------+-----------------------------+
- * | | 0 | | 1 1 1 1 | |
- * +---+---+---+---------+-----------------------------+
- */
-static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
+static bool trans_FMOV_dx(DisasContext *s, arg_rr *a)
{
- if (extract32(insn, 24, 1)) {
- unallocated_encoding(s); /* in decodetree */
- } else if (extract32(insn, 21, 1) == 0) {
- /* Floating point to fixed point conversions */
- unallocated_encoding(s); /* in decodetree */
- } else {
- switch (extract32(insn, 10, 2)) {
- case 1: /* Floating point conditional compare */
- case 2: /* Floating point data-processing (2 source) */
- case 3: /* Floating point conditional select */
- unallocated_encoding(s); /* in decodetree */
- break;
- case 0:
- switch (ctz32(extract32(insn, 12, 4))) {
- case 0: /* [15:12] == xxx1 */
- /* Floating point immediate */
- unallocated_encoding(s); /* in decodetree */
- break;
- case 1: /* [15:12] == xx10 */
- /* Floating point compare */
- unallocated_encoding(s); /* in decodetree */
- break;
- case 2: /* [15:12] == x100 */
- /* Floating point data-processing (1 source) */
- unallocated_encoding(s); /* in decodetree */
- break;
- case 3: /* [15:12] == 1000 */
- unallocated_encoding(s);
- break;
- default: /* [15:12] == 0000 */
- /* Floating point <-> integer conversions */
- disas_fp_int_conv(s, insn);
- break;
- }
- break;
- }
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
+ write_fp_dreg(s, a->rd, tcg_rn);
}
+ return true;
+}
+
+static bool trans_FMOV_ux(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rn = cpu_reg(s, a->rn);
+ tcg_gen_st_i64(tcg_rn, tcg_env, fp_reg_hi_offset(s, a->rd));
+ clear_vec_high(s, true, a->rd);
+ }
+ return true;
+}
+
+static bool trans_FMOV_xh(DisasContext *s, arg_rr *a)
+{
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ return false;
+ }
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ tcg_gen_ld16u_i64(tcg_rd, tcg_env, fp_reg_offset(s, a->rn, MO_16));
+ }
+ return true;
+}
+
+static bool trans_FMOV_ws(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ tcg_gen_ld32u_i64(tcg_rd, tcg_env, fp_reg_offset(s, a->rn, MO_32));
+ }
+ return true;
+}
+
+static bool trans_FMOV_xd(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_offset(s, a->rn, MO_64));
+ }
+ return true;
+}
+
+static bool trans_FMOV_xu(DisasContext *s, arg_rr *a)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
+ tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_hi_offset(s, a->rn));
+ }
+ return true;
}
/* Common vector code for handling integer to FP conversion */
@@ -10823,7 +10735,7 @@ static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
{
if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) {
- disas_data_proc_fp(s, insn);
+ unallocated_encoding(s); /* in decodetree */
} else {
/* SIMD, including crypto */
disas_data_proc_simd(s, insn);
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 7b83d06d0d..787e673f7c 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1365,6 +1365,20 @@ FCVTAU_g . 0011110 .. 100101 000000 ..... ..... @icvt
FJCVTZS 0 0011110 01 111110 000000 ..... ..... @rr
+FMOV_ws 0 0011110 00 100110 000000 ..... ..... @rr
+FMOV_sw 0 0011110 00 100111 000000 ..... ..... @rr
+
+FMOV_xd 1 0011110 01 100110 000000 ..... ..... @rr
+FMOV_dx 1 0011110 01 100111 000000 ..... ..... @rr
+
+# Move to/from upper half of 128-bit
+FMOV_xu 1 0011110 10 101110 000000 ..... ..... @rr
+FMOV_ux 1 0011110 10 101111 000000 ..... ..... @rr
+
+# Half-precision allows both sf=0 and sf=1 with identical results
+FMOV_xh - 0011110 11 100110 000000 ..... ..... @rr
+FMOV_hx - 0011110 11 100111 000000 ..... ..... @rr
+
# Floating-point data processing (1 source)
FMOV_s 00011110 .. 1 000000 10000 ..... ..... @rr_hsd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 34/67] target/arm: Convert SQABS, SQNEG to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (32 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 33/67] target/arm: Convert handle_fmov " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 14:28 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 35/67] target/arm: Convert ABS, NEG " Richard Henderson
` (33 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 123 +++++++++++++++++++++------------
target/arm/tcg/a64.decode | 11 +++
2 files changed, 89 insertions(+), 45 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index e0b5dd76b0..6564fff6b9 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8821,6 +8821,78 @@ static bool trans_FMOV_xu(DisasContext *s, arg_rr *a)
return true;
}
+typedef struct ENVScalar1 {
+ NeonGenOneOpEnvFn *gen_bhs[3];
+ NeonGenOne64OpEnvFn *gen_d;
+} ENVScalar1;
+
+static bool do_env_scalar1(DisasContext *s, arg_rr_e *a, const ENVScalar1 *f)
+{
+ if (!fp_access_check(s)) {
+ return true;
+ }
+ if (a->esz == MO_64) {
+ TCGv_i64 t = read_fp_dreg(s, a->rn);
+ f->gen_d(t, tcg_env, t);
+ write_fp_dreg(s, a->rd, t);
+ } else {
+ TCGv_i32 t = tcg_temp_new_i32();
+
+ read_vec_element_i32(s, t, a->rn, 0, a->esz);
+ f->gen_bhs[a->esz](t, tcg_env, t);
+ write_fp_sreg(s, a->rd, t);
+ }
+ return true;
+}
+
+static bool do_env_vector1(DisasContext *s, arg_qrr_e *a, const ENVScalar1 *f)
+{
+ if (a->esz == MO_64 && !a->q) {
+ return false;
+ }
+ if (!fp_access_check(s)) {
+ return true;
+ }
+ if (a->esz == MO_64) {
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ for (int i = 0; i < 2; ++i) {
+ read_vec_element(s, t, a->rn, i, MO_64);
+ f->gen_d(t, tcg_env, t);
+ write_vec_element(s, t, a->rd, i, MO_64);
+ }
+ } else {
+ TCGv_i32 t = tcg_temp_new_i32();
+ int n = (a->q ? 16 : 8) >> a->esz;
+
+ for (int i = 0; i < n; ++i) {
+ read_vec_element_i32(s, t, a->rn, i, a->esz);
+ f->gen_bhs[a->esz](t, tcg_env, t);
+ write_vec_element_i32(s, t, a->rd, i, a->esz);
+ }
+ }
+ clear_vec_high(s, a->q, a->rd);
+ return true;
+}
+
+static const ENVScalar1 f_scalar_sqabs = {
+ { gen_helper_neon_qabs_s8,
+ gen_helper_neon_qabs_s16,
+ gen_helper_neon_qabs_s32 },
+ gen_helper_neon_qabs_s64,
+};
+TRANS(SQABS_s, do_env_scalar1, a, &f_scalar_sqabs)
+TRANS(SQABS_v, do_env_vector1, a, &f_scalar_sqabs)
+
+static const ENVScalar1 f_scalar_sqneg = {
+ { gen_helper_neon_qneg_s8,
+ gen_helper_neon_qneg_s16,
+ gen_helper_neon_qneg_s32 },
+ gen_helper_neon_qneg_s64,
+};
+TRANS(SQNEG_s, do_env_scalar1, a, &f_scalar_sqneg)
+TRANS(SQNEG_v, do_env_vector1, a, &f_scalar_sqneg)
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9133,13 +9205,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
*/
tcg_gen_not_i64(tcg_rd, tcg_rn);
break;
- case 0x7: /* SQABS, SQNEG */
- if (u) {
- gen_helper_neon_qneg_s64(tcg_rd, tcg_env, tcg_rn);
- } else {
- gen_helper_neon_qabs_s64(tcg_rd, tcg_env, tcg_rn);
- }
- break;
case 0xa: /* CMLT */
cond = TCG_COND_LT;
do_cmop:
@@ -9202,6 +9267,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus);
break;
default:
+ case 0x7: /* SQABS, SQNEG */
g_assert_not_reached();
}
}
@@ -9544,8 +9610,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
- case 0x7: /* SQABS / SQNEG */
- break;
case 0xa: /* CMLT */
if (u) {
unallocated_encoding(s);
@@ -9644,6 +9708,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
break;
default:
case 0x3: /* USQADD / SUQADD */
+ case 0x7: /* SQABS / SQNEG */
unallocated_encoding(s);
return;
}
@@ -9673,18 +9738,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
read_vec_element_i32(s, tcg_rn, rn, 0, size);
switch (opcode) {
- case 0x7: /* SQABS, SQNEG */
- {
- NeonGenOneOpEnvFn *genfn;
- static NeonGenOneOpEnvFn * const fns[3][2] = {
- { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
- { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
- { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 },
- };
- genfn = fns[size][u];
- genfn(tcg_rd, tcg_env, tcg_rn);
- break;
- }
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
@@ -9702,6 +9755,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
tcg_fpstatus);
break;
default:
+ case 0x7: /* SQABS, SQNEG */
g_assert_not_reached();
}
@@ -10059,12 +10113,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
return;
}
break;
- case 0x7: /* SQABS, SQNEG */
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- break;
case 0xc ... 0xf:
case 0x16 ... 0x1f:
{
@@ -10235,6 +10283,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
default:
case 0x3: /* SUQADD, USQADD */
+ case 0x7: /* SQABS, SQNEG */
unallocated_encoding(s);
return;
}
@@ -10325,13 +10374,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
tcg_gen_clrsb_i32(tcg_res, tcg_op);
}
break;
- case 0x7: /* SQABS, SQNEG */
- if (u) {
- gen_helper_neon_qneg_s32(tcg_res, tcg_env, tcg_op);
- } else {
- gen_helper_neon_qabs_s32(tcg_res, tcg_env, tcg_op);
- }
- break;
case 0x2f: /* FABS */
gen_vfp_abss(tcg_res, tcg_op);
break;
@@ -10380,6 +10422,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus);
break;
default:
+ case 0x7: /* SQABS, SQNEG */
g_assert_not_reached();
}
} else {
@@ -10395,17 +10438,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
gen_helper_neon_cnt_u8(tcg_res, tcg_op);
}
break;
- case 0x7: /* SQABS, SQNEG */
- {
- NeonGenOneOpEnvFn *genfn;
- static NeonGenOneOpEnvFn * const fns[2][2] = {
- { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
- { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
- };
- genfn = fns[size][u];
- genfn(tcg_res, tcg_env, tcg_op);
- break;
- }
case 0x4: /* CLS, CLZ */
if (u) {
if (size == 0) {
@@ -10422,6 +10454,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
break;
default:
+ case 0x7: /* SQABS, SQNEG */
g_assert_not_reached();
}
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 787e673f7c..d26ee07597 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -47,6 +47,7 @@
@rr_h ........ ... ..... ...... rn:5 rd:5 &rr_e esz=1
@rr_s ........ ... ..... ...... rn:5 rd:5 &rr_e esz=2
@rr_d ........ ... ..... ...... rn:5 rd:5 &rr_e esz=3
+@rr_e ........ esz:2 . ..... ...... rn:5 rd:5 &rr_e
@rr_sd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_sd
@rr_hsd ........ ... ..... ...... rn:5 rd:5 &rr_e esz=%esz_hsd
@@ -1626,3 +1627,13 @@ UQRSHRN_si 0111 11110 .... ... 10011 1 ..... ..... @shri_s
SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..... @shri_b
SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..... @shri_h
SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..... @shri_s
+
+# Advanced SIMD scalar two-register miscellaneous
+
+SQABS_s 0101 1110 ..1 00000 01111 0 ..... ..... @rr_e
+SQNEG_s 0111 1110 ..1 00000 01111 0 ..... ..... @rr_e
+
+# Advanced SIMD two-register miscellaneous
+
+SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
+SQNEG_v 0.10 1110 ..1 00000 01111 0 ..... ..... @qrr_e
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 35/67] target/arm: Convert ABS, NEG to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (33 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 34/67] target/arm: Convert SQABS, SQNEG " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 14:30 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 36/67] target/arm: Introduce gen_gvec_cls, gen_gvec_clz Richard Henderson
` (32 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 46 +++++++++++++++++++++++-----------
target/arm/tcg/a64.decode | 4 +++
2 files changed, 35 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 6564fff6b9..c519f82452 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8893,6 +8893,33 @@ static const ENVScalar1 f_scalar_sqneg = {
TRANS(SQNEG_s, do_env_scalar1, a, &f_scalar_sqneg)
TRANS(SQNEG_v, do_env_vector1, a, &f_scalar_sqneg)
+static bool do_scalar1_d(DisasContext *s, arg_rr *a, ArithOneOp *f)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 t = read_fp_dreg(s, a->rn);
+ f(t, t);
+ write_fp_dreg(s, a->rd, t);
+ }
+ return true;
+}
+
+TRANS(ABS_s, do_scalar1_d, a, tcg_gen_abs_i64)
+TRANS(NEG_s, do_scalar1_d, a, tcg_gen_neg_i64)
+
+static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
+{
+ if (!a->q && a->esz == MO_64) {
+ return false;
+ }
+ if (fp_access_check(s)) {
+ gen_gvec_fn2(s, a->q, a->rd, a->rn, fn, a->esz);
+ }
+ return true;
+}
+
+TRANS(ABS_v, do_gvec_fn2, a, tcg_gen_gvec_abs)
+TRANS(NEG_v, do_gvec_fn2, a, tcg_gen_gvec_neg)
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9217,13 +9244,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
case 0x9: /* CMEQ, CMLE */
cond = u ? TCG_COND_LE : TCG_COND_EQ;
goto do_cmop;
- case 0xb: /* ABS, NEG */
- if (u) {
- tcg_gen_neg_i64(tcg_rd, tcg_rn);
- } else {
- tcg_gen_abs_i64(tcg_rd, tcg_rn);
- }
- break;
case 0x2f: /* FABS */
gen_vfp_absd(tcg_rd, tcg_rn);
break;
@@ -9268,6 +9288,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
break;
default:
case 0x7: /* SQABS, SQNEG */
+ case 0xb: /* ABS, NEG */
g_assert_not_reached();
}
}
@@ -9618,7 +9639,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
/* fall through */
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
- case 0xb: /* ABS, NEG */
if (size != 3) {
unallocated_encoding(s);
return;
@@ -9709,6 +9729,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
default:
case 0x3: /* USQADD / SUQADD */
case 0x7: /* SQABS / SQNEG */
+ case 0xb: /* ABS, NEG */
unallocated_encoding(s);
return;
}
@@ -10107,7 +10128,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
/* fall through */
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
- case 0xb: /* ABS, NEG */
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
@@ -10284,6 +10304,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
default:
case 0x3: /* SUQADD, USQADD */
case 0x7: /* SQABS, SQNEG */
+ case 0xb: /* ABS, NEG */
unallocated_encoding(s);
return;
}
@@ -10328,12 +10349,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
return;
case 0xb:
- if (u) { /* ABS, NEG */
- gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
- } else {
- gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_abs, size);
- }
- return;
+ g_assert_not_reached();
}
if (size == 3) {
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index d26ee07597..30cd05030a 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1632,8 +1632,12 @@ SQRSHRUN_si 0111 11110 .... ... 10001 1 ..... ..... @shri_s
SQABS_s 0101 1110 ..1 00000 01111 0 ..... ..... @rr_e
SQNEG_s 0111 1110 ..1 00000 01111 0 ..... ..... @rr_e
+ABS_s 0101 1110 111 00000 10111 0 ..... ..... @rr
+NEG_s 0111 1110 111 00000 10111 0 ..... ..... @rr
# Advanced SIMD two-register miscellaneous
SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
SQNEG_v 0.10 1110 ..1 00000 01111 0 ..... ..... @qrr_e
+ABS_v 0.00 1110 ..1 00000 10111 0 ..... ..... @qrr_e
+NEG_v 0.10 1110 ..1 00000 10111 0 ..... ..... @qrr_e
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 36/67] target/arm: Introduce gen_gvec_cls, gen_gvec_clz
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (34 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 35/67] target/arm: Convert ABS, NEG " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 16:29 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 37/67] target/arm: Convert CLS, CLZ (vector) to decodetree Richard Henderson
` (31 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Add gvec interfaces for CLS and CLZ operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate.h | 5 +++++
target/arm/tcg/gengvec.c | 35 +++++++++++++++++++++++++++++++++
target/arm/tcg/translate-a64.c | 29 +++++++--------------------
target/arm/tcg/translate-neon.c | 29 ++-------------------------
4 files changed, 49 insertions(+), 49 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 20cd0e851c..5c6c24f057 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -578,6 +578,11 @@ void gen_gvec_umaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
void gen_gvec_uminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_cls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_clz(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+
/*
* Forward to the isar_feature_* tests given a DisasContext pointer.
*/
diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c
index f652520b65..834b2961c0 100644
--- a/target/arm/tcg/gengvec.c
+++ b/target/arm/tcg/gengvec.c
@@ -2358,3 +2358,38 @@ void gen_gvec_urhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
assert(vece <= MO_32);
tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &g[vece]);
}
+
+void gen_gvec_cls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ static const GVecGen2 g[] = {
+ { .fni4 = gen_helper_neon_cls_s8,
+ .vece = MO_8 },
+ { .fni4 = gen_helper_neon_cls_s16,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_clrsb_i32,
+ .vece = MO_32 },
+ };
+ assert(vece <= MO_32);
+ tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
+}
+
+static void gen_clz32_i32(TCGv_i32 d, TCGv_i32 n)
+{
+ tcg_gen_clzi_i32(d, n, 32);
+}
+
+void gen_gvec_clz(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ static const GVecGen2 g[] = {
+ { .fni4 = gen_helper_neon_clz_u8,
+ .vece = MO_8 },
+ { .fni4 = gen_helper_neon_clz_u16,
+ .vece = MO_16 },
+ { .fni4 = gen_clz32_i32,
+ .vece = MO_32 },
+ };
+ assert(vece <= MO_32);
+ tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
+}
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index c519f82452..4abc786cf6 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -10325,6 +10325,13 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
switch (opcode) {
+ case 0x4: /* CLZ, CLS */
+ if (u) {
+ gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clz, size);
+ } else {
+ gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cls, size);
+ }
+ return;
case 0x5:
if (u && size == 0) { /* NOT */
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0);
@@ -10383,13 +10390,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
if (size == 2) {
/* Special cases for 32 bit elements */
switch (opcode) {
- case 0x4: /* CLS */
- if (u) {
- tcg_gen_clzi_i32(tcg_res, tcg_op, 32);
- } else {
- tcg_gen_clrsb_i32(tcg_res, tcg_op);
- }
- break;
case 0x2f: /* FABS */
gen_vfp_abss(tcg_res, tcg_op);
break;
@@ -10454,21 +10454,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
gen_helper_neon_cnt_u8(tcg_res, tcg_op);
}
break;
- case 0x4: /* CLS, CLZ */
- if (u) {
- if (size == 0) {
- gen_helper_neon_clz_u8(tcg_res, tcg_op);
- } else {
- gen_helper_neon_clz_u16(tcg_res, tcg_op);
- }
- } else {
- if (size == 0) {
- gen_helper_neon_cls_s8(tcg_res, tcg_op);
- } else {
- gen_helper_neon_cls_s16(tcg_res, tcg_op);
- }
- }
- break;
default:
case 0x7: /* SQABS, SQNEG */
g_assert_not_reached();
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index 9c8829ad7d..1c89a53272 100644
--- a/target/arm/tcg/translate-neon.c
+++ b/target/arm/tcg/translate-neon.c
@@ -3120,6 +3120,8 @@ DO_2MISC_VEC(VCGT0, gen_gvec_cgt0)
DO_2MISC_VEC(VCLE0, gen_gvec_cle0)
DO_2MISC_VEC(VCGE0, gen_gvec_cge0)
DO_2MISC_VEC(VCLT0, gen_gvec_clt0)
+DO_2MISC_VEC(VCLS, gen_gvec_cls)
+DO_2MISC_VEC(VCLZ, gen_gvec_clz)
static bool trans_VMVN(DisasContext *s, arg_2misc *a)
{
@@ -3227,33 +3229,6 @@ static bool trans_VREV16(DisasContext *s, arg_2misc *a)
return do_2misc(s, a, gen_rev16);
}
-static bool trans_VCLS(DisasContext *s, arg_2misc *a)
-{
- static NeonGenOneOpFn * const fn[] = {
- gen_helper_neon_cls_s8,
- gen_helper_neon_cls_s16,
- gen_helper_neon_cls_s32,
- NULL,
- };
- return do_2misc(s, a, fn[a->size]);
-}
-
-static void do_VCLZ_32(TCGv_i32 rd, TCGv_i32 rm)
-{
- tcg_gen_clzi_i32(rd, rm, 32);
-}
-
-static bool trans_VCLZ(DisasContext *s, arg_2misc *a)
-{
- static NeonGenOneOpFn * const fn[] = {
- gen_helper_neon_clz_u8,
- gen_helper_neon_clz_u16,
- do_VCLZ_32,
- NULL,
- };
- return do_2misc(s, a, fn[a->size]);
-}
-
static bool trans_VCNT(DisasContext *s, arg_2misc *a)
{
if (a->size != 0) {
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 36/67] target/arm: Introduce gen_gvec_cls, gen_gvec_clz
2024-12-01 15:05 ` [PATCH 36/67] target/arm: Introduce gen_gvec_cls, gen_gvec_clz Richard Henderson
@ 2024-12-02 16:29 ` Philippe Mathieu-Daudé
2024-12-02 17:56 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-12-02 16:29 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 1/12/24 16:05, Richard Henderson wrote:
> Add gvec interfaces for CLS and CLZ operations.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate.h | 5 +++++
> target/arm/tcg/gengvec.c | 35 +++++++++++++++++++++++++++++++++
> target/arm/tcg/translate-a64.c | 29 +++++++--------------------
> target/arm/tcg/translate-neon.c | 29 ++-------------------------
> 4 files changed, 49 insertions(+), 49 deletions(-)
> +void gen_gvec_cls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
> + uint32_t opr_sz, uint32_t max_sz)
> +{
> + static const GVecGen2 g[] = {
> + { .fni4 = gen_helper_neon_cls_s8,
> + .vece = MO_8 },
> + { .fni4 = gen_helper_neon_cls_s16,
> + .vece = MO_16 },
> + { .fni4 = tcg_gen_clrsb_i32,
Why do we have tcg_gen_clrsb_i32(), ...
> + .vece = MO_32 },
> + };
> + assert(vece <= MO_32);
> + tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
> +}
> +
> +static void gen_clz32_i32(TCGv_i32 d, TCGv_i32 n)
... but not tcg_gen_clz32_i32()?
> +{
> + tcg_gen_clzi_i32(d, n, 32);
> +}
Anyhow,
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 36/67] target/arm: Introduce gen_gvec_cls, gen_gvec_clz
2024-12-02 16:29 ` Philippe Mathieu-Daudé
@ 2024-12-02 17:56 ` Richard Henderson
0 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-02 17:56 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: qemu-arm
On 12/2/24 10:29, Philippe Mathieu-Daudé wrote:
> On 1/12/24 16:05, Richard Henderson wrote:
>> Add gvec interfaces for CLS and CLZ operations.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/tcg/translate.h | 5 +++++
>> target/arm/tcg/gengvec.c | 35 +++++++++++++++++++++++++++++++++
>> target/arm/tcg/translate-a64.c | 29 +++++++--------------------
>> target/arm/tcg/translate-neon.c | 29 ++-------------------------
>> 4 files changed, 49 insertions(+), 49 deletions(-)
>
>
>> +void gen_gvec_cls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
>> + uint32_t opr_sz, uint32_t max_sz)
>> +{
>> + static const GVecGen2 g[] = {
>> + { .fni4 = gen_helper_neon_cls_s8,
>> + .vece = MO_8 },
>> + { .fni4 = gen_helper_neon_cls_s16,
>> + .vece = MO_16 },
>> + { .fni4 = tcg_gen_clrsb_i32,
>
> Why do we have tcg_gen_clrsb_i32(), ...
>
>> + .vece = MO_32 },
>> + };
>> + assert(vece <= MO_32);
>> + tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
>> +}
>> +
>> +static void gen_clz32_i32(TCGv_i32 d, TCGv_i32 n)
>
> ... but not tcg_gen_clz32_i32()?
The tcg_gen_clz_i32 primitive has a third argument to specify the result for n == 0.
Passing that third argument is exactly what gen_clz32_i32 is doing.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 37/67] target/arm: Convert CLS, CLZ (vector) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (35 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 36/67] target/arm: Introduce gen_gvec_cls, gen_gvec_clz Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 14:40 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 38/67] target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit Richard Henderson
` (30 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 37 ++++++++++++++++------------------
target/arm/tcg/a64.decode | 2 ++
2 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 4abc786cf6..312bf48020 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8920,6 +8920,20 @@ static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
TRANS(ABS_v, do_gvec_fn2, a, tcg_gen_gvec_abs)
TRANS(NEG_v, do_gvec_fn2, a, tcg_gen_gvec_neg)
+static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
+{
+ if (a->esz == MO_64) {
+ return false;
+ }
+ if (fp_access_check(s)) {
+ gen_gvec_fn2(s, a->q, a->rd, a->rn, fn, a->esz);
+ }
+ return true;
+}
+
+TRANS(CLS_v, do_gvec_fn2_bhs, a, gen_gvec_cls)
+TRANS(CLZ_v, do_gvec_fn2_bhs, a, gen_gvec_clz)
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9219,13 +9233,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
TCGCond cond;
switch (opcode) {
- case 0x4: /* CLS, CLZ */
- if (u) {
- tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64);
- } else {
- tcg_gen_clrsb_i64(tcg_rd, tcg_rn);
- }
- break;
case 0x5: /* NOT */
/* This opcode is shared with CNT and RBIT but we have earlier
* enforced that size == 3 if and only if this is the NOT insn.
@@ -9287,6 +9294,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus);
break;
default:
+ case 0x4: /* CLS, CLZ */
case 0x7: /* SQABS, SQNEG */
case 0xb: /* ABS, NEG */
g_assert_not_reached();
@@ -10093,12 +10101,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
return;
- case 0x4: /* CLS, CLZ */
- if (size == 3) {
- unallocated_encoding(s);
- return;
- }
- break;
case 0x2: /* SADDLP, UADDLP */
case 0x6: /* SADALP, UADALP */
if (size == 3) {
@@ -10303,6 +10305,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
default:
case 0x3: /* SUQADD, USQADD */
+ case 0x4: /* CLS, CLZ */
case 0x7: /* SQABS, SQNEG */
case 0xb: /* ABS, NEG */
unallocated_encoding(s);
@@ -10325,13 +10328,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
switch (opcode) {
- case 0x4: /* CLZ, CLS */
- if (u) {
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clz, size);
- } else {
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cls, size);
- }
- return;
case 0x5:
if (u && size == 0) { /* NOT */
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0);
@@ -10355,6 +10351,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0xa: /* CMLT */
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
return;
+ case 0x4: /* CLZ, CLS */
case 0xb:
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 30cd05030a..c3acb5dc37 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1641,3 +1641,5 @@ SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
SQNEG_v 0.10 1110 ..1 00000 01111 0 ..... ..... @qrr_e
ABS_v 0.00 1110 ..1 00000 10111 0 ..... ..... @qrr_e
NEG_v 0.10 1110 ..1 00000 10111 0 ..... ..... @qrr_e
+CLS_v 0.00 1110 ..1 00000 01001 0 ..... ..... @qrr_e
+CLZ_v 0.10 1110 ..1 00000 01001 0 ..... ..... @qrr_e
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 37/67] target/arm: Convert CLS, CLZ (vector) to decodetree
2024-12-01 15:05 ` [PATCH 37/67] target/arm: Convert CLS, CLZ (vector) to decodetree Richard Henderson
@ 2024-12-06 14:40 ` Peter Maydell
2024-12-06 15:52 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 14:40 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:10, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 37 ++++++++++++++++------------------
> target/arm/tcg/a64.decode | 2 ++
> 2 files changed, 19 insertions(+), 20 deletions(-)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 4abc786cf6..312bf48020 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -8920,6 +8920,20 @@ static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
> TRANS(ABS_v, do_gvec_fn2, a, tcg_gen_gvec_abs)
> TRANS(NEG_v, do_gvec_fn2, a, tcg_gen_gvec_neg)
>
> +static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
> +{
> + if (a->esz == MO_64) {
> + return false;
> + }
> + if (fp_access_check(s)) {
> + gen_gvec_fn2(s, a->q, a->rd, a->rn, fn, a->esz);
> + }
> + return true;
> +}
> +
> +TRANS(CLS_v, do_gvec_fn2_bhs, a, gen_gvec_cls)
> +TRANS(CLZ_v, do_gvec_fn2_bhs, a, gen_gvec_clz)
> +
> /* Common vector code for handling integer to FP conversion */
> static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
> int elements, int is_signed,
> @@ -9219,13 +9233,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
> TCGCond cond;
>
> switch (opcode) {
> - case 0x4: /* CLS, CLZ */
> - if (u) {
> - tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64);
> - } else {
> - tcg_gen_clrsb_i64(tcg_rd, tcg_rn);
> - }
> - break;
> case 0x5: /* NOT */
This was dead code, right? We only call handle_2misc_64()
for size == 3, but size == 3 is an unallocated encoding for
"CLS/CLZ (vector)", which only deals with elements sizes up
to 32 bits. Worth mentioning in the commit message, I think.
(I was wondering why the new code doesn't have any cases for
operating on 64-bit elements whereas this old code did seem
to handle it.)
> /* This opcode is shared with CNT and RBIT but we have earlier
> * enforced that size == 3 if and only if this is the NOT insn.
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 37/67] target/arm: Convert CLS, CLZ (vector) to decodetree
2024-12-06 14:40 ` Peter Maydell
@ 2024-12-06 15:52 ` Richard Henderson
0 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-06 15:52 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 12/6/24 08:40, Peter Maydell wrote:
>> @@ -9219,13 +9233,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
>> TCGCond cond;
>>
>> switch (opcode) {
>> - case 0x4: /* CLS, CLZ */
>> - if (u) {
>> - tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64);
>> - } else {
>> - tcg_gen_clrsb_i64(tcg_rd, tcg_rn);
>> - }
>> - break;
>> case 0x5: /* NOT */
>
> This was dead code, right? We only call handle_2misc_64()
> for size == 3, but size == 3 is an unallocated encoding for
> "CLS/CLZ (vector)", which only deals with elements sizes up
> to 32 bits. Worth mentioning in the commit message, I think.
>
> (I was wondering why the new code doesn't have any cases for
> operating on 64-bit elements whereas this old code did seem
> to handle it.)
I had been wondering if I had failed to remove it earlier, but this has been dead code
since the day it was added: b05c3068577.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 38/67] target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (36 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 37/67] target/arm: Convert CLS, CLZ (vector) to decodetree Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:02 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 39/67] target/arm: Convert CNT, NOT, RBIT (vector) to decodetree Richard Henderson
` (29 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Add gvec interfaces for CNT and RBIT operations.
Use ctpop8 for CNT and revbit+bswap for RBIT.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 4 ++--
target/arm/tcg/translate.h | 4 ++++
target/arm/tcg/gengvec.c | 16 ++++++++++++++++
target/arm/tcg/neon_helper.c | 21 ---------------------
target/arm/tcg/translate-a64.c | 32 +++++++++-----------------------
target/arm/tcg/translate-neon.c | 16 ++++++++--------
target/arm/tcg/vec_helper.c | 24 ++++++++++++++++++++++++
7 files changed, 63 insertions(+), 54 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 0a697e752b..167e331a83 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -363,8 +363,8 @@ DEF_HELPER_1(neon_clz_u16, i32, i32)
DEF_HELPER_1(neon_cls_s8, i32, i32)
DEF_HELPER_1(neon_cls_s16, i32, i32)
DEF_HELPER_1(neon_cls_s32, i32, i32)
-DEF_HELPER_1(neon_cnt_u8, i32, i32)
-DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32)
+DEF_HELPER_FLAGS_3(gvec_cnt_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32)
DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 5c6c24f057..cb8e1b2586 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -582,6 +582,10 @@ void gen_gvec_cls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_clz(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_cnt(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_rbit(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
/*
* Forward to the isar_feature_* tests given a DisasContext pointer.
diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c
index 834b2961c0..85a0b50496 100644
--- a/target/arm/tcg/gengvec.c
+++ b/target/arm/tcg/gengvec.c
@@ -2393,3 +2393,19 @@ void gen_gvec_clz(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
assert(vece <= MO_32);
tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
}
+
+void gen_gvec_cnt(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ assert(vece == MO_8);
+ tcg_gen_gvec_2_ool(rd_ofs, rn_ofs, opr_sz, max_sz, 0,
+ gen_helper_gvec_cnt_b);
+}
+
+void gen_gvec_rbit(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ assert(vece == MO_8);
+ tcg_gen_gvec_2_ool(rd_ofs, rn_ofs, opr_sz, max_sz, 0,
+ gen_helper_gvec_rbit_b);
+}
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
index 93b2076c64..4e501925de 100644
--- a/target/arm/tcg/neon_helper.c
+++ b/target/arm/tcg/neon_helper.c
@@ -525,27 +525,6 @@ uint32_t HELPER(neon_cls_s32)(uint32_t x)
return count - 1;
}
-/* Bit count. */
-uint32_t HELPER(neon_cnt_u8)(uint32_t x)
-{
- x = (x & 0x55555555) + ((x >> 1) & 0x55555555);
- x = (x & 0x33333333) + ((x >> 2) & 0x33333333);
- x = (x & 0x0f0f0f0f) + ((x >> 4) & 0x0f0f0f0f);
- return x;
-}
-
-/* Reverse bits in each 8 bit word */
-uint32_t HELPER(neon_rbit_u8)(uint32_t x)
-{
- x = ((x & 0xf0f0f0f0) >> 4)
- | ((x & 0x0f0f0f0f) << 4);
- x = ((x & 0x88888888) >> 3)
- | ((x & 0x44444444) >> 1)
- | ((x & 0x22222222) << 1)
- | ((x & 0x11111111) << 3);
- return x;
-}
-
#define NEON_QDMULH16(dest, src1, src2, round) do { \
uint32_t tmp = (int32_t)(int16_t) src1 * (int16_t) src2; \
if ((tmp ^ (tmp << 1)) & SIGNBIT) { \
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 312bf48020..f96b29e5a9 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -10328,12 +10328,15 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
switch (opcode) {
- case 0x5:
- if (u && size == 0) { /* NOT */
+ case 0x5: /* CNT, NOT, RBIT */
+ if (!u) {
+ gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cnt, 0);
+ } else if (size) {
+ gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_rbit, 0);
+ } else {
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0);
- return;
}
- break;
+ return;
case 0x8: /* CMGT, CMGE */
if (u) {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size);
@@ -10378,13 +10381,14 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
} else {
int pass;
+ assert(size == 2);
for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
TCGv_i32 tcg_op = tcg_temp_new_i32();
TCGv_i32 tcg_res = tcg_temp_new_i32();
read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
- if (size == 2) {
+ {
/* Special cases for 32 bit elements */
switch (opcode) {
case 0x2f: /* FABS */
@@ -10438,25 +10442,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x7: /* SQABS, SQNEG */
g_assert_not_reached();
}
- } else {
- /* Use helpers for 8 and 16 bit elements */
- switch (opcode) {
- case 0x5: /* CNT, RBIT */
- /* For these two insns size is part of the opcode specifier
- * (handled earlier); they always operate on byte elements.
- */
- if (u) {
- gen_helper_neon_rbit_u8(tcg_res, tcg_op);
- } else {
- gen_helper_neon_cnt_u8(tcg_res, tcg_op);
- }
- break;
- default:
- case 0x7: /* SQABS, SQNEG */
- g_assert_not_reached();
- }
}
-
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
}
}
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index 1c89a53272..50d0bf7753 100644
--- a/target/arm/tcg/translate-neon.c
+++ b/target/arm/tcg/translate-neon.c
@@ -3131,6 +3131,14 @@ static bool trans_VMVN(DisasContext *s, arg_2misc *a)
return do_2misc_vec(s, a, tcg_gen_gvec_not);
}
+static bool trans_VCNT(DisasContext *s, arg_2misc *a)
+{
+ if (a->size != 0) {
+ return false;
+ }
+ return do_2misc_vec(s, a, gen_gvec_cnt);
+}
+
#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \
static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \
uint32_t rm_ofs, uint32_t oprsz, \
@@ -3229,14 +3237,6 @@ static bool trans_VREV16(DisasContext *s, arg_2misc *a)
return do_2misc(s, a, gen_rev16);
}
-static bool trans_VCNT(DisasContext *s, arg_2misc *a)
-{
- if (a->size != 0) {
- return false;
- }
- return do_2misc(s, a, gen_helper_neon_cnt_u8);
-}
-
static void gen_VABS_F(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
uint32_t oprsz, uint32_t maxsz)
{
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index e825d501a2..60381258cf 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -3072,3 +3072,27 @@ DO_CLAMP(gvec_uclamp_b, uint8_t)
DO_CLAMP(gvec_uclamp_h, uint16_t)
DO_CLAMP(gvec_uclamp_s, uint32_t)
DO_CLAMP(gvec_uclamp_d, uint64_t)
+
+/* Bit count in each 8-bit word. */
+void HELPER(gvec_cnt_b)(void *vd, void *vn, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ uint8_t *d = vd, *n = vn;
+
+ for (i = 0; i < opr_sz; ++i) {
+ d[i] = ctpop8(n[i]);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
+/* Reverse bits in each 8 bit word */
+void HELPER(gvec_rbit_b)(void *vd, void *vn, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ uint64_t *d = vd, *n = vn;
+
+ for (i = 0; i < opr_sz / 8; ++i) {
+ d[i] = revbit64(bswap64(n[i]));
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 38/67] target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit
2024-12-01 15:05 ` [PATCH 38/67] target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit Richard Henderson
@ 2024-12-06 15:02 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 15:02 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:08, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Add gvec interfaces for CNT and RBIT operations.
> Use ctpop8 for CNT and revbit+bswap for RBIT.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.h | 4 ++--
> target/arm/tcg/translate.h | 4 ++++
> target/arm/tcg/gengvec.c | 16 ++++++++++++++++
> target/arm/tcg/neon_helper.c | 21 ---------------------
> target/arm/tcg/translate-a64.c | 32 +++++++++-----------------------
> target/arm/tcg/translate-neon.c | 16 ++++++++--------
> target/arm/tcg/vec_helper.c | 24 ++++++++++++++++++++++++
> 7 files changed, 63 insertions(+), 54 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 39/67] target/arm: Convert CNT, NOT, RBIT (vector) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (37 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 38/67] target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:03 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 40/67] target/arm: Convert CMGT, CMGE, GMLT, GMLE, CMEQ (zero) " Richard Henderson
` (28 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 34 ++++++----------------------------
target/arm/tcg/a64.decode | 4 ++++
2 files changed, 10 insertions(+), 28 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index f96b29e5a9..3d08c6e09b 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8919,6 +8919,9 @@ static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
TRANS(ABS_v, do_gvec_fn2, a, tcg_gen_gvec_abs)
TRANS(NEG_v, do_gvec_fn2, a, tcg_gen_gvec_neg)
+TRANS(NOT_v, do_gvec_fn2, a, tcg_gen_gvec_not)
+TRANS(CNT_v, do_gvec_fn2, a, gen_gvec_cnt)
+TRANS(RBIT_v, do_gvec_fn2, a, gen_gvec_rbit)
static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
@@ -9233,12 +9236,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
TCGCond cond;
switch (opcode) {
- case 0x5: /* NOT */
- /* This opcode is shared with CNT and RBIT but we have earlier
- * enforced that size == 3 if and only if this is the NOT insn.
- */
- tcg_gen_not_i64(tcg_rd, tcg_rn);
- break;
case 0xa: /* CMLT */
cond = TCG_COND_LT;
do_cmop:
@@ -9295,6 +9292,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
break;
default:
case 0x4: /* CLS, CLZ */
+ case 0x5: /* NOT */
case 0x7: /* SQABS, SQNEG */
case 0xb: /* ABS, NEG */
g_assert_not_reached();
@@ -10076,19 +10074,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x1: /* REV16 */
handle_rev(s, opcode, u, is_q, size, rn, rd);
return;
- case 0x5: /* CNT, NOT, RBIT */
- if (u && size == 0) {
- /* NOT */
- break;
- } else if (u && size == 1) {
- /* RBIT */
- break;
- } else if (!u && size == 0) {
- /* CNT */
- break;
- }
- unallocated_encoding(s);
- return;
case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
if (size == 3) {
@@ -10306,6 +10291,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
default:
case 0x3: /* SUQADD, USQADD */
case 0x4: /* CLS, CLZ */
+ case 0x5: /* CNT, NOT, RBIT */
case 0x7: /* SQABS, SQNEG */
case 0xb: /* ABS, NEG */
unallocated_encoding(s);
@@ -10328,15 +10314,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
switch (opcode) {
- case 0x5: /* CNT, NOT, RBIT */
- if (!u) {
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cnt, 0);
- } else if (size) {
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_rbit, 0);
- } else {
- gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0);
- }
- return;
case 0x8: /* CMGT, CMGE */
if (u) {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size);
@@ -10355,6 +10332,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
return;
case 0x4: /* CLZ, CLS */
+ case 0x5: /* CNT, NOT, RBIT */
case 0xb:
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index c3acb5dc37..29f7741bfb 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -71,6 +71,7 @@
@rrr_q1e3 ........ ... rm:5 ...... rn:5 rd:5 &qrrr_e q=1 esz=3
@rrrr_q1e3 ........ ... rm:5 . ra:5 rn:5 rd:5 &qrrrr_e q=1 esz=3
+@qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0
@qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1
@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
@@ -1643,3 +1644,6 @@ ABS_v 0.00 1110 ..1 00000 10111 0 ..... ..... @qrr_e
NEG_v 0.10 1110 ..1 00000 10111 0 ..... ..... @qrr_e
CLS_v 0.00 1110 ..1 00000 01001 0 ..... ..... @qrr_e
CLZ_v 0.10 1110 ..1 00000 01001 0 ..... ..... @qrr_e
+CNT_v 0.00 1110 001 00000 01011 0 ..... ..... @qrr_b
+NOT_v 0.10 1110 001 00000 01011 0 ..... ..... @qrr_b
+RBIT_v 0.10 1110 011 00000 01011 0 ..... ..... @qrr_b
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 39/67] target/arm: Convert CNT, NOT, RBIT (vector) to decodetree
2024-12-01 15:05 ` [PATCH 39/67] target/arm: Convert CNT, NOT, RBIT (vector) to decodetree Richard Henderson
@ 2024-12-06 15:03 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 15:03 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 34 ++++++----------------------------
> target/arm/tcg/a64.decode | 4 ++++
> 2 files changed, 10 insertions(+), 28 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 40/67] target/arm: Convert CMGT, CMGE, GMLT, GMLE, CMEQ (zero) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (38 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 39/67] target/arm: Convert CNT, NOT, RBIT (vector) to decodetree Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:06 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 41/67] target/arm: Introduce gen_gvec_rev{16,32,64} Richard Henderson
` (27 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 94 +++++++++++-----------------------
target/arm/tcg/a64.decode | 10 ++++
2 files changed, 40 insertions(+), 64 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 3d08c6e09b..bc1d0e18eb 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8906,6 +8906,22 @@ static bool do_scalar1_d(DisasContext *s, arg_rr *a, ArithOneOp *f)
TRANS(ABS_s, do_scalar1_d, a, tcg_gen_abs_i64)
TRANS(NEG_s, do_scalar1_d, a, tcg_gen_neg_i64)
+static bool do_cmop0_d(DisasContext *s, arg_rr *a, TCGCond cond)
+{
+ if (fp_access_check(s)) {
+ TCGv_i64 t = read_fp_dreg(s, a->rn);
+ tcg_gen_negsetcond_i64(cond, t, t, tcg_constant_i64(0));
+ write_fp_dreg(s, a->rd, t);
+ }
+ return true;
+}
+
+TRANS(CMGT0_s, do_cmop0_d, a, TCG_COND_GT)
+TRANS(CMGE0_s, do_cmop0_d, a, TCG_COND_GE)
+TRANS(CMLE0_s, do_cmop0_d, a, TCG_COND_LE)
+TRANS(CMLT0_s, do_cmop0_d, a, TCG_COND_LT)
+TRANS(CMEQ0_s, do_cmop0_d, a, TCG_COND_EQ)
+
static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
if (!a->q && a->esz == MO_64) {
@@ -8922,6 +8938,11 @@ TRANS(NEG_v, do_gvec_fn2, a, tcg_gen_gvec_neg)
TRANS(NOT_v, do_gvec_fn2, a, tcg_gen_gvec_not)
TRANS(CNT_v, do_gvec_fn2, a, gen_gvec_cnt)
TRANS(RBIT_v, do_gvec_fn2, a, gen_gvec_rbit)
+TRANS(CMGT0_v, do_gvec_fn2, a, gen_gvec_cgt0)
+TRANS(CMGE0_v, do_gvec_fn2, a, gen_gvec_cge0)
+TRANS(CMLT0_v, do_gvec_fn2, a, gen_gvec_clt0)
+TRANS(CMLE0_v, do_gvec_fn2, a, gen_gvec_cle0)
+TRANS(CMEQ0_v, do_gvec_fn2, a, gen_gvec_ceq0)
static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
@@ -9233,21 +9254,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
* The caller only need provide tcg_rmode and tcg_fpstatus if the op
* requires them.
*/
- TCGCond cond;
-
switch (opcode) {
- case 0xa: /* CMLT */
- cond = TCG_COND_LT;
- do_cmop:
- /* 64 bit integer comparison against zero, result is test ? -1 : 0. */
- tcg_gen_negsetcond_i64(cond, tcg_rd, tcg_rn, tcg_constant_i64(0));
- break;
- case 0x8: /* CMGT, CMGE */
- cond = u ? TCG_COND_GE : TCG_COND_GT;
- goto do_cmop;
- case 0x9: /* CMEQ, CMLE */
- cond = u ? TCG_COND_LE : TCG_COND_EQ;
- goto do_cmop;
case 0x2f: /* FABS */
gen_vfp_absd(tcg_rd, tcg_rn);
break;
@@ -9294,6 +9301,9 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
case 0x4: /* CLS, CLZ */
case 0x5: /* NOT */
case 0x7: /* SQABS, SQNEG */
+ case 0x8: /* CMGT, CMGE */
+ case 0x9: /* CMEQ, CMLE */
+ case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
g_assert_not_reached();
}
@@ -9637,19 +9647,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
- case 0xa: /* CMLT */
- if (u) {
- unallocated_encoding(s);
- return;
- }
- /* fall through */
- case 0x8: /* CMGT, CMGE */
- case 0x9: /* CMEQ, CMLE */
- if (size != 3) {
- unallocated_encoding(s);
- return;
- }
- break;
case 0x12: /* SQXTUN */
if (!u) {
unallocated_encoding(s);
@@ -9735,6 +9732,9 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
default:
case 0x3: /* USQADD / SUQADD */
case 0x7: /* SQABS / SQNEG */
+ case 0x8: /* CMGT, CMGE */
+ case 0x9: /* CMEQ, CMLE */
+ case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
unallocated_encoding(s);
return;
@@ -10107,19 +10107,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
handle_shll(s, is_q, size, rn, rd);
return;
- case 0xa: /* CMLT */
- if (u == 1) {
- unallocated_encoding(s);
- return;
- }
- /* fall through */
- case 0x8: /* CMGT, CMGE */
- case 0x9: /* CMEQ, CMLE */
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- break;
case 0xc ... 0xf:
case 0x16 ... 0x1f:
{
@@ -10293,6 +10280,9 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x4: /* CLS, CLZ */
case 0x5: /* CNT, NOT, RBIT */
case 0x7: /* SQABS, SQNEG */
+ case 0x8: /* CMGT, CMGE */
+ case 0x9: /* CMEQ, CMLE */
+ case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
unallocated_encoding(s);
return;
@@ -10313,30 +10303,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
tcg_rmode = NULL;
}
- switch (opcode) {
- case 0x8: /* CMGT, CMGE */
- if (u) {
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size);
- } else {
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cgt0, size);
- }
- return;
- case 0x9: /* CMEQ, CMLE */
- if (u) {
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cle0, size);
- } else {
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_ceq0, size);
- }
- return;
- case 0xa: /* CMLT */
- gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
- return;
- case 0x4: /* CLZ, CLS */
- case 0x5: /* CNT, NOT, RBIT */
- case 0xb:
- g_assert_not_reached();
- }
-
if (size == 3) {
/* All 64-bit element operations can be shared with scalar 2misc */
int pass;
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 29f7741bfb..4f8231d07a 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1635,6 +1635,11 @@ SQABS_s 0101 1110 ..1 00000 01111 0 ..... ..... @rr_e
SQNEG_s 0111 1110 ..1 00000 01111 0 ..... ..... @rr_e
ABS_s 0101 1110 111 00000 10111 0 ..... ..... @rr
NEG_s 0111 1110 111 00000 10111 0 ..... ..... @rr
+CMGT0_s 0101 1110 111 00000 10001 0 ..... ..... @rr
+CMGE0_s 0111 1110 111 00000 10001 0 ..... ..... @rr
+CMEQ0_s 0101 1110 111 00000 10011 0 ..... ..... @rr
+CMLE0_s 0111 1110 111 00000 10011 0 ..... ..... @rr
+CMLT0_s 0101 1110 111 00000 10101 0 ..... ..... @rr
# Advanced SIMD two-register miscellaneous
@@ -1647,3 +1652,8 @@ CLZ_v 0.10 1110 ..1 00000 01001 0 ..... ..... @qrr_e
CNT_v 0.00 1110 001 00000 01011 0 ..... ..... @qrr_b
NOT_v 0.10 1110 001 00000 01011 0 ..... ..... @qrr_b
RBIT_v 0.10 1110 011 00000 01011 0 ..... ..... @qrr_b
+CMGT0_v 0.00 1110 ..1 00000 10001 0 ..... ..... @qrr_e
+CMGE0_v 0.10 1110 ..1 00000 10001 0 ..... ..... @qrr_e
+CMEQ0_v 0.00 1110 ..1 00000 10011 0 ..... ..... @qrr_e
+CMLE0_v 0.10 1110 ..1 00000 10011 0 ..... ..... @qrr_e
+CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 40/67] target/arm: Convert CMGT, CMGE, GMLT, GMLE, CMEQ (zero) to decodetree
2024-12-01 15:05 ` [PATCH 40/67] target/arm: Convert CMGT, CMGE, GMLT, GMLE, CMEQ (zero) " Richard Henderson
@ 2024-12-06 15:06 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 15:06 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 94 +++++++++++-----------------------
> target/arm/tcg/a64.decode | 10 ++++
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 41/67] target/arm: Introduce gen_gvec_rev{16,32,64}
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (39 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 40/67] target/arm: Convert CMGT, CMGE, GMLT, GMLE, CMEQ (zero) " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:09 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 42/67] target/arm: Convert handle_rev to decodetree Richard Henderson
` (26 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate.h | 6 +++
target/arm/tcg/gengvec.c | 58 ++++++++++++++++++++++
target/arm/tcg/translate-neon.c | 88 +++++++--------------------------
3 files changed, 81 insertions(+), 71 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index cb8e1b2586..342ebedafc 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -586,6 +586,12 @@ void gen_gvec_cnt(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_rbit(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_rev16(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_rev32(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_rev64(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
/*
* Forward to the isar_feature_* tests given a DisasContext pointer.
diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c
index 85a0b50496..33c0a94958 100644
--- a/target/arm/tcg/gengvec.c
+++ b/target/arm/tcg/gengvec.c
@@ -2409,3 +2409,61 @@ void gen_gvec_rbit(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
tcg_gen_gvec_2_ool(rd_ofs, rn_ofs, opr_sz, max_sz, 0,
gen_helper_gvec_rbit_b);
}
+
+void gen_gvec_rev16(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ assert(vece == MO_8);
+ tcg_gen_gvec_rotli(MO_16, rd_ofs, rn_ofs, 8, opr_sz, max_sz);
+}
+
+static void gen_bswap32_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ tcg_gen_bswap64_i64(d, n);
+ tcg_gen_rotli_i64(d, d, 32);
+}
+
+void gen_gvec_rev32(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ static const GVecGen2 g = {
+ .fni8 = gen_bswap32_i64,
+ .fni4 = tcg_gen_bswap32_i32,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_32
+ };
+
+ switch (vece) {
+ case MO_16:
+ tcg_gen_gvec_rotli(MO_32, rd_ofs, rn_ofs, 16, opr_sz, max_sz);
+ break;
+ case MO_8:
+ tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+void gen_gvec_rev64(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ static const GVecGen2 g[] = {
+ { .fni8 = tcg_gen_bswap64_i64,
+ .vece = MO_64 },
+ { .fni8 = tcg_gen_hswap_i64,
+ .vece = MO_64 },
+ };
+
+ switch (vece) {
+ case MO_32:
+ tcg_gen_gvec_rotli(MO_64, rd_ofs, rn_ofs, 32, opr_sz, max_sz);
+ break;
+ case MO_8:
+ case MO_16:
+ tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index 50d0bf7753..ca6f5578b4 100644
--- a/target/arm/tcg/translate-neon.c
+++ b/target/arm/tcg/translate-neon.c
@@ -2565,58 +2565,6 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
return true;
}
-static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
-{
- int pass, half;
- TCGv_i32 tmp[2];
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (a->size == 3) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- tmp[0] = tcg_temp_new_i32();
- tmp[1] = tcg_temp_new_i32();
-
- for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
- for (half = 0; half < 2; half++) {
- read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32);
- switch (a->size) {
- case 0:
- tcg_gen_bswap32_i32(tmp[half], tmp[half]);
- break;
- case 1:
- gen_swap_half(tmp[half], tmp[half]);
- break;
- case 2:
- break;
- default:
- g_assert_not_reached();
- }
- }
- write_neon_element32(tmp[1], a->vd, pass * 2, MO_32);
- write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32);
- }
- return true;
-}
-
static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
NeonGenWidenFn *widenfn,
NeonGenTwo64OpFn *opfn,
@@ -3122,6 +3070,7 @@ DO_2MISC_VEC(VCGE0, gen_gvec_cge0)
DO_2MISC_VEC(VCLT0, gen_gvec_clt0)
DO_2MISC_VEC(VCLS, gen_gvec_cls)
DO_2MISC_VEC(VCLZ, gen_gvec_clz)
+DO_2MISC_VEC(VREV64, gen_gvec_rev64)
static bool trans_VMVN(DisasContext *s, arg_2misc *a)
{
@@ -3139,6 +3088,22 @@ static bool trans_VCNT(DisasContext *s, arg_2misc *a)
return do_2misc_vec(s, a, gen_gvec_cnt);
}
+static bool trans_VREV16(DisasContext *s, arg_2misc *a)
+{
+ if (a->size != 0) {
+ return false;
+ }
+ return do_2misc_vec(s, a, gen_gvec_rev16);
+}
+
+static bool trans_VREV32(DisasContext *s, arg_2misc *a)
+{
+ if (a->size != 0 && a->size != 1) {
+ return false;
+ }
+ return do_2misc_vec(s, a, gen_gvec_rev32);
+}
+
#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \
static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \
uint32_t rm_ofs, uint32_t oprsz, \
@@ -3218,25 +3183,6 @@ static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
return true;
}
-static bool trans_VREV32(DisasContext *s, arg_2misc *a)
-{
- static NeonGenOneOpFn * const fn[] = {
- tcg_gen_bswap32_i32,
- gen_swap_half,
- NULL,
- NULL,
- };
- return do_2misc(s, a, fn[a->size]);
-}
-
-static bool trans_VREV16(DisasContext *s, arg_2misc *a)
-{
- if (a->size != 0) {
- return false;
- }
- return do_2misc(s, a, gen_rev16);
-}
-
static void gen_VABS_F(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
uint32_t oprsz, uint32_t maxsz)
{
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 41/67] target/arm: Introduce gen_gvec_rev{16,32,64}
2024-12-01 15:05 ` [PATCH 41/67] target/arm: Introduce gen_gvec_rev{16,32,64} Richard Henderson
@ 2024-12-06 15:09 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 15:09 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:20, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate.h | 6 +++
> target/arm/tcg/gengvec.c | 58 ++++++++++++++++++++++
> target/arm/tcg/translate-neon.c | 88 +++++++--------------------------
> 3 files changed, 81 insertions(+), 71 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 42/67] target/arm: Convert handle_rev to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (40 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 41/67] target/arm: Introduce gen_gvec_rev{16,32,64} Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-03 11:49 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 43/67] target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c Richard Henderson
` (25 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes REV16, REV32, REV64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 79 +++-------------------------------
target/arm/tcg/a64.decode | 5 +++
2 files changed, 10 insertions(+), 74 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index bc1d0e18eb..11ccdb2d08 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8943,6 +8943,8 @@ TRANS(CMGE0_v, do_gvec_fn2, a, gen_gvec_cge0)
TRANS(CMLT0_v, do_gvec_fn2, a, gen_gvec_clt0)
TRANS(CMLE0_v, do_gvec_fn2, a, gen_gvec_cle0)
TRANS(CMEQ0_v, do_gvec_fn2, a, gen_gvec_ceq0)
+TRANS(REV16_v, do_gvec_fn2, a, gen_gvec_rev16)
+TRANS(REV32_v, do_gvec_fn2, a, gen_gvec_rev32)
static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
@@ -8957,6 +8959,7 @@ static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
TRANS(CLS_v, do_gvec_fn2_bhs, a, gen_gvec_cls)
TRANS(CLZ_v, do_gvec_fn2_bhs, a, gen_gvec_clz)
+TRANS(REV64_v, do_gvec_fn2_bhs, a, gen_gvec_rev64)
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
@@ -9886,76 +9889,6 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
}
}
-static void handle_rev(DisasContext *s, int opcode, bool u,
- bool is_q, int size, int rn, int rd)
-{
- int op = (opcode << 1) | u;
- int opsz = op + size;
- int grp_size = 3 - opsz;
- int dsize = is_q ? 128 : 64;
- int i;
-
- if (opsz >= 3) {
- unallocated_encoding(s);
- return;
- }
-
- if (!fp_access_check(s)) {
- return;
- }
-
- if (size == 0) {
- /* Special case bytes, use bswap op on each group of elements */
- int groups = dsize / (8 << grp_size);
-
- for (i = 0; i < groups; i++) {
- TCGv_i64 tcg_tmp = tcg_temp_new_i64();
-
- read_vec_element(s, tcg_tmp, rn, i, grp_size);
- switch (grp_size) {
- case MO_16:
- tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ);
- break;
- case MO_32:
- tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ);
- break;
- case MO_64:
- tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
- break;
- default:
- g_assert_not_reached();
- }
- write_vec_element(s, tcg_tmp, rd, i, grp_size);
- }
- clear_vec_high(s, is_q, rd);
- } else {
- int revmask = (1 << grp_size) - 1;
- int esize = 8 << size;
- int elements = dsize / esize;
- TCGv_i64 tcg_rn = tcg_temp_new_i64();
- TCGv_i64 tcg_rd[2];
-
- for (i = 0; i < 2; i++) {
- tcg_rd[i] = tcg_temp_new_i64();
- tcg_gen_movi_i64(tcg_rd[i], 0);
- }
-
- for (i = 0; i < elements; i++) {
- int e_rev = (i & 0xf) ^ revmask;
- int w = (e_rev * esize) / 64;
- int o = (e_rev * esize) % 64;
-
- read_vec_element(s, tcg_rn, rn, i, size);
- tcg_gen_deposit_i64(tcg_rd[w], tcg_rd[w], tcg_rn, o, esize);
- }
-
- for (i = 0; i < 2; i++) {
- write_vec_element(s, tcg_rd[i], rd, i, MO_64);
- }
- clear_vec_high(s, true, rd);
- }
-}
-
static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
bool is_q, int size, int rn, int rd)
{
@@ -10070,10 +10003,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
- case 0x0: /* REV64, REV32 */
- case 0x1: /* REV16 */
- handle_rev(s, opcode, u, is_q, size, rn, rd);
- return;
case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
if (size == 3) {
@@ -10276,6 +10205,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
break;
}
default:
+ case 0x0: /* REV64 */
+ case 0x1: /* REV16, REV32 */
case 0x3: /* SUQADD, USQADD */
case 0x4: /* CLS, CLZ */
case 0x5: /* CNT, NOT, RBIT */
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 4f8231d07a..2531809096 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -73,6 +73,7 @@
@qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0
@qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1
+@qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e
@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
@@ -1657,3 +1658,7 @@ CMGE0_v 0.10 1110 ..1 00000 10001 0 ..... ..... @qrr_e
CMEQ0_v 0.00 1110 ..1 00000 10011 0 ..... ..... @qrr_e
CMLE0_v 0.10 1110 ..1 00000 10011 0 ..... ..... @qrr_e
CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e
+
+REV16_v 0.00 1110 001 00000 00011 0 ..... ..... @qrr_b
+REV32_v 0.10 1110 0.1 00000 00011 0 ..... ..... @qrr_bh
+REV64_v 0.00 1110 ..1 00000 00001 0 ..... ..... @qrr_e
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 42/67] target/arm: Convert handle_rev to decodetree
2024-12-01 15:05 ` [PATCH 42/67] target/arm: Convert handle_rev to decodetree Richard Henderson
@ 2024-12-03 11:49 ` Peter Maydell
2024-12-03 14:09 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-03 11:49 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:16, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This includes REV16, REV32, REV64.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> @@ -10070,10 +10003,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
> TCGv_ptr tcg_fpstatus;
>
> switch (opcode) {
> - case 0x0: /* REV64, REV32 */
> - case 0x1: /* REV16 */
> - handle_rev(s, opcode, u, is_q, size, rn, rd);
> - return;
> case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
> case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
> if (size == 3) {
> @@ -10276,6 +10205,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
> break;
> }
> default:
> + case 0x0: /* REV64 */
> + case 0x1: /* REV16, REV32 */
REV32 is case 0x0, not 0x1, per the comments deleted above.
> case 0x3: /* SUQADD, USQADD */
> case 0x4: /* CLS, CLZ */
> case 0x5: /* CNT, NOT, RBIT */
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index 4f8231d07a..2531809096 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -73,6 +73,7 @@
>
> @qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0
> @qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1
> +@qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e
> @qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
>
> @qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
> @@ -1657,3 +1658,7 @@ CMGE0_v 0.10 1110 ..1 00000 10001 0 ..... ..... @qrr_e
> CMEQ0_v 0.00 1110 ..1 00000 10011 0 ..... ..... @qrr_e
> CMLE0_v 0.10 1110 ..1 00000 10011 0 ..... ..... @qrr_e
> CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e
> +
> +REV16_v 0.00 1110 001 00000 00011 0 ..... ..... @qrr_b
> +REV32_v 0.10 1110 0.1 00000 00011 0 ..... ..... @qrr_bh
> +REV64_v 0.00 1110 ..1 00000 00001 0 ..... ..... @qrr_e
This doesn't look quite right -- in the decode table in C4.1.96.21,
2-reg misc REV32 is opcode 00000, like REV64, not 00001 like REV16.
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1660,5 +1660,5 @@ CMLE0_v 0.10 1110 ..1 00000 10011 0
..... ..... @qrr_e
CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e
REV16_v 0.00 1110 001 00000 00011 0 ..... ..... @qrr_b
-REV32_v 0.10 1110 0.1 00000 00011 0 ..... ..... @qrr_bh
+REV32_v 0.10 1110 0.1 00000 00001 0 ..... ..... @qrr_bh
REV64_v 0.00 1110 ..1 00000 00001 0 ..... ..... @qrr_e
should I think be the right fixup.
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 42/67] target/arm: Convert handle_rev to decodetree
2024-12-03 11:49 ` Peter Maydell
@ 2024-12-03 14:09 ` Richard Henderson
0 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-03 14:09 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 12/3/24 05:49, Peter Maydell wrote:
> On Sun, 1 Dec 2024 at 15:16, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> This includes REV16, REV32, REV64.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>
>> @@ -10070,10 +10003,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>> TCGv_ptr tcg_fpstatus;
>>
>> switch (opcode) {
>> - case 0x0: /* REV64, REV32 */
>> - case 0x1: /* REV16 */
>> - handle_rev(s, opcode, u, is_q, size, rn, rd);
>> - return;
>> case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
>> case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
>> if (size == 3) {
>> @@ -10276,6 +10205,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
>> break;
>> }
>> default:
>> + case 0x0: /* REV64 */
>> + case 0x1: /* REV16, REV32 */
>
> REV32 is case 0x0, not 0x1, per the comments deleted above.
>
>> case 0x3: /* SUQADD, USQADD */
>> case 0x4: /* CLS, CLZ */
>> case 0x5: /* CNT, NOT, RBIT */
>> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
>> index 4f8231d07a..2531809096 100644
>> --- a/target/arm/tcg/a64.decode
>> +++ b/target/arm/tcg/a64.decode
>> @@ -73,6 +73,7 @@
>>
>> @qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0
>> @qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1
>> +@qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e
>> @qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
>>
>> @qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
>> @@ -1657,3 +1658,7 @@ CMGE0_v 0.10 1110 ..1 00000 10001 0 ..... ..... @qrr_e
>> CMEQ0_v 0.00 1110 ..1 00000 10011 0 ..... ..... @qrr_e
>> CMLE0_v 0.10 1110 ..1 00000 10011 0 ..... ..... @qrr_e
>> CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e
>> +
>> +REV16_v 0.00 1110 001 00000 00011 0 ..... ..... @qrr_b
>> +REV32_v 0.10 1110 0.1 00000 00011 0 ..... ..... @qrr_bh
>> +REV64_v 0.00 1110 ..1 00000 00001 0 ..... ..... @qrr_e
>
> This doesn't look quite right -- in the decode table in C4.1.96.21,
> 2-reg misc REV32 is opcode 00000, like REV64, not 00001 like REV16.
>
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -1660,5 +1660,5 @@ CMLE0_v 0.10 1110 ..1 00000 10011 0
> ..... ..... @qrr_e
> CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e
>
> REV16_v 0.00 1110 001 00000 00011 0 ..... ..... @qrr_b
> -REV32_v 0.10 1110 0.1 00000 00011 0 ..... ..... @qrr_bh
> +REV32_v 0.10 1110 0.1 00000 00001 0 ..... ..... @qrr_bh
> REV64_v 0.00 1110 ..1 00000 00001 0 ..... ..... @qrr_e
>
> should I think be the right fixup.
Yep, my bad. I remember "fixing" the comment, because I thought it was off. I must have
been tired, or something. Odd that this passes risu... maybe we're missing a pattern.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 43/67] target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (41 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 42/67] target/arm: Convert handle_rev to decodetree Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:10 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 44/67] target/arm: Introduce gen_gvec_{s,u}{add,ada}lp Richard Henderson
` (24 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Move from helper-a64.c to neon_helper.c so that these
functions are available for arm32 code as well.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 2 ++
target/arm/tcg/helper-a64.h | 2 --
target/arm/tcg/helper-a64.c | 43 ------------------------------------
target/arm/tcg/neon_helper.c | 43 ++++++++++++++++++++++++++++++++++++
4 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 167e331a83..57e0ce387b 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -399,6 +399,8 @@ DEF_HELPER_2(neon_addl_u16, i64, i64, i64)
DEF_HELPER_2(neon_addl_u32, i64, i64, i64)
DEF_HELPER_2(neon_paddl_u16, i64, i64, i64)
DEF_HELPER_2(neon_paddl_u32, i64, i64, i64)
+DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_2(neon_subl_u16, i64, i64, i64)
DEF_HELPER_2(neon_subl_u32, i64, i64, i64)
DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64)
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
index 203b7b7ac8..f811bb85dc 100644
--- a/target/arm/tcg/helper-a64.h
+++ b/target/arm/tcg/helper-a64.h
@@ -41,9 +41,7 @@ DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
-DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(neon_addlp_u8, TCG_CALL_NO_RWG_SE, i64, i64)
-DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 3f4d7b9aba..9b3c407be3 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -306,39 +306,6 @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
}
-/* Pairwise long add: add pairs of adjacent elements into
- * double-width elements in the result (eg _s8 is an 8x8->16 op)
- */
-uint64_t HELPER(neon_addlp_s8)(uint64_t a)
-{
- uint64_t nsignmask = 0x0080008000800080ULL;
- uint64_t wsignmask = 0x8000800080008000ULL;
- uint64_t elementmask = 0x00ff00ff00ff00ffULL;
- uint64_t tmp1, tmp2;
- uint64_t res, signres;
-
- /* Extract odd elements, sign extend each to a 16 bit field */
- tmp1 = a & elementmask;
- tmp1 ^= nsignmask;
- tmp1 |= wsignmask;
- tmp1 = (tmp1 - nsignmask) ^ wsignmask;
- /* Ditto for the even elements */
- tmp2 = (a >> 8) & elementmask;
- tmp2 ^= nsignmask;
- tmp2 |= wsignmask;
- tmp2 = (tmp2 - nsignmask) ^ wsignmask;
-
- /* calculate the result by summing bits 0..14, 16..22, etc,
- * and then adjusting the sign bits 15, 23, etc manually.
- * This ensures the addition can't overflow the 16 bit field.
- */
- signres = (tmp1 ^ tmp2) & wsignmask;
- res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
- res ^= signres;
-
- return res;
-}
-
uint64_t HELPER(neon_addlp_u8)(uint64_t a)
{
uint64_t tmp;
@@ -348,16 +315,6 @@ uint64_t HELPER(neon_addlp_u8)(uint64_t a)
return tmp;
}
-uint64_t HELPER(neon_addlp_s16)(uint64_t a)
-{
- int32_t reslo, reshi;
-
- reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
- reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
-
- return (uint32_t)reslo | (((uint64_t)reshi) << 32);
-}
-
uint64_t HELPER(neon_addlp_u16)(uint64_t a)
{
uint64_t tmp;
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
index 4e501925de..b92ddd4914 100644
--- a/target/arm/tcg/neon_helper.c
+++ b/target/arm/tcg/neon_helper.c
@@ -866,6 +866,49 @@ uint64_t HELPER(neon_paddl_u32)(uint64_t a, uint64_t b)
return low + ((uint64_t)high << 32);
}
+/* Pairwise long add: add pairs of adjacent elements into
+ * double-width elements in the result (eg _s8 is an 8x8->16 op)
+ */
+uint64_t HELPER(neon_addlp_s8)(uint64_t a)
+{
+ uint64_t nsignmask = 0x0080008000800080ULL;
+ uint64_t wsignmask = 0x8000800080008000ULL;
+ uint64_t elementmask = 0x00ff00ff00ff00ffULL;
+ uint64_t tmp1, tmp2;
+ uint64_t res, signres;
+
+ /* Extract odd elements, sign extend each to a 16 bit field */
+ tmp1 = a & elementmask;
+ tmp1 ^= nsignmask;
+ tmp1 |= wsignmask;
+ tmp1 = (tmp1 - nsignmask) ^ wsignmask;
+ /* Ditto for the even elements */
+ tmp2 = (a >> 8) & elementmask;
+ tmp2 ^= nsignmask;
+ tmp2 |= wsignmask;
+ tmp2 = (tmp2 - nsignmask) ^ wsignmask;
+
+ /* calculate the result by summing bits 0..14, 16..22, etc,
+ * and then adjusting the sign bits 15, 23, etc manually.
+ * This ensures the addition can't overflow the 16 bit field.
+ */
+ signres = (tmp1 ^ tmp2) & wsignmask;
+ res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
+ res ^= signres;
+
+ return res;
+}
+
+uint64_t HELPER(neon_addlp_s16)(uint64_t a)
+{
+ int32_t reslo, reshi;
+
+ reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
+ reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
+
+ return (uint32_t)reslo | (((uint64_t)reshi) << 32);
+}
+
uint64_t HELPER(neon_subl_u16)(uint64_t a, uint64_t b)
{
uint64_t mask;
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 43/67] target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c
2024-12-01 15:05 ` [PATCH 43/67] target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c Richard Henderson
@ 2024-12-06 15:10 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 15:10 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:20, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Move from helper-a64.c to neon_helper.c so that these
> functions are available for arm32 code as well.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.h | 2 ++
> target/arm/tcg/helper-a64.h | 2 --
> target/arm/tcg/helper-a64.c | 43 ------------------------------------
> target/arm/tcg/neon_helper.c | 43 ++++++++++++++++++++++++++++++++++++
> 4 files changed, 45 insertions(+), 45 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 44/67] target/arm: Introduce gen_gvec_{s,u}{add,ada}lp
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (42 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 43/67] target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:36 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 45/67] target/arm: Convert handle_2misc_pairwise to decodetree Richard Henderson
` (23 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Pairwise addition with and without accumulation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 2 -
target/arm/tcg/translate.h | 9 ++
target/arm/tcg/gengvec.c | 230 ++++++++++++++++++++++++++++++++
target/arm/tcg/neon_helper.c | 22 ---
target/arm/tcg/translate-neon.c | 150 +--------------------
5 files changed, 243 insertions(+), 170 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 57e0ce387b..6369d07d05 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -397,8 +397,6 @@ DEF_HELPER_1(neon_widen_s16, i64, i32)
DEF_HELPER_2(neon_addl_u16, i64, i64, i64)
DEF_HELPER_2(neon_addl_u32, i64, i64, i64)
-DEF_HELPER_2(neon_paddl_u16, i64, i64, i64)
-DEF_HELPER_2(neon_paddl_u32, i64, i64, i64)
DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_2(neon_subl_u16, i64, i64, i64)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 342ebedafc..edd775d564 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -593,6 +593,15 @@ void gen_gvec_rev32(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
void gen_gvec_rev64(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_saddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_sadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_uaddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_uadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+
/*
* Forward to the isar_feature_* tests given a DisasContext pointer.
*/
diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c
index 33c0a94958..2755da8ac7 100644
--- a/target/arm/tcg/gengvec.c
+++ b/target/arm/tcg/gengvec.c
@@ -2467,3 +2467,233 @@ void gen_gvec_rev64(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
g_assert_not_reached();
}
}
+
+static void gen_saddlp_vec(unsigned vece, TCGv_vec d, TCGv_vec n)
+{
+ int half = 4 << vece;
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+
+ tcg_gen_shli_vec(vece, t, n, half);
+ tcg_gen_sari_vec(vece, d, n, half);
+ tcg_gen_sari_vec(vece, t, t, half);
+ tcg_gen_add_vec(vece, d, d, t);
+}
+
+static void gen_saddlp_s_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_ext32s_i64(t, n);
+ tcg_gen_sari_i64(d, n, 32);
+ tcg_gen_add_i64(d, d, t);
+}
+
+void gen_gvec_saddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_sari_vec, INDEX_op_shli_vec, INDEX_op_add_vec, 0
+ };
+ static const GVecGen2 g[] = {
+ { .fniv = gen_saddlp_vec,
+ .fni8 = gen_helper_neon_addlp_s8,
+ .opt_opc = vecop_list,
+ .vece = MO_16 },
+ { .fniv = gen_saddlp_vec,
+ .fni8 = gen_helper_neon_addlp_s16,
+ .opt_opc = vecop_list,
+ .vece = MO_32 },
+ { .fniv = gen_saddlp_vec,
+ .fni8 = gen_saddlp_s_i64,
+ .opt_opc = vecop_list,
+ .vece = MO_64 },
+ };
+ assert(vece <= MO_32);
+ tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
+}
+
+static void gen_sadalp_vec(unsigned vece, TCGv_vec d, TCGv_vec n)
+{
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+
+ gen_saddlp_vec(vece, t, n);
+ tcg_gen_add_vec(vece, d, d, t);
+}
+
+static void gen_sadalp_b_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ gen_helper_neon_addlp_s8(t, n);
+ tcg_gen_vec_add16_i64(d, d, t);
+}
+
+static void gen_sadalp_h_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ gen_helper_neon_addlp_s16(t, n);
+ tcg_gen_vec_add32_i64(d, d, t);
+}
+
+static void gen_sadalp_s_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ gen_saddlp_s_i64(t, n);
+ tcg_gen_add_i64(d, d, t);
+}
+
+void gen_gvec_sadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_sari_vec, INDEX_op_shli_vec, INDEX_op_add_vec, 0
+ };
+ static const GVecGen2 g[] = {
+ { .fniv = gen_sadalp_vec,
+ .fni8 = gen_sadalp_b_i64,
+ .opt_opc = vecop_list,
+ .load_dest = true,
+ .vece = MO_16 },
+ { .fniv = gen_sadalp_vec,
+ .fni8 = gen_sadalp_h_i64,
+ .opt_opc = vecop_list,
+ .load_dest = true,
+ .vece = MO_32 },
+ { .fniv = gen_sadalp_vec,
+ .fni8 = gen_sadalp_s_i64,
+ .opt_opc = vecop_list,
+ .load_dest = true,
+ .vece = MO_64 },
+ };
+ assert(vece <= MO_32);
+ tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
+}
+
+static void gen_uaddlp_vec(unsigned vece, TCGv_vec d, TCGv_vec n)
+{
+ int half = 4 << vece;
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_constant_vec_matching(d, vece, MAKE_64BIT_MASK(0, half));
+
+ tcg_gen_shri_vec(vece, t, n, half);
+ tcg_gen_and_vec(vece, d, n, m);
+ tcg_gen_add_vec(vece, d, d, t);
+}
+
+static void gen_uaddlp_b_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+ TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0xff));
+
+ tcg_gen_shri_i64(t, n, 8);
+ tcg_gen_and_i64(d, n, m);
+ tcg_gen_and_i64(t, t, m);
+ /* No carry between widened unsigned elements. */
+ tcg_gen_add_i64(d, d, t);
+}
+
+static void gen_uaddlp_h_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+ TCGv_i64 m = tcg_constant_i64(dup_const(MO_32, 0xffff));
+
+ tcg_gen_shri_i64(t, n, 16);
+ tcg_gen_and_i64(d, n, m);
+ tcg_gen_and_i64(t, t, m);
+ /* No carry between widened unsigned elements. */
+ tcg_gen_add_i64(d, d, t);
+}
+
+static void gen_uaddlp_s_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_ext32u_i64(t, n);
+ tcg_gen_shri_i64(d, n, 32);
+ tcg_gen_add_i64(d, d, t);
+}
+
+void gen_gvec_uaddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_shri_vec, INDEX_op_add_vec, 0
+ };
+ static const GVecGen2 g[] = {
+ { .fniv = gen_uaddlp_vec,
+ .fni8 = gen_uaddlp_b_i64,
+ .opt_opc = vecop_list,
+ .vece = MO_16 },
+ { .fniv = gen_uaddlp_vec,
+ .fni8 = gen_uaddlp_h_i64,
+ .opt_opc = vecop_list,
+ .vece = MO_32 },
+ { .fniv = gen_uaddlp_vec,
+ .fni8 = gen_uaddlp_s_i64,
+ .opt_opc = vecop_list,
+ .vece = MO_64 },
+ };
+ assert(vece <= MO_32);
+ tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
+}
+
+static void gen_uadalp_vec(unsigned vece, TCGv_vec d, TCGv_vec n)
+{
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+
+ gen_uaddlp_vec(vece, t, n);
+ tcg_gen_add_vec(vece, d, d, t);
+}
+
+static void gen_uadalp_b_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ gen_uaddlp_b_i64(t, n);
+ tcg_gen_vec_add16_i64(d, d, t);
+}
+
+static void gen_uadalp_h_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ gen_uaddlp_h_i64(t, n);
+ tcg_gen_vec_add32_i64(d, d, t);
+}
+
+static void gen_uadalp_s_i64(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ gen_uaddlp_s_i64(t, n);
+ tcg_gen_add_i64(d, d, t);
+}
+
+void gen_gvec_uadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_shri_vec, INDEX_op_add_vec, 0
+ };
+ static const GVecGen2 g[] = {
+ { .fniv = gen_uadalp_vec,
+ .fni8 = gen_uadalp_b_i64,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_16 },
+ { .fniv = gen_uadalp_vec,
+ .fni8 = gen_uadalp_h_i64,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_32 },
+ { .fniv = gen_uadalp_vec,
+ .fni8 = gen_uadalp_s_i64,
+ .load_dest = true,
+ .opt_opc = vecop_list,
+ .vece = MO_64 },
+ };
+ assert(vece <= MO_32);
+ tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
+}
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
index b92ddd4914..1a22857b5e 100644
--- a/target/arm/tcg/neon_helper.c
+++ b/target/arm/tcg/neon_helper.c
@@ -844,28 +844,6 @@ uint64_t HELPER(neon_addl_u32)(uint64_t a, uint64_t b)
return (a + b) ^ mask;
}
-uint64_t HELPER(neon_paddl_u16)(uint64_t a, uint64_t b)
-{
- uint64_t tmp;
- uint64_t tmp2;
-
- tmp = a & 0x0000ffff0000ffffull;
- tmp += (a >> 16) & 0x0000ffff0000ffffull;
- tmp2 = b & 0xffff0000ffff0000ull;
- tmp2 += (b << 16) & 0xffff0000ffff0000ull;
- return ( tmp & 0xffff)
- | ((tmp >> 16) & 0xffff0000ull)
- | ((tmp2 << 16) & 0xffff00000000ull)
- | ( tmp2 & 0xffff000000000000ull);
-}
-
-uint64_t HELPER(neon_paddl_u32)(uint64_t a, uint64_t b)
-{
- uint32_t low = a + (a >> 32);
- uint32_t high = b + (b >> 32);
- return low + ((uint64_t)high << 32);
-}
-
/* Pairwise long add: add pairs of adjacent elements into
* double-width elements in the result (eg _s8 is an 8x8->16 op)
*/
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index ca6f5578b4..19a18018f1 100644
--- a/target/arm/tcg/translate-neon.c
+++ b/target/arm/tcg/translate-neon.c
@@ -2565,152 +2565,6 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
return true;
}
-static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
- NeonGenWidenFn *widenfn,
- NeonGenTwo64OpFn *opfn,
- NeonGenTwo64OpFn *accfn)
-{
- /*
- * Pairwise long operations: widen both halves of the pair,
- * combine the pairs with the opfn, and then possibly accumulate
- * into the destination with the accfn.
- */
- int pass;
-
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vd | a->vm) & 0x10)) {
- return false;
- }
-
- if ((a->vd | a->vm) & a->q) {
- return false;
- }
-
- if (!widenfn) {
- return false;
- }
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- for (pass = 0; pass < a->q + 1; pass++) {
- TCGv_i32 tmp;
- TCGv_i64 rm0_64, rm1_64, rd_64;
-
- rm0_64 = tcg_temp_new_i64();
- rm1_64 = tcg_temp_new_i64();
- rd_64 = tcg_temp_new_i64();
-
- tmp = tcg_temp_new_i32();
- read_neon_element32(tmp, a->vm, pass * 2, MO_32);
- widenfn(rm0_64, tmp);
- read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32);
- widenfn(rm1_64, tmp);
-
- opfn(rd_64, rm0_64, rm1_64);
-
- if (accfn) {
- TCGv_i64 tmp64 = tcg_temp_new_i64();
- read_neon_element64(tmp64, a->vd, pass, MO_64);
- accfn(rd_64, tmp64, rd_64);
- }
- write_neon_element64(rd_64, a->vd, pass, MO_64);
- }
- return true;
-}
-
-static bool trans_VPADDL_S(DisasContext *s, arg_2misc *a)
-{
- static NeonGenWidenFn * const widenfn[] = {
- gen_helper_neon_widen_s8,
- gen_helper_neon_widen_s16,
- tcg_gen_ext_i32_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const opfn[] = {
- gen_helper_neon_paddl_u16,
- gen_helper_neon_paddl_u32,
- tcg_gen_add_i64,
- NULL,
- };
-
- return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL);
-}
-
-static bool trans_VPADDL_U(DisasContext *s, arg_2misc *a)
-{
- static NeonGenWidenFn * const widenfn[] = {
- gen_helper_neon_widen_u8,
- gen_helper_neon_widen_u16,
- tcg_gen_extu_i32_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const opfn[] = {
- gen_helper_neon_paddl_u16,
- gen_helper_neon_paddl_u32,
- tcg_gen_add_i64,
- NULL,
- };
-
- return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL);
-}
-
-static bool trans_VPADAL_S(DisasContext *s, arg_2misc *a)
-{
- static NeonGenWidenFn * const widenfn[] = {
- gen_helper_neon_widen_s8,
- gen_helper_neon_widen_s16,
- tcg_gen_ext_i32_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const opfn[] = {
- gen_helper_neon_paddl_u16,
- gen_helper_neon_paddl_u32,
- tcg_gen_add_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const accfn[] = {
- gen_helper_neon_addl_u16,
- gen_helper_neon_addl_u32,
- tcg_gen_add_i64,
- NULL,
- };
-
- return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
- accfn[a->size]);
-}
-
-static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a)
-{
- static NeonGenWidenFn * const widenfn[] = {
- gen_helper_neon_widen_u8,
- gen_helper_neon_widen_u16,
- tcg_gen_extu_i32_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const opfn[] = {
- gen_helper_neon_paddl_u16,
- gen_helper_neon_paddl_u32,
- tcg_gen_add_i64,
- NULL,
- };
- static NeonGenTwo64OpFn * const accfn[] = {
- gen_helper_neon_addl_u16,
- gen_helper_neon_addl_u32,
- tcg_gen_add_i64,
- NULL,
- };
-
- return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size],
- accfn[a->size]);
-}
-
typedef void ZipFn(TCGv_ptr, TCGv_ptr);
static bool do_zip_uzp(DisasContext *s, arg_2misc *a,
@@ -3071,6 +2925,10 @@ DO_2MISC_VEC(VCLT0, gen_gvec_clt0)
DO_2MISC_VEC(VCLS, gen_gvec_cls)
DO_2MISC_VEC(VCLZ, gen_gvec_clz)
DO_2MISC_VEC(VREV64, gen_gvec_rev64)
+DO_2MISC_VEC(VPADDL_S, gen_gvec_saddlp)
+DO_2MISC_VEC(VPADDL_U, gen_gvec_uaddlp)
+DO_2MISC_VEC(VPADAL_S, gen_gvec_sadalp)
+DO_2MISC_VEC(VPADAL_U, gen_gvec_uadalp)
static bool trans_VMVN(DisasContext *s, arg_2misc *a)
{
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 44/67] target/arm: Introduce gen_gvec_{s,u}{add,ada}lp
2024-12-01 15:05 ` [PATCH 44/67] target/arm: Introduce gen_gvec_{s,u}{add,ada}lp Richard Henderson
@ 2024-12-06 15:36 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 15:36 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:12, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Pairwise addition with and without accumulation.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper.h | 2 -
> target/arm/tcg/translate.h | 9 ++
> target/arm/tcg/gengvec.c | 230 ++++++++++++++++++++++++++++++++
> target/arm/tcg/neon_helper.c | 22 ---
> target/arm/tcg/translate-neon.c | 150 +--------------------
> 5 files changed, 243 insertions(+), 170 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 45/67] target/arm: Convert handle_2misc_pairwise to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (43 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 44/67] target/arm: Introduce gen_gvec_{s,u}{add,ada}lp Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:37 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 46/67] target/arm: Remove helper_neon_{add,sub}l_u{16,32} Richard Henderson
` (22 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes SADDLP, UADDLP, SADALP, UADALP.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/helper-a64.h | 2 -
target/arm/tcg/helper-a64.c | 18 --------
target/arm/tcg/translate-a64.c | 84 +++-------------------------------
target/arm/tcg/a64.decode | 5 ++
4 files changed, 11 insertions(+), 98 deletions(-)
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
index f811bb85dc..ac7ca190fa 100644
--- a/target/arm/tcg/helper-a64.h
+++ b/target/arm/tcg/helper-a64.h
@@ -41,8 +41,6 @@ DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr)
DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr)
-DEF_HELPER_FLAGS_1(neon_addlp_u8, TCG_CALL_NO_RWG_SE, i64, i64)
-DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr)
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 9b3c407be3..3de564e0fe 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -306,24 +306,6 @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
}
-uint64_t HELPER(neon_addlp_u8)(uint64_t a)
-{
- uint64_t tmp;
-
- tmp = a & 0x00ff00ff00ff00ffULL;
- tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
- return tmp;
-}
-
-uint64_t HELPER(neon_addlp_u16)(uint64_t a)
-{
- uint64_t tmp;
-
- tmp = a & 0x0000ffff0000ffffULL;
- tmp += (a >> 16) & 0x0000ffff0000ffffULL;
- return tmp;
-}
-
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
{
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 11ccdb2d08..c6cc1c9e09 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8960,6 +8960,10 @@ static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
TRANS(CLS_v, do_gvec_fn2_bhs, a, gen_gvec_cls)
TRANS(CLZ_v, do_gvec_fn2_bhs, a, gen_gvec_clz)
TRANS(REV64_v, do_gvec_fn2_bhs, a, gen_gvec_rev64)
+TRANS(SADDLP_v, do_gvec_fn2_bhs, a, gen_gvec_saddlp)
+TRANS(UADDLP_v, do_gvec_fn2_bhs, a, gen_gvec_uaddlp)
+TRANS(SADALP_v, do_gvec_fn2_bhs, a, gen_gvec_sadalp)
+TRANS(UADALP_v, do_gvec_fn2_bhs, a, gen_gvec_uadalp)
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
@@ -9889,73 +9893,6 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
}
}
-static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
- bool is_q, int size, int rn, int rd)
-{
- /* Implement the pairwise operations from 2-misc:
- * SADDLP, UADDLP, SADALP, UADALP.
- * These all add pairs of elements in the input to produce a
- * double-width result element in the output (possibly accumulating).
- */
- bool accum = (opcode == 0x6);
- int maxpass = is_q ? 2 : 1;
- int pass;
- TCGv_i64 tcg_res[2];
-
- if (size == 2) {
- /* 32 + 32 -> 64 op */
- MemOp memop = size + (u ? 0 : MO_SIGN);
-
- for (pass = 0; pass < maxpass; pass++) {
- TCGv_i64 tcg_op1 = tcg_temp_new_i64();
- TCGv_i64 tcg_op2 = tcg_temp_new_i64();
-
- tcg_res[pass] = tcg_temp_new_i64();
-
- read_vec_element(s, tcg_op1, rn, pass * 2, memop);
- read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop);
- tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
- if (accum) {
- read_vec_element(s, tcg_op1, rd, pass, MO_64);
- tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
- }
- }
- } else {
- for (pass = 0; pass < maxpass; pass++) {
- TCGv_i64 tcg_op = tcg_temp_new_i64();
- NeonGenOne64OpFn *genfn;
- static NeonGenOne64OpFn * const fns[2][2] = {
- { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 },
- { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 },
- };
-
- genfn = fns[size][u];
-
- tcg_res[pass] = tcg_temp_new_i64();
-
- read_vec_element(s, tcg_op, rn, pass, MO_64);
- genfn(tcg_res[pass], tcg_op);
-
- if (accum) {
- read_vec_element(s, tcg_op, rd, pass, MO_64);
- if (size == 0) {
- gen_helper_neon_addl_u16(tcg_res[pass],
- tcg_res[pass], tcg_op);
- } else {
- gen_helper_neon_addl_u32(tcg_res[pass],
- tcg_res[pass], tcg_op);
- }
- }
- }
- }
- if (!is_q) {
- tcg_res[1] = tcg_constant_i64(0);
- }
- for (pass = 0; pass < 2; pass++) {
- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
- }
-}
-
static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
{
/* Implement SHLL and SHLL2 */
@@ -10015,17 +9952,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
return;
- case 0x2: /* SADDLP, UADDLP */
- case 0x6: /* SADALP, UADALP */
- if (size == 3) {
- unallocated_encoding(s);
- return;
- }
- if (!fp_access_check(s)) {
- return;
- }
- handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd);
- return;
case 0x13: /* SHLL, SHLL2 */
if (u == 0 || size == 3) {
unallocated_encoding(s);
@@ -10207,9 +10133,11 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
default:
case 0x0: /* REV64 */
case 0x1: /* REV16, REV32 */
+ case 0x2: /* SADDLP, UADDLP */
case 0x3: /* SUQADD, USQADD */
case 0x4: /* CLS, CLZ */
case 0x5: /* CNT, NOT, RBIT */
+ case 0x6: /* SADALP, UADALP */
case 0x7: /* SQABS, SQNEG */
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 2531809096..77020bb175 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1662,3 +1662,8 @@ CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e
REV16_v 0.00 1110 001 00000 00011 0 ..... ..... @qrr_b
REV32_v 0.10 1110 0.1 00000 00011 0 ..... ..... @qrr_bh
REV64_v 0.00 1110 ..1 00000 00001 0 ..... ..... @qrr_e
+
+SADDLP_v 0.00 1110 ..1 00000 00101 0 ..... ..... @qrr_e
+UADDLP_v 0.10 1110 ..1 00000 00101 0 ..... ..... @qrr_e
+SADALP_v 0.00 1110 ..1 00000 01101 0 ..... ..... @qrr_e
+UADALP_v 0.10 1110 ..1 00000 01101 0 ..... ..... @qrr_e
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 46/67] target/arm: Remove helper_neon_{add,sub}l_u{16,32}
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (44 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 45/67] target/arm: Convert handle_2misc_pairwise to decodetree Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:15 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 47/67] target/arm: Introduce clear_vec Richard Henderson
` (21 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
These have generic equivalents: tcg_gen_vec_{add,sub}{16,32}_i64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 4 ----
target/arm/tcg/neon_helper.c | 36 ---------------------------------
target/arm/tcg/translate-neon.c | 22 ++++++++++----------
3 files changed, 11 insertions(+), 51 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 6369d07d05..04e422ab08 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -395,12 +395,8 @@ DEF_HELPER_1(neon_widen_s8, i64, i32)
DEF_HELPER_1(neon_widen_u16, i64, i32)
DEF_HELPER_1(neon_widen_s16, i64, i32)
-DEF_HELPER_2(neon_addl_u16, i64, i64, i64)
-DEF_HELPER_2(neon_addl_u32, i64, i64, i64)
DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64)
-DEF_HELPER_2(neon_subl_u16, i64, i64, i64)
-DEF_HELPER_2(neon_subl_u32, i64, i64, i64)
DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64)
DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64)
DEF_HELPER_2(neon_abdl_u16, i64, i32, i32)
diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c
index 1a22857b5e..c687e882ad 100644
--- a/target/arm/tcg/neon_helper.c
+++ b/target/arm/tcg/neon_helper.c
@@ -826,24 +826,6 @@ uint64_t HELPER(neon_widen_s16)(uint32_t x)
return ((uint32_t)(int16_t)x) | (high << 32);
}
-uint64_t HELPER(neon_addl_u16)(uint64_t a, uint64_t b)
-{
- uint64_t mask;
- mask = (a ^ b) & 0x8000800080008000ull;
- a &= ~0x8000800080008000ull;
- b &= ~0x8000800080008000ull;
- return (a + b) ^ mask;
-}
-
-uint64_t HELPER(neon_addl_u32)(uint64_t a, uint64_t b)
-{
- uint64_t mask;
- mask = (a ^ b) & 0x8000000080000000ull;
- a &= ~0x8000000080000000ull;
- b &= ~0x8000000080000000ull;
- return (a + b) ^ mask;
-}
-
/* Pairwise long add: add pairs of adjacent elements into
* double-width elements in the result (eg _s8 is an 8x8->16 op)
*/
@@ -887,24 +869,6 @@ uint64_t HELPER(neon_addlp_s16)(uint64_t a)
return (uint32_t)reslo | (((uint64_t)reshi) << 32);
}
-uint64_t HELPER(neon_subl_u16)(uint64_t a, uint64_t b)
-{
- uint64_t mask;
- mask = (a ^ ~b) & 0x8000800080008000ull;
- a |= 0x8000800080008000ull;
- b &= ~0x8000800080008000ull;
- return (a - b) ^ mask;
-}
-
-uint64_t HELPER(neon_subl_u32)(uint64_t a, uint64_t b)
-{
- uint64_t mask;
- mask = (a ^ ~b) & 0x8000000080000000ull;
- a |= 0x8000000080000000ull;
- b &= ~0x8000000080000000ull;
- return (a - b) ^ mask;
-}
-
uint64_t HELPER(neon_addl_saturate_s32)(CPUARMState *env, uint64_t a, uint64_t b)
{
uint32_t x, y;
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index 19a18018f1..0821f10fad 100644
--- a/target/arm/tcg/translate-neon.c
+++ b/target/arm/tcg/translate-neon.c
@@ -1560,8 +1560,8 @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
NULL, NULL, \
}; \
static NeonGenTwo64OpFn * const addfn[] = { \
- gen_helper_neon_##OP##l_u16, \
- gen_helper_neon_##OP##l_u32, \
+ tcg_gen_vec_##OP##16_i64, \
+ tcg_gen_vec_##OP##32_i64, \
tcg_gen_##OP##_i64, \
NULL, \
}; \
@@ -1639,8 +1639,8 @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
{ \
static NeonGenTwo64OpFn * const addfn[] = { \
- gen_helper_neon_##OP##l_u16, \
- gen_helper_neon_##OP##l_u32, \
+ tcg_gen_vec_##OP##16_i64, \
+ tcg_gen_vec_##OP##32_i64, \
tcg_gen_##OP##_i64, \
NULL, \
}; \
@@ -1761,8 +1761,8 @@ static bool trans_VABAL_S_3d(DisasContext *s, arg_3diff *a)
NULL,
};
static NeonGenTwo64OpFn * const addfn[] = {
- gen_helper_neon_addl_u16,
- gen_helper_neon_addl_u32,
+ tcg_gen_vec_add16_i64,
+ tcg_gen_vec_add32_i64,
tcg_gen_add_i64,
NULL,
};
@@ -1779,8 +1779,8 @@ static bool trans_VABAL_U_3d(DisasContext *s, arg_3diff *a)
NULL,
};
static NeonGenTwo64OpFn * const addfn[] = {
- gen_helper_neon_addl_u16,
- gen_helper_neon_addl_u32,
+ tcg_gen_vec_add16_i64,
+ tcg_gen_vec_add32_i64,
tcg_gen_add_i64,
NULL,
};
@@ -1840,8 +1840,8 @@ static bool trans_VMULL_U_3d(DisasContext *s, arg_3diff *a)
NULL, \
}; \
static NeonGenTwo64OpFn * const accfn[] = { \
- gen_helper_neon_##ACC##l_u16, \
- gen_helper_neon_##ACC##l_u32, \
+ tcg_gen_vec_##ACC##16_i64, \
+ tcg_gen_vec_##ACC##32_i64, \
tcg_gen_##ACC##_i64, \
NULL, \
}; \
@@ -2371,7 +2371,7 @@ static bool trans_VMULL_U_2sc(DisasContext *s, arg_2scalar *a)
}; \
static NeonGenTwo64OpFn * const accfn[] = { \
NULL, \
- gen_helper_neon_##ACC##l_u32, \
+ tcg_gen_vec_##ACC##32_i64, \
tcg_gen_##ACC##_i64, \
NULL, \
}; \
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 46/67] target/arm: Remove helper_neon_{add,sub}l_u{16,32}
2024-12-01 15:05 ` [PATCH 46/67] target/arm: Remove helper_neon_{add,sub}l_u{16,32} Richard Henderson
@ 2024-12-06 15:15 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 15:15 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:15, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> These have generic equivalents: tcg_gen_vec_{add,sub}{16,32}_i64.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 47/67] target/arm: Introduce clear_vec
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (45 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 46/67] target/arm: Remove helper_neon_{add,sub}l_u{16,32} Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-02 16:33 ` Philippe Mathieu-Daudé
2024-12-01 15:05 ` [PATCH 48/67] target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree Richard Henderson
` (20 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
In a couple of places, clearing the entire vector before storing one
element is the easiest solution. Wrap that into a helper function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index c6cc1c9e09..9b2ff20413 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -628,7 +628,16 @@ static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
return v;
}
-/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
+static void clear_vec(DisasContext *s, int rd)
+{
+ unsigned ofs = fp_reg_offset(s, rd, MO_64);
+ unsigned vsz = vec_full_reg_size(s);
+
+ tcg_gen_gvec_dup_imm(MO_64, ofs, vsz, vsz, 0);
+}
+
+/*
+ * Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
* If SVE is not enabled, then there are only 128 bits in the vector.
*/
static void clear_vec_high(DisasContext *s, bool is_q, int rd)
@@ -4851,7 +4860,6 @@ static bool trans_SM3SS1(DisasContext *s, arg_SM3SS1 *a)
TCGv_i32 tcg_op2 = tcg_temp_new_i32();
TCGv_i32 tcg_op3 = tcg_temp_new_i32();
TCGv_i32 tcg_res = tcg_temp_new_i32();
- unsigned vsz, dofs;
read_vec_element_i32(s, tcg_op1, a->rn, 3, MO_32);
read_vec_element_i32(s, tcg_op2, a->rm, 3, MO_32);
@@ -4863,9 +4871,7 @@ static bool trans_SM3SS1(DisasContext *s, arg_SM3SS1 *a)
tcg_gen_rotri_i32(tcg_res, tcg_res, 25);
/* Clear the whole register first, then store bits [127:96]. */
- vsz = vec_full_reg_size(s);
- dofs = vec_full_reg_offset(s, a->rd);
- tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0);
+ clear_vec(s, a->rd);
write_vec_element_i32(s, tcg_res, a->rd, 3, MO_32);
}
return true;
@@ -6307,7 +6313,6 @@ static bool do_scalar_muladd_widening_idx(DisasContext *s, arg_rrx_e *a,
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
- unsigned vsz, dofs;
if (acc) {
read_vec_element(s, t0, a->rd, 0, a->esz + 1);
@@ -6317,9 +6322,7 @@ static bool do_scalar_muladd_widening_idx(DisasContext *s, arg_rrx_e *a,
fn(t0, t1, t2);
/* Clear the whole register first, then store scalar. */
- vsz = vec_full_reg_size(s);
- dofs = vec_full_reg_offset(s, a->rd);
- tcg_gen_gvec_dup_imm(MO_64, dofs, vsz, vsz, 0);
+ clear_vec(s, a->rd);
write_vec_element(s, t0, a->rd, 0, a->esz + 1);
}
return true;
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 48/67] target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (46 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 47/67] target/arm: Introduce clear_vec Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:46 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 49/67] target/arm: Convert FCVTN, BFCVTN " Richard Henderson
` (19 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 153 ++++++++++++++++++++-------------
target/arm/tcg/a64.decode | 9 ++
2 files changed, 102 insertions(+), 60 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 9b2ff20413..6c44e9d8a1 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8925,6 +8925,62 @@ TRANS(CMLE0_s, do_cmop0_d, a, TCG_COND_LE)
TRANS(CMLT0_s, do_cmop0_d, a, TCG_COND_LT)
TRANS(CMEQ0_s, do_cmop0_d, a, TCG_COND_EQ)
+static bool do_2misc_narrow_scalar(DisasContext *s, arg_rr_e *a,
+ ArithOneOp * const fn[3])
+{
+ if (a->esz == MO_64) {
+ return false;
+ }
+ if (fp_access_check(s)) {
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ read_vec_element(s, t, a->rn, 0, a->esz + 1);
+ fn[a->esz](t, t);
+ clear_vec(s, a->rd);
+ write_vec_element(s, t, a->rd, 0, a->esz);
+ }
+ return true;
+}
+
+#define WRAP_ENV(NAME) \
+ static void gen_##NAME(TCGv_i64 d, TCGv_i64 n) \
+ { gen_helper_##NAME(d, tcg_env, n); }
+
+WRAP_ENV(neon_unarrow_sat8)
+WRAP_ENV(neon_unarrow_sat16)
+WRAP_ENV(neon_unarrow_sat32)
+
+static ArithOneOp * const f_scalar_sqxtun[] = {
+ gen_neon_unarrow_sat8,
+ gen_neon_unarrow_sat16,
+ gen_neon_unarrow_sat32,
+};
+TRANS(SQXTUN_s, do_2misc_narrow_scalar, a, f_scalar_sqxtun)
+
+WRAP_ENV(neon_narrow_sat_s8)
+WRAP_ENV(neon_narrow_sat_s16)
+WRAP_ENV(neon_narrow_sat_s32)
+
+static ArithOneOp * const f_scalar_sqxtn[] = {
+ gen_neon_narrow_sat_s8,
+ gen_neon_narrow_sat_s16,
+ gen_neon_narrow_sat_s32,
+};
+TRANS(SQXTN_s, do_2misc_narrow_scalar, a, f_scalar_sqxtn)
+
+WRAP_ENV(neon_narrow_sat_u8)
+WRAP_ENV(neon_narrow_sat_u16)
+WRAP_ENV(neon_narrow_sat_u32)
+
+static ArithOneOp * const f_scalar_uqxtn[] = {
+ gen_neon_narrow_sat_u8,
+ gen_neon_narrow_sat_u16,
+ gen_neon_narrow_sat_u32,
+};
+TRANS(UQXTN_s, do_2misc_narrow_scalar, a, f_scalar_uqxtn)
+
+#undef WRAP_ENV
+
static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
if (!a->q && a->esz == MO_64) {
@@ -8968,6 +9024,37 @@ TRANS(UADDLP_v, do_gvec_fn2_bhs, a, gen_gvec_uaddlp)
TRANS(SADALP_v, do_gvec_fn2_bhs, a, gen_gvec_sadalp)
TRANS(UADALP_v, do_gvec_fn2_bhs, a, gen_gvec_uadalp)
+static bool do_2misc_narrow_vector(DisasContext *s, arg_qrr_e *a,
+ ArithOneOp * const fn[3])
+{
+ if (a->esz == MO_64) {
+ return false;
+ }
+ if (fp_access_check(s)) {
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ read_vec_element(s, t0, a->rn, 0, MO_64);
+ read_vec_element(s, t1, a->rn, 1, MO_64);
+ fn[a->esz](t0, t0);
+ fn[a->esz](t1, t1);
+ write_vec_element(s, t0, a->rd, a->q ? 2 : 0, MO_32);
+ write_vec_element(s, t1, a->rd, a->q ? 3 : 1, MO_32);
+ clear_vec_high(s, a->q, a->rd);
+ }
+ return true;
+}
+
+static ArithOneOp * const f_scalar_xtn[] = {
+ gen_helper_neon_narrow_u8,
+ gen_helper_neon_narrow_u16,
+ tcg_gen_ext32u_i64,
+};
+TRANS(XTN, do_2misc_narrow_vector, a, f_scalar_xtn)
+TRANS(SQXTUN_v, do_2misc_narrow_vector, a, f_scalar_sqxtun)
+TRANS(SQXTN_v, do_2misc_narrow_vector, a, f_scalar_sqxtn)
+TRANS(UQXTN_v, do_2misc_narrow_vector, a, f_scalar_uqxtn)
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9550,38 +9637,6 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
tcg_res[pass] = tcg_temp_new_i64();
switch (opcode) {
- case 0x12: /* XTN, SQXTUN */
- {
- static NeonGenOne64OpFn * const xtnfns[3] = {
- gen_helper_neon_narrow_u8,
- gen_helper_neon_narrow_u16,
- tcg_gen_ext32u_i64,
- };
- static NeonGenOne64OpEnvFn * const sqxtunfns[3] = {
- gen_helper_neon_unarrow_sat8,
- gen_helper_neon_unarrow_sat16,
- gen_helper_neon_unarrow_sat32,
- };
- if (u) {
- genenvfn = sqxtunfns[size];
- } else {
- genfn = xtnfns[size];
- }
- break;
- }
- case 0x14: /* SQXTN, UQXTN */
- {
- static NeonGenOne64OpEnvFn * const fns[3][2] = {
- { gen_helper_neon_narrow_sat_s8,
- gen_helper_neon_narrow_sat_u8 },
- { gen_helper_neon_narrow_sat_s16,
- gen_helper_neon_narrow_sat_u16 },
- { gen_helper_neon_narrow_sat_s32,
- gen_helper_neon_narrow_sat_u32 },
- };
- genenvfn = fns[size][u];
- break;
- }
case 0x16: /* FCVTN, FCVTN2 */
/* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
if (size == 2) {
@@ -9622,6 +9677,8 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
}
break;
default:
+ case 0x12: /* XTN, SQXTUN */
+ case 0x14: /* SQXTN, UQXTN */
g_assert_not_reached();
}
@@ -9657,22 +9714,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
- case 0x12: /* SQXTUN */
- if (!u) {
- unallocated_encoding(s);
- return;
- }
- /* fall through */
- case 0x14: /* SQXTN, UQXTN */
- if (size == 3) {
- unallocated_encoding(s);
- return;
- }
- if (!fp_access_check(s)) {
- return;
- }
- handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd);
- return;
case 0xc ... 0xf:
case 0x16 ... 0x1d:
case 0x1f:
@@ -9746,6 +9787,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x9: /* CMEQ, CMLE */
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
+ case 0x12: /* SQXTUN */
+ case 0x14: /* SQXTN, UQXTN */
unallocated_encoding(s);
return;
}
@@ -9943,18 +9986,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
- case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
- case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
- if (size == 3) {
- unallocated_encoding(s);
- return;
- }
- if (!fp_access_check(s)) {
- return;
- }
-
- handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
- return;
case 0x13: /* SHLL, SHLL2 */
if (u == 0 || size == 3) {
unallocated_encoding(s);
@@ -10146,6 +10177,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x9: /* CMEQ, CMLE */
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
+ case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
+ case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
unallocated_encoding(s);
return;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 77020bb175..9a01037446 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1642,6 +1642,10 @@ CMEQ0_s 0101 1110 111 00000 10011 0 ..... ..... @rr
CMLE0_s 0111 1110 111 00000 10011 0 ..... ..... @rr
CMLT0_s 0101 1110 111 00000 10101 0 ..... ..... @rr
+SQXTUN_s 0111 1110 ..1 00001 00101 0 ..... ..... @rr_e
+SQXTN_s 0101 1110 ..1 00001 01001 0 ..... ..... @rr_e
+UQXTN_s 0111 1110 ..1 00001 01001 0 ..... ..... @rr_e
+
# Advanced SIMD two-register miscellaneous
SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
@@ -1667,3 +1671,8 @@ SADDLP_v 0.00 1110 ..1 00000 00101 0 ..... ..... @qrr_e
UADDLP_v 0.10 1110 ..1 00000 00101 0 ..... ..... @qrr_e
SADALP_v 0.00 1110 ..1 00000 01101 0 ..... ..... @qrr_e
UADALP_v 0.10 1110 ..1 00000 01101 0 ..... ..... @qrr_e
+
+XTN 0.00 1110 ..1 00001 00101 0 ..... ..... @qrr_e
+SQXTUN_v 0.10 1110 ..1 00001 00101 0 ..... ..... @qrr_e
+SQXTN_v 0.00 1110 ..1 00001 01001 0 ..... ..... @qrr_e
+UQXTN_v 0.10 1110 ..1 00001 01001 0 ..... ..... @qrr_e
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 48/67] target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree
2024-12-01 15:05 ` [PATCH 48/67] target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree Richard Henderson
@ 2024-12-06 15:46 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 15:46 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:18, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 153 ++++++++++++++++++++-------------
> target/arm/tcg/a64.decode | 9 ++
> 2 files changed, 102 insertions(+), 60 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 49/67] target/arm: Convert FCVTN, BFCVTN to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (47 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 48/67] target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:48 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 50/67] target/arm: Convert FCVTXN " Richard Henderson
` (18 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 89 ++++++++++++++++++----------------
target/arm/tcg/a64.decode | 5 ++
2 files changed, 52 insertions(+), 42 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 6c44e9d8a1..8b76c307af 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9055,6 +9055,49 @@ TRANS(SQXTUN_v, do_2misc_narrow_vector, a, f_scalar_sqxtun)
TRANS(SQXTN_v, do_2misc_narrow_vector, a, f_scalar_sqxtn)
TRANS(UQXTN_v, do_2misc_narrow_vector, a, f_scalar_uqxtn)
+static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i32 tcg_lo = tcg_temp_new_i32();
+ TCGv_i32 tcg_hi = tcg_temp_new_i32();
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_i32 ahp = get_ahp_flag();
+
+ tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, n);
+ gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp);
+ gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp);
+ tcg_gen_deposit_i32(tcg_lo, tcg_lo, tcg_hi, 16, 16);
+ tcg_gen_extu_i32_i64(d, tcg_lo);
+}
+
+static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ gen_helper_vfp_fcvtsd(tmp, n, tcg_env);
+ tcg_gen_extu_i32_i64(d, tmp);
+}
+
+static ArithOneOp * const f_vector_fcvtn[] = {
+ NULL,
+ gen_fcvtn_hs,
+ gen_fcvtn_sd,
+};
+TRANS(FCVTN_v, do_2misc_narrow_vector, a, f_vector_fcvtn)
+
+static void gen_bfcvtn_hs(TCGv_i64 d, TCGv_i64 n)
+{
+ TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ gen_helper_bfcvt_pair(tmp, n, fpst);
+ tcg_gen_extu_i32_i64(d, tmp);
+}
+
+static ArithOneOp * const f_vector_bfcvtn[] = {
+ NULL,
+ gen_bfcvtn_hs,
+ NULL,
+};
+TRANS_FEAT(BFCVTN_v, aa64_bf16, do_2misc_narrow_vector, a, f_vector_bfcvtn)
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9637,33 +9680,6 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
tcg_res[pass] = tcg_temp_new_i64();
switch (opcode) {
- case 0x16: /* FCVTN, FCVTN2 */
- /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
- if (size == 2) {
- TCGv_i32 tmp = tcg_temp_new_i32();
- gen_helper_vfp_fcvtsd(tmp, tcg_op, tcg_env);
- tcg_gen_extu_i32_i64(tcg_res[pass], tmp);
- } else {
- TCGv_i32 tcg_lo = tcg_temp_new_i32();
- TCGv_i32 tcg_hi = tcg_temp_new_i32();
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
- TCGv_i32 ahp = get_ahp_flag();
-
- tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op);
- gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp);
- gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp);
- tcg_gen_deposit_i32(tcg_lo, tcg_lo, tcg_hi, 16, 16);
- tcg_gen_extu_i32_i64(tcg_res[pass], tcg_lo);
- }
- break;
- case 0x36: /* BFCVTN, BFCVTN2 */
- {
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
- TCGv_i32 tmp = tcg_temp_new_i32();
- gen_helper_bfcvt_pair(tmp, tcg_op, fpst);
- tcg_gen_extu_i32_i64(tcg_res[pass], tmp);
- }
- break;
case 0x56: /* FCVTXN, FCVTXN2 */
{
/*
@@ -9679,6 +9695,8 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
default:
case 0x12: /* XTN, SQXTUN */
case 0x14: /* SQXTN, UQXTN */
+ case 0x16: /* FCVTN, FCVTN2 */
+ case 0x36: /* BFCVTN, BFCVTN2 */
g_assert_not_reached();
}
@@ -10092,21 +10110,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
return;
}
- /* fall through */
- case 0x16: /* FCVTN, FCVTN2 */
- /* handle_2misc_narrow does a 2*size -> size operation, but these
- * instructions encode the source size rather than dest size.
- */
- if (!fp_access_check(s)) {
- return;
- }
- handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd);
- return;
- case 0x36: /* BFCVTN, BFCVTN2 */
- if (!dc_isar_feature(aa64_bf16, s) || size != 2) {
- unallocated_encoding(s);
- return;
- }
if (!fp_access_check(s)) {
return;
}
@@ -10159,6 +10162,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
break;
default:
+ case 0x16: /* FCVTN, FCVTN2 */
+ case 0x36: /* BFCVTN, BFCVTN2 */
unallocated_encoding(s);
return;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 9a01037446..1412b99241 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -21,6 +21,7 @@
%rd 0:5
%esz_sd 22:1 !function=plus_2
+%esz_hs 22:1 !function=plus_1
%esz_hsd 22:2 !function=xor_2
%hl 11:1 21:1
%hlm 11:1 20:2
@@ -74,6 +75,7 @@
@qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0
@qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1
@qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e
+@qrr_hs . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=%esz_hs
@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
@@ -1676,3 +1678,6 @@ XTN 0.00 1110 ..1 00001 00101 0 ..... ..... @qrr_e
SQXTUN_v 0.10 1110 ..1 00001 00101 0 ..... ..... @qrr_e
SQXTN_v 0.00 1110 ..1 00001 01001 0 ..... ..... @qrr_e
UQXTN_v 0.10 1110 ..1 00001 01001 0 ..... ..... @qrr_e
+
+FCVTN_v 0.00 1110 0.1 00001 01101 0 ..... ..... @qrr_hs
+BFCVTN_v 0.00 1110 101 00001 01101 0 ..... ..... @qrr_h
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 50/67] target/arm: Convert FCVTXN to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (48 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 49/67] target/arm: Convert FCVTN, BFCVTN " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:50 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 51/67] target/arm: Convert SHLL " Richard Henderson
` (17 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove handle_2misc_narrow as this was the last insn decoded
by that function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 101 +++++++--------------------------
target/arm/tcg/a64.decode | 4 ++
2 files changed, 24 insertions(+), 81 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 8b76c307af..dd46749ac6 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8979,6 +8979,24 @@ static ArithOneOp * const f_scalar_uqxtn[] = {
};
TRANS(UQXTN_s, do_2misc_narrow_scalar, a, f_scalar_uqxtn)
+static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n)
+{
+ /*
+ * 64 bit to 32 bit float conversion
+ * with von Neumann rounding (round to odd)
+ */
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ gen_helper_fcvtx_f64_to_f32(tmp, n, tcg_env);
+ tcg_gen_extu_i32_i64(d, tmp);
+}
+
+static ArithOneOp * const f_scalar_fcvtxn[] = {
+ NULL,
+ NULL,
+ gen_fcvtxn_sd,
+};
+TRANS(FCVTXN_s, do_2misc_narrow_scalar, a, f_scalar_fcvtxn)
+
#undef WRAP_ENV
static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
@@ -9082,6 +9100,7 @@ static ArithOneOp * const f_vector_fcvtn[] = {
gen_fcvtn_sd,
};
TRANS(FCVTN_v, do_2misc_narrow_vector, a, f_vector_fcvtn)
+TRANS(FCVTXN_v, do_2misc_narrow_vector, a, f_scalar_fcvtxn)
static void gen_bfcvtn_hs(TCGv_i64 d, TCGv_i64 n)
{
@@ -9651,68 +9670,6 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
}
}
-static void handle_2misc_narrow(DisasContext *s, bool scalar,
- int opcode, bool u, bool is_q,
- int size, int rn, int rd)
-{
- /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
- * in the source becomes a size element in the destination).
- */
- int pass;
- TCGv_i64 tcg_res[2];
- int destelt = is_q ? 2 : 0;
- int passes = scalar ? 1 : 2;
-
- if (scalar) {
- tcg_res[1] = tcg_constant_i64(0);
- }
-
- for (pass = 0; pass < passes; pass++) {
- TCGv_i64 tcg_op = tcg_temp_new_i64();
- NeonGenOne64OpFn *genfn = NULL;
- NeonGenOne64OpEnvFn *genenvfn = NULL;
-
- if (scalar) {
- read_vec_element(s, tcg_op, rn, pass, size + 1);
- } else {
- read_vec_element(s, tcg_op, rn, pass, MO_64);
- }
- tcg_res[pass] = tcg_temp_new_i64();
-
- switch (opcode) {
- case 0x56: /* FCVTXN, FCVTXN2 */
- {
- /*
- * 64 bit to 32 bit float conversion
- * with von Neumann rounding (round to odd)
- */
- TCGv_i32 tmp = tcg_temp_new_i32();
- assert(size == 2);
- gen_helper_fcvtx_f64_to_f32(tmp, tcg_op, tcg_env);
- tcg_gen_extu_i32_i64(tcg_res[pass], tmp);
- }
- break;
- default:
- case 0x12: /* XTN, SQXTUN */
- case 0x14: /* SQXTN, UQXTN */
- case 0x16: /* FCVTN, FCVTN2 */
- case 0x36: /* BFCVTN, BFCVTN2 */
- g_assert_not_reached();
- }
-
- if (genfn) {
- genfn(tcg_res[pass], tcg_op);
- } else if (genenvfn) {
- genenvfn(tcg_res[pass], tcg_env, tcg_op);
- }
- }
-
- for (pass = 0; pass < 2; pass++) {
- write_vec_element(s, tcg_res[pass], rd, destelt + pass, MO_32);
- }
- clear_vec_high(s, is_q, rd);
-}
-
/* AdvSIMD scalar two reg misc
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +-----+---+-----------+------+-----------+--------+-----+------+------+
@@ -9784,15 +9741,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
rmode = FPROUNDING_TIEAWAY;
break;
case 0x56: /* FCVTXN, FCVTXN2 */
- if (size == 2) {
- unallocated_encoding(s);
- return;
- }
- if (!fp_access_check(s)) {
- return;
- }
- handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd);
- return;
default:
unallocated_encoding(s);
return;
@@ -10105,16 +10053,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd);
return;
- case 0x56: /* FCVTXN, FCVTXN2 */
- if (size == 2) {
- unallocated_encoding(s);
- return;
- }
- if (!fp_access_check(s)) {
- return;
- }
- handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd);
- return;
case 0x17: /* FCVTL, FCVTL2 */
if (!fp_access_check(s)) {
return;
@@ -10164,6 +10102,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
default:
case 0x16: /* FCVTN, FCVTN2 */
case 0x36: /* BFCVTN, BFCVTN2 */
+ case 0x56: /* FCVTXN, FCVTXN2 */
unallocated_encoding(s);
return;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 1412b99241..bc87dd4a03 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -74,6 +74,7 @@
@qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0
@qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1
+@qrr_s . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=2
@qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e
@qrr_hs . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=%esz_hs
@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
@@ -1648,6 +1649,8 @@ SQXTUN_s 0111 1110 ..1 00001 00101 0 ..... ..... @rr_e
SQXTN_s 0101 1110 ..1 00001 01001 0 ..... ..... @rr_e
UQXTN_s 0111 1110 ..1 00001 01001 0 ..... ..... @rr_e
+FCVTXN_s 0111 1110 011 00001 01101 0 ..... ..... @rr_s
+
# Advanced SIMD two-register miscellaneous
SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
@@ -1680,4 +1683,5 @@ SQXTN_v 0.00 1110 ..1 00001 01001 0 ..... ..... @qrr_e
UQXTN_v 0.10 1110 ..1 00001 01001 0 ..... ..... @qrr_e
FCVTN_v 0.00 1110 0.1 00001 01101 0 ..... ..... @qrr_hs
+FCVTXN_v 0.10 1110 011 00001 01101 0 ..... ..... @qrr_s
BFCVTN_v 0.00 1110 101 00001 01101 0 ..... ..... @qrr_h
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 51/67] target/arm: Convert SHLL to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (49 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 50/67] target/arm: Convert FCVTXN " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 15:52 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 52/67] target/arm: Convert FABS, FNEG (vector) " Richard Henderson
` (16 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 75 +++++++++++++++++-----------------
target/arm/tcg/a64.decode | 2 +
2 files changed, 40 insertions(+), 37 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index dd46749ac6..613dcdb9a2 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9117,6 +9117,43 @@ static ArithOneOp * const f_vector_bfcvtn[] = {
};
TRANS_FEAT(BFCVTN_v, aa64_bf16, do_2misc_narrow_vector, a, f_vector_bfcvtn)
+static bool trans_SHLL_v(DisasContext *s, arg_qrr_e *a)
+{
+ static NeonGenWidenFn * const widenfns[3] = {
+ gen_helper_neon_widen_u8,
+ gen_helper_neon_widen_u16,
+ tcg_gen_extu_i32_i64,
+ };
+ NeonGenWidenFn *widenfn;
+ TCGv_i64 tcg_res[2];
+ TCGv_i32 tcg_op;
+ int part, pass;
+
+ if (a->esz == MO_64) {
+ return false;
+ }
+ if (!fp_access_check(s)) {
+ return true;
+ }
+
+ tcg_op = tcg_temp_new_i32();
+ widenfn = widenfns[a->esz];
+ part = a->q ? 2 : 0;
+
+ for (pass = 0; pass < 2; pass++) {
+ read_vec_element_i32(s, tcg_op, a->rn, part + pass, MO_32);
+ tcg_res[pass] = tcg_temp_new_i64();
+ widenfn(tcg_res[pass], tcg_op);
+ tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << a->esz);
+ }
+
+ for (pass = 0; pass < 2; pass++) {
+ write_vec_element(s, tcg_res[pass], a->rd, pass, MO_64);
+ }
+ return true;
+}
+
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9905,33 +9942,6 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
}
}
-static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
-{
- /* Implement SHLL and SHLL2 */
- int pass;
- int part = is_q ? 2 : 0;
- TCGv_i64 tcg_res[2];
-
- for (pass = 0; pass < 2; pass++) {
- static NeonGenWidenFn * const widenfns[3] = {
- gen_helper_neon_widen_u8,
- gen_helper_neon_widen_u16,
- tcg_gen_extu_i32_i64,
- };
- NeonGenWidenFn *widenfn = widenfns[size];
- TCGv_i32 tcg_op = tcg_temp_new_i32();
-
- read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32);
- tcg_res[pass] = tcg_temp_new_i64();
- widenfn(tcg_res[pass], tcg_op);
- tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size);
- }
-
- for (pass = 0; pass < 2; pass++) {
- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
- }
-}
-
/* AdvSIMD two reg misc
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
@@ -9952,16 +9962,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
- case 0x13: /* SHLL, SHLL2 */
- if (u == 0 || size == 3) {
- unallocated_encoding(s);
- return;
- }
- if (!fp_access_check(s)) {
- return;
- }
- handle_shll(s, is_q, size, rn, rd);
- return;
case 0xc ... 0xf:
case 0x16 ... 0x1f:
{
@@ -10122,6 +10122,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
+ case 0x13: /* SHLL, SHLL2 */
case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
unallocated_encoding(s);
return;
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index bc87dd4a03..8f91b9af1a 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1685,3 +1685,5 @@ UQXTN_v 0.10 1110 ..1 00001 01001 0 ..... ..... @qrr_e
FCVTN_v 0.00 1110 0.1 00001 01101 0 ..... ..... @qrr_hs
FCVTXN_v 0.10 1110 011 00001 01101 0 ..... ..... @qrr_s
BFCVTN_v 0.00 1110 101 00001 01101 0 ..... ..... @qrr_h
+
+SHLL_v 0.10 1110 ..1 00001 00111 0 ..... ..... @qrr_e
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 52/67] target/arm: Convert FABS, FNEG (vector) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (50 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 51/67] target/arm: Convert SHLL " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 16:03 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 53/67] target/arm: Convert FSQRT " Richard Henderson
` (15 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 61 ++++++++++++++++++----------------
target/arm/tcg/a64.decode | 7 ++++
2 files changed, 39 insertions(+), 29 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 613dcdb9a2..31272c1878 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9153,6 +9153,28 @@ static bool trans_SHLL_v(DisasContext *s, arg_qrr_e *a)
return true;
}
+static bool do_fabs_fneg_v(DisasContext *s, arg_qrr_e *a, bool neg)
+{
+ int check = fp_access_check_vector_hsd(s, a->q, a->esz);
+ uint64_t sign;
+
+ if (check <= 0) {
+ return check == 0;
+ }
+
+ sign = 1ull << ((8 << a->esz) - 1);
+ if (neg) {
+ gen_gvec_fn2i(s, a->q, a->rd, a->rn, sign,
+ tcg_gen_gvec_xori, a->esz);
+ } else {
+ gen_gvec_fn2i(s, a->q, a->rd, a->rn, sign - 1,
+ tcg_gen_gvec_andi, a->esz);
+ }
+ return true;
+}
+
+TRANS(FABS_v, do_fabs_fneg_v, a, false)
+TRANS(FNEG_v, do_fabs_fneg_v, a, true)
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
@@ -9451,12 +9473,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
* requires them.
*/
switch (opcode) {
- case 0x2f: /* FABS */
- gen_vfp_absd(tcg_rd, tcg_rn);
- break;
- case 0x6f: /* FNEG */
- gen_vfp_negd(tcg_rd, tcg_rn);
- break;
case 0x7f: /* FSQRT */
gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, tcg_fpstatus);
break;
@@ -9501,6 +9517,8 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
case 0x9: /* CMEQ, CMLE */
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
+ case 0x2f: /* FABS */
+ case 0x6f: /* FNEG */
g_assert_not_reached();
}
}
@@ -9972,13 +9990,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
size = is_double ? 3 : 2;
switch (opcode) {
- case 0x2f: /* FABS */
- case 0x6f: /* FNEG */
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- break;
case 0x1d: /* SCVTF */
case 0x5d: /* UCVTF */
{
@@ -10103,6 +10114,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x16: /* FCVTN, FCVTN2 */
case 0x36: /* BFCVTN, BFCVTN2 */
case 0x56: /* FCVTXN, FCVTXN2 */
+ case 0x2f: /* FABS */
+ case 0x6f: /* FNEG */
unallocated_encoding(s);
return;
}
@@ -10175,12 +10188,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
{
/* Special cases for 32 bit elements */
switch (opcode) {
- case 0x2f: /* FABS */
- gen_vfp_abss(tcg_res, tcg_op);
- break;
- case 0x6f: /* FNEG */
- gen_vfp_negs(tcg_res, tcg_op);
- break;
case 0x7f: /* FSQRT */
gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_fpstatus);
break;
@@ -10224,6 +10231,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
break;
default:
case 0x7: /* SQABS, SQNEG */
+ case 0x2f: /* FABS */
+ case 0x6f: /* FNEG */
g_assert_not_reached();
}
}
@@ -10366,14 +10375,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x7b: /* FCVTZU */
rmode = FPROUNDING_ZERO;
break;
- case 0x2f: /* FABS */
- case 0x6f: /* FNEG */
- need_fpst = false;
- break;
case 0x7d: /* FRSQRTE */
case 0x7f: /* FSQRT (vector) */
break;
default:
+ case 0x2f: /* FABS */
+ case 0x6f: /* FNEG */
unallocated_encoding(s);
return;
}
@@ -10476,12 +10483,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x59: /* FRINTX */
gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
break;
- case 0x2f: /* FABS */
- tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
- break;
- case 0x6f: /* FNEG */
- tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
- break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
@@ -10489,6 +10490,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
gen_helper_vfp_sqrth(tcg_res, tcg_op, tcg_fpstatus);
break;
default:
+ case 0x2f: /* FABS */
+ case 0x6f: /* FNEG */
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 8f91b9af1a..fec6aa7a23 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -77,6 +77,7 @@
@qrr_s . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=2
@qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e
@qrr_hs . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=%esz_hs
+@qrr_sd . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=%esz_sd
@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
@@ -1687,3 +1688,9 @@ FCVTXN_v 0.10 1110 011 00001 01101 0 ..... ..... @qrr_s
BFCVTN_v 0.00 1110 101 00001 01101 0 ..... ..... @qrr_h
SHLL_v 0.10 1110 ..1 00001 00111 0 ..... ..... @qrr_e
+
+FABS_v 0.00 1110 111 11000 11111 0 ..... ..... @qrr_h
+FABS_v 0.00 1110 1.1 00000 11111 0 ..... ..... @qrr_sd
+
+FNEG_v 0.10 1110 111 11000 11111 0 ..... ..... @qrr_h
+FNEG_v 0.10 1110 1.1 00000 11111 0 ..... ..... @qrr_sd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 52/67] target/arm: Convert FABS, FNEG (vector) to decodetree
2024-12-01 15:05 ` [PATCH 52/67] target/arm: Convert FABS, FNEG (vector) " Richard Henderson
@ 2024-12-06 16:03 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 16:03 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:19, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 61 ++++++++++++++++++----------------
> target/arm/tcg/a64.decode | 7 ++++
> 2 files changed, 39 insertions(+), 29 deletions(-)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 613dcdb9a2..31272c1878 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -9153,6 +9153,28 @@ static bool trans_SHLL_v(DisasContext *s, arg_qrr_e *a)
> return true;
> }
>
> +static bool do_fabs_fneg_v(DisasContext *s, arg_qrr_e *a, bool neg)
> +{
> + int check = fp_access_check_vector_hsd(s, a->q, a->esz);
> + uint64_t sign;
> +
> + if (check <= 0) {
> + return check == 0;
> + }
> +
> + sign = 1ull << ((8 << a->esz) - 1);
> + if (neg) {
> + gen_gvec_fn2i(s, a->q, a->rd, a->rn, sign,
> + tcg_gen_gvec_xori, a->esz);
> + } else {
> + gen_gvec_fn2i(s, a->q, a->rd, a->rn, sign - 1,
> + tcg_gen_gvec_andi, a->esz);
> + }
> + return true;
> +}
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Annoying FEAT_AFP wrinkle: for FPCR.AH=1 we will need to make
fabs and fneg not flip the sign bit for NaNs. I guess that means
AH will need to be a tbflags bit so we can generate the nice
vector code for AH=0 and fall back to something else for AH=1.
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 53/67] target/arm: Convert FSQRT (vector) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (51 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 52/67] target/arm: Convert FABS, FNEG (vector) " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 16:11 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 54/67] target/arm: Convert FRINT* " Richard Henderson
` (14 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 67 +++++++++++++++++++++++++---------
target/arm/tcg/a64.decode | 3 ++
2 files changed, 53 insertions(+), 17 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 31272c1878..1e8cb07992 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9176,6 +9176,51 @@ static bool do_fabs_fneg_v(DisasContext *s, arg_qrr_e *a, bool neg)
TRANS(FABS_v, do_fabs_fneg_v, a, false)
TRANS(FNEG_v, do_fabs_fneg_v, a, true)
+static bool do_fp1_vector(DisasContext *s, arg_qrr_e *a,
+ const FPScalar1 *f, int rmode)
+{
+ TCGv_i32 tcg_rmode = NULL;
+ TCGv_ptr fpst;
+ int check = fp_access_check_vector_hsd(s, a->q, a->esz);
+
+ if (check <= 0) {
+ return check == 0;
+ }
+
+ fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ if (rmode >= 0) {
+ tcg_rmode = gen_set_rmode(rmode, fpst);
+ }
+
+ if (a->esz == MO_64) {
+ TCGv_i64 t64 = tcg_temp_new_i64();
+
+ for (int pass = 0; pass < 2; ++pass) {
+ read_vec_element(s, t64, a->rn, pass, MO_64);
+ f->gen_d(t64, t64, fpst);
+ write_vec_element(s, t64, a->rd, pass, MO_64);
+ }
+ } else {
+ TCGv_i32 t32 = tcg_temp_new_i32();
+ void (*gen)(TCGv_i32, TCGv_i32, TCGv_ptr)
+ = (a->esz == MO_16 ? f->gen_h : f->gen_s);
+
+ for (int pass = 0, n = (a->q ? 16 : 8) >> a->esz; pass < n; ++pass) {
+ read_vec_element_i32(s, t32, a->rn, pass, a->esz);
+ gen(t32, t32, fpst);
+ write_vec_element_i32(s, t32, a->rd, pass, a->esz);
+ }
+ }
+ clear_vec_high(s, a->q, a->rd);
+
+ if (rmode >= 0) {
+ gen_restore_rmode(tcg_rmode, fpst);
+ }
+ return true;
+}
+
+TRANS(FSQRT_v, do_fp1_vector, a, &f_scalar_fsqrt, -1)
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9473,9 +9518,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
* requires them.
*/
switch (opcode) {
- case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, tcg_fpstatus);
- break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
@@ -9519,6 +9561,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
case 0xb: /* ABS, NEG */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
+ case 0x7f: /* FSQRT */
g_assert_not_reached();
}
}
@@ -10016,13 +10059,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
return;
- case 0x7f: /* FSQRT */
- need_fpstatus = true;
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x3a: /* FCVTPS */
@@ -10116,6 +10152,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x56: /* FCVTXN, FCVTXN2 */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
+ case 0x7f: /* FSQRT */
unallocated_encoding(s);
return;
}
@@ -10188,9 +10225,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
{
/* Special cases for 32 bit elements */
switch (opcode) {
- case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_fpstatus);
- break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
@@ -10233,6 +10267,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x7: /* SQABS, SQNEG */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
+ case 0x7f: /* FSQRT */
g_assert_not_reached();
}
}
@@ -10376,11 +10411,11 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
rmode = FPROUNDING_ZERO;
break;
case 0x7d: /* FRSQRTE */
- case 0x7f: /* FSQRT (vector) */
break;
default:
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
+ case 0x7f: /* FSQRT (vector) */
unallocated_encoding(s);
return;
}
@@ -10486,12 +10521,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
- case 0x7f: /* FSQRT */
- gen_helper_vfp_sqrth(tcg_res, tcg_op, tcg_fpstatus);
- break;
default:
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
+ case 0x7f: /* FSQRT */
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index fec6aa7a23..f6b334b148 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1694,3 +1694,6 @@ FABS_v 0.00 1110 1.1 00000 11111 0 ..... ..... @qrr_sd
FNEG_v 0.10 1110 111 11000 11111 0 ..... ..... @qrr_h
FNEG_v 0.10 1110 1.1 00000 11111 0 ..... ..... @qrr_sd
+
+FSQRT_v 0.10 1110 111 11001 11111 0 ..... ..... @qrr_h
+FSQRT_v 0.10 1110 1.1 00001 11111 0 ..... ..... @qrr_sd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 54/67] target/arm: Convert FRINT* (vector) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (52 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 53/67] target/arm: Convert FSQRT " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 16:12 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 55/67] target/arm: Convert FCVT* (vector, integer) scalar " Richard Henderson
` (13 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 176 ++++++++++++---------------------
target/arm/tcg/a64.decode | 26 +++++
2 files changed, 88 insertions(+), 114 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 1e8cb07992..98a42feb7d 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9221,6 +9221,21 @@ static bool do_fp1_vector(DisasContext *s, arg_qrr_e *a,
TRANS(FSQRT_v, do_fp1_vector, a, &f_scalar_fsqrt, -1)
+TRANS(FRINTN_v, do_fp1_vector, a, &f_scalar_frint, FPROUNDING_TIEEVEN)
+TRANS(FRINTP_v, do_fp1_vector, a, &f_scalar_frint, FPROUNDING_POSINF)
+TRANS(FRINTM_v, do_fp1_vector, a, &f_scalar_frint, FPROUNDING_NEGINF)
+TRANS(FRINTZ_v, do_fp1_vector, a, &f_scalar_frint, FPROUNDING_ZERO)
+TRANS(FRINTA_v, do_fp1_vector, a, &f_scalar_frint, FPROUNDING_TIEAWAY)
+TRANS(FRINTI_v, do_fp1_vector, a, &f_scalar_frint, -1)
+TRANS(FRINTX_v, do_fp1_vector, a, &f_scalar_frintx, -1)
+
+TRANS_FEAT(FRINT32Z_v, aa64_frint, do_fp1_vector, a,
+ &f_scalar_frint32, FPROUNDING_ZERO)
+TRANS_FEAT(FRINT32X_v, aa64_frint, do_fp1_vector, a, &f_scalar_frint32, -1)
+TRANS_FEAT(FRINT64Z_v, aa64_frint, do_fp1_vector, a,
+ &f_scalar_frint64, FPROUNDING_ZERO)
+TRANS_FEAT(FRINT64X_v, aa64_frint, do_fp1_vector, a, &f_scalar_frint64, -1)
+
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@@ -9532,25 +9547,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
case 0x7b: /* FCVTZU */
gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
break;
- case 0x18: /* FRINTN */
- case 0x19: /* FRINTM */
- case 0x38: /* FRINTP */
- case 0x39: /* FRINTZ */
- case 0x58: /* FRINTA */
- case 0x79: /* FRINTI */
- gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus);
- break;
- case 0x59: /* FRINTX */
- gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus);
- break;
- case 0x1e: /* FRINT32Z */
- case 0x5e: /* FRINT32X */
- gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus);
- break;
- case 0x1f: /* FRINT64Z */
- case 0x5f: /* FRINT64X */
- gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus);
- break;
default:
case 0x4: /* CLS, CLZ */
case 0x5: /* NOT */
@@ -9562,6 +9558,17 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
case 0x7f: /* FSQRT */
+ case 0x18: /* FRINTN */
+ case 0x19: /* FRINTM */
+ case 0x38: /* FRINTP */
+ case 0x39: /* FRINTZ */
+ case 0x58: /* FRINTA */
+ case 0x79: /* FRINTI */
+ case 0x59: /* FRINTX */
+ case 0x1e: /* FRINT32Z */
+ case 0x5e: /* FRINT32X */
+ case 0x1f: /* FRINT64Z */
+ case 0x5f: /* FRINT64X */
g_assert_not_reached();
}
}
@@ -10106,46 +10113,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
handle_2misc_widening(s, opcode, is_q, size, rn, rd);
return;
- case 0x18: /* FRINTN */
- case 0x19: /* FRINTM */
- case 0x38: /* FRINTP */
- case 0x39: /* FRINTZ */
- rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
- /* fall through */
- case 0x59: /* FRINTX */
- case 0x79: /* FRINTI */
- need_fpstatus = true;
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- break;
- case 0x58: /* FRINTA */
- rmode = FPROUNDING_TIEAWAY;
- need_fpstatus = true;
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- break;
case 0x7c: /* URSQRTE */
if (size == 3) {
unallocated_encoding(s);
return;
}
break;
- case 0x1e: /* FRINT32Z */
- case 0x1f: /* FRINT64Z */
- rmode = FPROUNDING_ZERO;
- /* fall through */
- case 0x5e: /* FRINT32X */
- case 0x5f: /* FRINT64X */
- need_fpstatus = true;
- if ((size == 3 && !is_q) || !dc_isar_feature(aa64_frint, s)) {
- unallocated_encoding(s);
- return;
- }
- break;
default:
case 0x16: /* FCVTN, FCVTN2 */
case 0x36: /* BFCVTN, BFCVTN2 */
@@ -10153,6 +10126,17 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
case 0x7f: /* FSQRT */
+ case 0x18: /* FRINTN */
+ case 0x19: /* FRINTM */
+ case 0x38: /* FRINTP */
+ case 0x39: /* FRINTZ */
+ case 0x59: /* FRINTX */
+ case 0x79: /* FRINTI */
+ case 0x58: /* FRINTA */
+ case 0x1e: /* FRINT32Z */
+ case 0x1f: /* FRINT64Z */
+ case 0x5e: /* FRINT32X */
+ case 0x5f: /* FRINT64X */
unallocated_encoding(s);
return;
}
@@ -10241,33 +10225,25 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
gen_helper_vfp_touls(tcg_res, tcg_op,
tcg_constant_i32(0), tcg_fpstatus);
break;
- case 0x18: /* FRINTN */
- case 0x19: /* FRINTM */
- case 0x38: /* FRINTP */
- case 0x39: /* FRINTZ */
- case 0x58: /* FRINTA */
- case 0x79: /* FRINTI */
- gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus);
- break;
- case 0x59: /* FRINTX */
- gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus);
- break;
case 0x7c: /* URSQRTE */
gen_helper_rsqrte_u32(tcg_res, tcg_op);
break;
- case 0x1e: /* FRINT32Z */
- case 0x5e: /* FRINT32X */
- gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus);
- break;
- case 0x1f: /* FRINT64Z */
- case 0x5f: /* FRINT64X */
- gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus);
- break;
default:
case 0x7: /* SQABS, SQNEG */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
case 0x7f: /* FSQRT */
+ case 0x18: /* FRINTN */
+ case 0x19: /* FRINTM */
+ case 0x38: /* FRINTP */
+ case 0x39: /* FRINTZ */
+ case 0x58: /* FRINTA */
+ case 0x79: /* FRINTI */
+ case 0x59: /* FRINTX */
+ case 0x1e: /* FRINT32Z */
+ case 0x5e: /* FRINT32X */
+ case 0x1f: /* FRINT64Z */
+ case 0x5f: /* FRINT64X */
g_assert_not_reached();
}
}
@@ -10301,7 +10277,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
int rn, rd;
bool is_q;
bool is_scalar;
- bool only_in_vector = false;
int pass;
TCGv_i32 tcg_rmode = NULL;
@@ -10355,31 +10330,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x3d: /* FRECPE */
case 0x3f: /* FRECPX */
break;
- case 0x18: /* FRINTN */
- only_in_vector = true;
- rmode = FPROUNDING_TIEEVEN;
- break;
- case 0x19: /* FRINTM */
- only_in_vector = true;
- rmode = FPROUNDING_NEGINF;
- break;
- case 0x38: /* FRINTP */
- only_in_vector = true;
- rmode = FPROUNDING_POSINF;
- break;
- case 0x39: /* FRINTZ */
- only_in_vector = true;
- rmode = FPROUNDING_ZERO;
- break;
- case 0x58: /* FRINTA */
- only_in_vector = true;
- rmode = FPROUNDING_TIEAWAY;
- break;
- case 0x59: /* FRINTX */
- case 0x79: /* FRINTI */
- only_in_vector = true;
- /* current rounding mode */
- break;
case 0x1a: /* FCVTNS */
rmode = FPROUNDING_TIEEVEN;
break;
@@ -10416,6 +10366,13 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
case 0x7f: /* FSQRT (vector) */
+ case 0x18: /* FRINTN */
+ case 0x19: /* FRINTM */
+ case 0x38: /* FRINTP */
+ case 0x39: /* FRINTZ */
+ case 0x58: /* FRINTA */
+ case 0x59: /* FRINTX */
+ case 0x79: /* FRINTI */
unallocated_encoding(s);
return;
}
@@ -10427,11 +10384,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
return;
}
- /* FRINTxx is only in the vector form */
- if (only_in_vector) {
- unallocated_encoding(s);
- return;
- }
}
if (!fp_access_check(s)) {
@@ -10507,17 +10459,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x7b: /* FCVTZU */
gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
break;
- case 0x18: /* FRINTN */
- case 0x19: /* FRINTM */
- case 0x38: /* FRINTP */
- case 0x39: /* FRINTZ */
- case 0x58: /* FRINTA */
- case 0x79: /* FRINTI */
- gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
- break;
- case 0x59: /* FRINTX */
- gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
- break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
@@ -10525,6 +10466,13 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
case 0x7f: /* FSQRT */
+ case 0x18: /* FRINTN */
+ case 0x19: /* FRINTM */
+ case 0x38: /* FRINTP */
+ case 0x39: /* FRINTZ */
+ case 0x58: /* FRINTA */
+ case 0x79: /* FRINTI */
+ case 0x59: /* FRINTX */
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index f6b334b148..4bd72d7f7f 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1697,3 +1697,29 @@ FNEG_v 0.10 1110 1.1 00000 11111 0 ..... ..... @qrr_sd
FSQRT_v 0.10 1110 111 11001 11111 0 ..... ..... @qrr_h
FSQRT_v 0.10 1110 1.1 00001 11111 0 ..... ..... @qrr_sd
+
+FRINTN_v 0.00 1110 011 11001 10001 0 ..... ..... @qrr_h
+FRINTN_v 0.00 1110 0.1 00001 10001 0 ..... ..... @qrr_sd
+
+FRINTM_v 0.00 1110 011 11001 10011 0 ..... ..... @qrr_h
+FRINTM_v 0.00 1110 0.1 00001 10011 0 ..... ..... @qrr_sd
+
+FRINTP_v 0.00 1110 111 11001 10001 0 ..... ..... @qrr_h
+FRINTP_v 0.00 1110 1.1 00001 10001 0 ..... ..... @qrr_sd
+
+FRINTZ_v 0.00 1110 111 11001 10011 0 ..... ..... @qrr_h
+FRINTZ_v 0.00 1110 1.1 00001 10011 0 ..... ..... @qrr_sd
+
+FRINTA_v 0.10 1110 011 11001 10001 0 ..... ..... @qrr_h
+FRINTA_v 0.10 1110 0.1 00001 10001 0 ..... ..... @qrr_sd
+
+FRINTX_v 0.10 1110 011 11001 10011 0 ..... ..... @qrr_h
+FRINTX_v 0.10 1110 0.1 00001 10011 0 ..... ..... @qrr_sd
+
+FRINTI_v 0.10 1110 111 11001 10011 0 ..... ..... @qrr_h
+FRINTI_v 0.10 1110 1.1 00001 10011 0 ..... ..... @qrr_sd
+
+FRINT32Z_v 0.00 1110 0.1 00001 11101 0 ..... ..... @qrr_sd
+FRINT32X_v 0.10 1110 0.1 00001 11101 0 ..... ..... @qrr_sd
+FRINT64Z_v 0.00 1110 0.1 00001 11111 0 ..... ..... @qrr_sd
+FRINT64X_v 0.10 1110 0.1 00001 11111 0 ..... ..... @qrr_sd
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 55/67] target/arm: Convert FCVT* (vector, integer) scalar to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (53 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 54/67] target/arm: Convert FRINT* " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 16:23 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 56/67] target/arm: Convert FCVT* (vector, fixed-point) " Richard Henderson
` (12 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Arm silliness with naming, the scalar insns described
as part of the vector instructions, as separate from
the "regular" scalar insns which output to general registers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 135 ++++++++++++++-------------------
target/arm/tcg/a64.decode | 30 ++++++++
2 files changed, 87 insertions(+), 78 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 98a42feb7d..ad245f2c26 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8678,6 +8678,16 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
tcg_shift, tcg_fpstatus);
tcg_gen_extu_i32_i64(tcg_out, tcg_single);
break;
+ case MO_16 | MO_SIGN:
+ gen_helper_vfp_toshh(tcg_single, tcg_single,
+ tcg_shift, tcg_fpstatus);
+ tcg_gen_extu_i32_i64(tcg_out, tcg_single);
+ break;
+ case MO_16:
+ gen_helper_vfp_touhh(tcg_single, tcg_single,
+ tcg_shift, tcg_fpstatus);
+ tcg_gen_extu_i32_i64(tcg_out, tcg_single);
+ break;
default:
g_assert_not_reached();
}
@@ -8721,6 +8731,42 @@ TRANS(FCVTZU_g, do_fcvt_g, a, FPROUNDING_ZERO, false)
TRANS(FCVTAS_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, true)
TRANS(FCVTAU_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, false)
+/*
+ * FCVT* (vector), scalar version.
+ * Which sounds weird, but really just means output to fp register
+ * instead of output to general register. Input and output element
+ * size are always equal.
+ */
+static bool do_fcvt_f(DisasContext *s, arg_fcvt *a,
+ ARMFPRounding rmode, bool is_signed)
+{
+ TCGv_i64 tcg_int;
+ int check = fp_access_check_scalar_hsd(s, a->esz);
+
+ if (check <= 0) {
+ return check == 0;
+ }
+
+ tcg_int = tcg_temp_new_i64();
+ do_fcvt_scalar(s, a->esz | (is_signed ? MO_SIGN : 0),
+ a->esz, tcg_int, a->shift, a->rn, rmode);
+
+ clear_vec(s, a->rd);
+ write_vec_element(s, tcg_int, a->rd, 0, a->esz);
+ return true;
+}
+
+TRANS(FCVTNS_f, do_fcvt_f, a, FPROUNDING_TIEEVEN, true)
+TRANS(FCVTNU_f, do_fcvt_f, a, FPROUNDING_TIEEVEN, false)
+TRANS(FCVTPS_f, do_fcvt_f, a, FPROUNDING_POSINF, true)
+TRANS(FCVTPU_f, do_fcvt_f, a, FPROUNDING_POSINF, false)
+TRANS(FCVTMS_f, do_fcvt_f, a, FPROUNDING_NEGINF, true)
+TRANS(FCVTMU_f, do_fcvt_f, a, FPROUNDING_NEGINF, false)
+TRANS(FCVTZS_f, do_fcvt_f, a, FPROUNDING_ZERO, true)
+TRANS(FCVTZU_f, do_fcvt_f, a, FPROUNDING_ZERO, false)
+TRANS(FCVTAS_f, do_fcvt_f, a, FPROUNDING_TIEAWAY, true)
+TRANS(FCVTAU_f, do_fcvt_f, a, FPROUNDING_TIEAWAY, false)
+
static bool trans_FJCVTZS(DisasContext *s, arg_FJCVTZS *a)
{
if (!dc_isar_feature(aa64_jscvt, s)) {
@@ -9788,10 +9834,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
int opcode = extract32(insn, 12, 5);
int size = extract32(insn, 22, 2);
bool u = extract32(insn, 29, 1);
- bool is_fcvt = false;
- int rmode;
- TCGv_i32 tcg_rmode;
- TCGv_ptr tcg_fpstatus;
switch (opcode) {
case 0xc ... 0xf:
@@ -9836,15 +9878,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x5b: /* FCVTMU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
- is_fcvt = true;
- rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
- break;
case 0x1c: /* FCVTAS */
case 0x5c: /* FCVTAU */
- /* TIEAWAY doesn't fit in the usual rounding mode encoding */
- is_fcvt = true;
- rmode = FPROUNDING_TIEAWAY;
- break;
case 0x56: /* FCVTXN, FCVTXN2 */
default:
unallocated_encoding(s);
@@ -9863,59 +9898,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
return;
}
-
- if (!fp_access_check(s)) {
- return;
- }
-
- if (is_fcvt) {
- tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
- } else {
- tcg_fpstatus = NULL;
- tcg_rmode = NULL;
- }
-
- if (size == 3) {
- TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
- TCGv_i64 tcg_rd = tcg_temp_new_i64();
-
- handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus);
- write_fp_dreg(s, rd, tcg_rd);
- } else {
- TCGv_i32 tcg_rn = tcg_temp_new_i32();
- TCGv_i32 tcg_rd = tcg_temp_new_i32();
-
- read_vec_element_i32(s, tcg_rn, rn, 0, size);
-
- switch (opcode) {
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0),
- tcg_fpstatus);
- break;
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x5c: /* FCVTAU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0),
- tcg_fpstatus);
- break;
- default:
- case 0x7: /* SQABS, SQNEG */
- g_assert_not_reached();
- }
-
- write_fp_sreg(s, rd, tcg_rd);
- }
-
- if (is_fcvt) {
- gen_restore_rmode(tcg_rmode, tcg_fpstatus);
- }
+ g_assert_not_reached();
}
/* AdvSIMD shift by immediate
@@ -10403,31 +10386,27 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
TCGv_i32 tcg_res = tcg_temp_new_i32();
switch (fpop) {
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
- break;
case 0x3d: /* FRECPE */
gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x3f: /* FRECPX */
gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x5c: /* FCVTAU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
- break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
default:
case 0x6f: /* FNEG */
+ case 0x1a: /* FCVTNS */
+ case 0x1b: /* FCVTMS */
+ case 0x1c: /* FCVTAS */
+ case 0x3a: /* FCVTPS */
+ case 0x3b: /* FCVTZS */
+ case 0x5a: /* FCVTNU */
+ case 0x5b: /* FCVTMU */
+ case 0x5c: /* FCVTAU */
+ case 0x7a: /* FCVTPU */
+ case 0x7b: /* FCVTZU */
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 4bd72d7f7f..617bbc6380 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1652,6 +1652,36 @@ UQXTN_s 0111 1110 ..1 00001 01001 0 ..... ..... @rr_e
FCVTXN_s 0111 1110 011 00001 01101 0 ..... ..... @rr_s
+@icvt_h . ....... .. ...... ...... rn:5 rd:5 \
+ &fcvt sf=0 esz=1 shift=0
+@icvt_sd . ....... .. ...... ...... rn:5 rd:5 \
+ &fcvt sf=0 esz=%esz_sd shift=0
+
+FCVTNS_f 0101 1110 011 11001 10101 0 ..... ..... @icvt_h
+FCVTNS_f 0101 1110 0.1 00001 10101 0 ..... ..... @icvt_sd
+FCVTNU_f 0111 1110 011 11001 10101 0 ..... ..... @icvt_h
+FCVTNU_f 0111 1110 0.1 00001 10101 0 ..... ..... @icvt_sd
+
+FCVTPS_f 0101 1110 111 11001 10101 0 ..... ..... @icvt_h
+FCVTPS_f 0101 1110 1.1 00001 10101 0 ..... ..... @icvt_sd
+FCVTPU_f 0111 1110 111 11001 10101 0 ..... ..... @icvt_h
+FCVTPU_f 0111 1110 1.1 00001 10101 0 ..... ..... @icvt_sd
+
+FCVTMS_f 0101 1110 011 11001 10111 0 ..... ..... @icvt_h
+FCVTMS_f 0101 1110 0.1 00001 10111 0 ..... ..... @icvt_sd
+FCVTMU_f 0111 1110 011 11001 10111 0 ..... ..... @icvt_h
+FCVTMU_f 0111 1110 0.1 00001 10111 0 ..... ..... @icvt_sd
+
+FCVTZS_f 0101 1110 111 11001 10111 0 ..... ..... @icvt_h
+FCVTZS_f 0101 1110 1.1 00001 10111 0 ..... ..... @icvt_sd
+FCVTZU_f 0111 1110 111 11001 10111 0 ..... ..... @icvt_h
+FCVTZU_f 0111 1110 1.1 00001 10111 0 ..... ..... @icvt_sd
+
+FCVTAS_f 0101 1110 011 11001 11001 0 ..... ..... @icvt_h
+FCVTAS_f 0101 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
+FCVTAU_f 0111 1110 011 11001 11001 0 ..... ..... @icvt_h
+FCVTAU_f 0111 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
+
# Advanced SIMD two-register miscellaneous
SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 55/67] target/arm: Convert FCVT* (vector, integer) scalar to decodetree
2024-12-01 15:05 ` [PATCH 55/67] target/arm: Convert FCVT* (vector, integer) scalar " Richard Henderson
@ 2024-12-06 16:23 ` Peter Maydell
2024-12-06 18:12 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 16:23 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:21, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Arm silliness with naming, the scalar insns described
> as part of the vector instructions, as separate from
> the "regular" scalar insns which output to general registers.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 135 ++++++++++++++-------------------
> target/arm/tcg/a64.decode | 30 ++++++++
> 2 files changed, 87 insertions(+), 78 deletions(-)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 98a42feb7d..ad245f2c26 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -8678,6 +8678,16 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
> tcg_shift, tcg_fpstatus);
> tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> break;
> + case MO_16 | MO_SIGN:
> + gen_helper_vfp_toshh(tcg_single, tcg_single,
> + tcg_shift, tcg_fpstatus);
> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> + break;
> + case MO_16:
> + gen_helper_vfp_touhh(tcg_single, tcg_single,
> + tcg_shift, tcg_fpstatus);
> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
> + break;
This hunk adds calls to the toshh and touhh helpers,
but as far as I can see it doesn't remove any calls to
those helpers that were in the old decode functions or
any calls to the handle_simd_shift_fpint_conv() function
which was the only one that did call them. Should this
be in a different patch?
(Conversely, we remove calls to gen_helper_advsimd_f16tosinth
and gen_helper_advsimd_f16touinth but don't have those here.)
thnaks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* Re: [PATCH 55/67] target/arm: Convert FCVT* (vector, integer) scalar to decodetree
2024-12-06 16:23 ` Peter Maydell
@ 2024-12-06 18:12 ` Richard Henderson
0 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-06 18:12 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 12/6/24 10:23, Peter Maydell wrote:
> On Sun, 1 Dec 2024 at 15:21, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Arm silliness with naming, the scalar insns described
>> as part of the vector instructions, as separate from
>> the "regular" scalar insns which output to general registers.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/tcg/translate-a64.c | 135 ++++++++++++++-------------------
>> target/arm/tcg/a64.decode | 30 ++++++++
>> 2 files changed, 87 insertions(+), 78 deletions(-)
>>
>> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
>> index 98a42feb7d..ad245f2c26 100644
>> --- a/target/arm/tcg/translate-a64.c
>> +++ b/target/arm/tcg/translate-a64.c
>> @@ -8678,6 +8678,16 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
>> tcg_shift, tcg_fpstatus);
>> tcg_gen_extu_i32_i64(tcg_out, tcg_single);
>> break;
>> + case MO_16 | MO_SIGN:
>> + gen_helper_vfp_toshh(tcg_single, tcg_single,
>> + tcg_shift, tcg_fpstatus);
>> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
>> + break;
>> + case MO_16:
>> + gen_helper_vfp_touhh(tcg_single, tcg_single,
>> + tcg_shift, tcg_fpstatus);
>> + tcg_gen_extu_i32_i64(tcg_out, tcg_single);
>> + break;
>
> This hunk adds calls to the toshh and touhh helpers,
> but as far as I can see it doesn't remove any calls to
> those helpers that were in the old decode functions or
> any calls to the handle_simd_shift_fpint_conv() function
> which was the only one that did call them. Should this
> be in a different patch?
Removing those happens in patch 61, with FCVTZ* (vector, fixed-point).
Here we're only converting the scalar path.
> (Conversely, we remove calls to gen_helper_advsimd_f16tosinth
> and gen_helper_advsimd_f16touinth but don't have those here.)
With the conversion I'm sharing more code. So we (eventially) remove advsimd_f16to*inth
entirely and use only vfp_to*hh. They both call the same float16_to_*int16_scalbn
function in the end.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 56/67] target/arm: Convert FCVT* (vector, fixed-point) scalar to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (54 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 55/67] target/arm: Convert FCVT* (vector, integer) scalar " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-01 15:05 ` [PATCH 57/67] target/arm: Convert [US]CVTF (vector, integer) " Richard Henderson
` (11 subsequent siblings)
67 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 4 +---
target/arm/tcg/a64.decode | 19 +++++++++++++++++++
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index ad245f2c26..bdeb0288fd 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9547,9 +9547,6 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
opcode, rn, rd);
break;
- case 0x1f: /* FCVTZS, FCVTZU */
- handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd);
- break;
default:
case 0x00: /* SSHR / USHR */
case 0x02: /* SSRA / USRA */
@@ -9563,6 +9560,7 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
case 0x11: /* SQRSHRUN */
case 0x12: /* SQSHRN, UQSHRN */
case 0x13: /* SQRSHRN, UQRSHRN */
+ case 0x1f: /* FCVTZS, FCVTZU */
unallocated_encoding(s);
break;
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 617bbc6380..4cb5b20826 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1682,6 +1682,25 @@ FCVTAS_f 0101 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
FCVTAU_f 0111 1110 011 11001 11001 0 ..... ..... @icvt_h
FCVTAU_f 0111 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
+%fcvt_f_sh_h 16:4 !function=rsub_16
+%fcvt_f_sh_s 16:5 !function=rsub_32
+%fcvt_f_sh_d 16:6 !function=rsub_64
+
+@fcvt_fixed_h .... .... . 001 .... ...... rn:5 rd:5 \
+ &fcvt sf=0 esz=1 shift=%fcvt_f_sh_h
+@fcvt_fixed_s .... .... . 01 ..... ...... rn:5 rd:5 \
+ &fcvt sf=0 esz=2 shift=%fcvt_f_sh_s
+@fcvt_fixed_d .... .... . 1 ...... ...... rn:5 rd:5 \
+ &fcvt sf=0 esz=3 shift=%fcvt_f_sh_d
+
+FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_h
+FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_s
+FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_d
+
+FCVTZU_f 0111 1111 0 ....... 111111 ..... ..... @fcvt_fixed_h
+FCVTZU_f 0111 1111 0 ....... 111111 ..... ..... @fcvt_fixed_s
+FCVTZU_f 0111 1111 0 ....... 111111 ..... ..... @fcvt_fixed_d
+
# Advanced SIMD two-register miscellaneous
SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 57/67] target/arm: Convert [US]CVTF (vector, integer) scalar to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (55 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 56/67] target/arm: Convert FCVT* (vector, fixed-point) " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 16:24 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 58/67] target/arm: Convert [US]CVTF (vector, fixed-point) " Richard Henderson
` (10 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 35 ++++++++++++++++++++++++----------
target/arm/tcg/a64.decode | 6 ++++++
2 files changed, 31 insertions(+), 10 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index bdeb0288fd..9808b976fd 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8603,6 +8603,29 @@ static bool do_cvtf_g(DisasContext *s, arg_fcvt *a, bool is_signed)
TRANS(SCVTF_g, do_cvtf_g, a, true)
TRANS(UCVTF_g, do_cvtf_g, a, false)
+/*
+ * [US]CVTF (vector), scalar version.
+ * Which sounds weird, but really just means input from fp register
+ * instead of input from general register. Input and output element
+ * size are always equal.
+ */
+static bool do_cvtf_f(DisasContext *s, arg_fcvt *a, bool is_signed)
+{
+ TCGv_i64 tcg_int;
+ int check = fp_access_check_scalar_hsd(s, a->esz);
+
+ if (check <= 0) {
+ return check == 0;
+ }
+
+ tcg_int = tcg_temp_new_i64();
+ read_vec_element(s, tcg_int, a->rn, 0, a->esz | (is_signed ? MO_SIGN : 0));
+ return do_cvtf_scalar(s, a->esz, a->rd, a->shift, tcg_int, is_signed);
+}
+
+TRANS(SCVTF_f, do_cvtf_f, a, true)
+TRANS(UCVTF_f, do_cvtf_f, a, false)
+
static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
TCGv_i64 tcg_out, int shift, int rn,
ARMFPRounding rmode)
@@ -9850,16 +9873,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x6d: /* FCMLE (zero) */
handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd);
return;
- case 0x1d: /* SCVTF */
- case 0x5d: /* UCVTF */
- {
- bool is_signed = (opcode == 0x1d);
- if (!fp_access_check(s)) {
- return;
- }
- handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size);
- return;
- }
case 0x3d: /* FRECPE */
case 0x3f: /* FRECPX */
case 0x7d: /* FRSQRTE */
@@ -9879,6 +9892,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x1c: /* FCVTAS */
case 0x5c: /* FCVTAU */
case 0x56: /* FCVTXN, FCVTXN2 */
+ case 0x1d: /* SCVTF */
+ case 0x5d: /* UCVTF */
default:
unallocated_encoding(s);
return;
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 4cb5b20826..707715f433 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1657,6 +1657,12 @@ FCVTXN_s 0111 1110 011 00001 01101 0 ..... ..... @rr_s
@icvt_sd . ....... .. ...... ...... rn:5 rd:5 \
&fcvt sf=0 esz=%esz_sd shift=0
+SCVTF_f 0101 1110 011 11001 11011 0 ..... ..... @icvt_h
+SCVTF_f 0101 1110 0.1 00001 11011 0 ..... ..... @icvt_sd
+
+UCVTF_f 0111 1110 011 11001 11011 0 ..... ..... @icvt_h
+UCVTF_f 0111 1110 0.1 00001 11011 0 ..... ..... @icvt_sd
+
FCVTNS_f 0101 1110 011 11001 10101 0 ..... ..... @icvt_h
FCVTNS_f 0101 1110 0.1 00001 10101 0 ..... ..... @icvt_sd
FCVTNU_f 0111 1110 011 11001 10101 0 ..... ..... @icvt_h
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 58/67] target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (56 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 57/67] target/arm: Convert [US]CVTF (vector, integer) " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 16:27 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 59/67] target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz Richard Henderson
` (9 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove disas_simd_scalar_shift_imm as these were the
last insns decoded by that function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 47 ----------------------------------
target/arm/tcg/a64.decode | 8 ++++++
2 files changed, 8 insertions(+), 47 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 9808b976fd..ea178f85c2 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9543,52 +9543,6 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
-/* AdvSIMD scalar shift by immediate
- * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
- * +-----+---+-------------+------+------+--------+---+------+------+
- * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
- * +-----+---+-------------+------+------+--------+---+------+------+
- *
- * This is the scalar version so it works on a fixed sized registers
- */
-static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
-{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int opcode = extract32(insn, 11, 5);
- int immb = extract32(insn, 16, 3);
- int immh = extract32(insn, 19, 4);
- bool is_u = extract32(insn, 29, 1);
-
- if (immh == 0) {
- unallocated_encoding(s);
- return;
- }
-
- switch (opcode) {
- case 0x1c: /* SCVTF, UCVTF */
- handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
- opcode, rn, rd);
- break;
- default:
- case 0x00: /* SSHR / USHR */
- case 0x02: /* SSRA / USRA */
- case 0x04: /* SRSHR / URSHR */
- case 0x06: /* SRSRA / URSRA */
- case 0x08: /* SRI */
- case 0x0a: /* SHL / SLI */
- case 0x0c: /* SQSHLU */
- case 0x0e: /* SQSHL, UQSHL */
- case 0x10: /* SQSHRUN */
- case 0x11: /* SQRSHRUN */
- case 0x12: /* SQSHRN, UQSHRN */
- case 0x13: /* SQRSHRN, UQRSHRN */
- case 0x1f: /* FCVTZS, FCVTZU */
- unallocated_encoding(s);
- break;
- }
-}
-
static void handle_2misc_64(DisasContext *s, int opcode, bool u,
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
@@ -10489,7 +10443,6 @@ static const AArch64DecodeTable data_proc_simd[] = {
{ 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
{ 0x0f000400, 0x9f800400, disas_simd_shift_imm },
{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
- { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
{ 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
{ 0x00000000, 0x00000000, NULL }
};
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 707715f433..197555555e 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1699,6 +1699,14 @@ FCVTAU_f 0111 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
@fcvt_fixed_d .... .... . 1 ...... ...... rn:5 rd:5 \
&fcvt sf=0 esz=3 shift=%fcvt_f_sh_d
+SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_h
+SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_s
+SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_d
+
+UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_h
+UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_s
+UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_d
+
FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_h
FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_s
FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_d
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 58/67] target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree
2024-12-01 15:05 ` [PATCH 58/67] target/arm: Convert [US]CVTF (vector, fixed-point) " Richard Henderson
@ 2024-12-06 16:27 ` Peter Maydell
2024-12-06 18:15 ` Richard Henderson
0 siblings, 1 reply; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 16:27 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:12, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Remove disas_simd_scalar_shift_imm as these were the
> last insns decoded by that function.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate-a64.c | 47 ----------------------------------
> target/arm/tcg/a64.decode | 8 ++++++
> 2 files changed, 8 insertions(+), 47 deletions(-)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index 9808b976fd..ea178f85c2 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -9543,52 +9543,6 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
> gen_restore_rmode(tcg_rmode, tcg_fpstatus);
> }
>
> -/* AdvSIMD scalar shift by immediate
> - * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
> - * +-----+---+-------------+------+------+--------+---+------+------+
> - * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
> - * +-----+---+-------------+------+------+--------+---+------+------+
> - *
> - * This is the scalar version so it works on a fixed sized registers
> - */
> -static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
> -{
> - int rd = extract32(insn, 0, 5);
> - int rn = extract32(insn, 5, 5);
> - int opcode = extract32(insn, 11, 5);
> - int immb = extract32(insn, 16, 3);
> - int immh = extract32(insn, 19, 4);
> - bool is_u = extract32(insn, 29, 1);
> -
> - if (immh == 0) {
> - unallocated_encoding(s);
> - return;
> - }
> -
> - switch (opcode) {
> - case 0x1c: /* SCVTF, UCVTF */
> - handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
> - opcode, rn, rd);
> - break;
> - default:
> - case 0x00: /* SSHR / USHR */
> - case 0x02: /* SSRA / USRA */
> - case 0x04: /* SRSHR / URSHR */
> - case 0x06: /* SRSRA / URSRA */
> - case 0x08: /* SRI */
> - case 0x0a: /* SHL / SLI */
> - case 0x0c: /* SQSHLU */
> - case 0x0e: /* SQSHL, UQSHL */
> - case 0x10: /* SQSHRUN */
> - case 0x11: /* SQRSHRUN */
> - case 0x12: /* SQSHRN, UQSHRN */
> - case 0x13: /* SQRSHRN, UQRSHRN */
> - case 0x1f: /* FCVTZS, FCVTZU */
> - unallocated_encoding(s);
> - break;
> - }
> -}
> -
> static void handle_2misc_64(DisasContext *s, int opcode, bool u,
> TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
> TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
> @@ -10489,7 +10443,6 @@ static const AArch64DecodeTable data_proc_simd[] = {
> { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
> { 0x0f000400, 0x9f800400, disas_simd_shift_imm },
> { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
> - { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
> { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
> { 0x00000000, 0x00000000, NULL }
> };
> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
> index 707715f433..197555555e 100644
> --- a/target/arm/tcg/a64.decode
> +++ b/target/arm/tcg/a64.decode
> @@ -1699,6 +1699,14 @@ FCVTAU_f 0111 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
> @fcvt_fixed_d .... .... . 1 ...... ...... rn:5 rd:5 \
> &fcvt sf=0 esz=3 shift=%fcvt_f_sh_d
>
> +SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_h
> +SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_s
> +SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_d
> +
> +UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_h
> +UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_s
> +UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_d
> +
> FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_h
> FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_s
> FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_d
Aren't we missing the new trans functions for these insns ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread* Re: [PATCH 58/67] target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree
2024-12-06 16:27 ` Peter Maydell
@ 2024-12-06 18:15 ` Richard Henderson
0 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-06 18:15 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, qemu-arm
On 12/6/24 10:27, Peter Maydell wrote:
> On Sun, 1 Dec 2024 at 15:12, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Remove disas_simd_scalar_shift_imm as these were the
>> last insns decoded by that function.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/arm/tcg/translate-a64.c | 47 ----------------------------------
>> target/arm/tcg/a64.decode | 8 ++++++
>> 2 files changed, 8 insertions(+), 47 deletions(-)
>>
>> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
>> index 9808b976fd..ea178f85c2 100644
>> --- a/target/arm/tcg/translate-a64.c
>> +++ b/target/arm/tcg/translate-a64.c
>> @@ -9543,52 +9543,6 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
>> gen_restore_rmode(tcg_rmode, tcg_fpstatus);
>> }
>>
>> -/* AdvSIMD scalar shift by immediate
>> - * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
>> - * +-----+---+-------------+------+------+--------+---+------+------+
>> - * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
>> - * +-----+---+-------------+------+------+--------+---+------+------+
>> - *
>> - * This is the scalar version so it works on a fixed sized registers
>> - */
>> -static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
>> -{
>> - int rd = extract32(insn, 0, 5);
>> - int rn = extract32(insn, 5, 5);
>> - int opcode = extract32(insn, 11, 5);
>> - int immb = extract32(insn, 16, 3);
>> - int immh = extract32(insn, 19, 4);
>> - bool is_u = extract32(insn, 29, 1);
>> -
>> - if (immh == 0) {
>> - unallocated_encoding(s);
>> - return;
>> - }
>> -
>> - switch (opcode) {
>> - case 0x1c: /* SCVTF, UCVTF */
>> - handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
>> - opcode, rn, rd);
>> - break;
>> - default:
>> - case 0x00: /* SSHR / USHR */
>> - case 0x02: /* SSRA / USRA */
>> - case 0x04: /* SRSHR / URSHR */
>> - case 0x06: /* SRSRA / URSRA */
>> - case 0x08: /* SRI */
>> - case 0x0a: /* SHL / SLI */
>> - case 0x0c: /* SQSHLU */
>> - case 0x0e: /* SQSHL, UQSHL */
>> - case 0x10: /* SQSHRUN */
>> - case 0x11: /* SQRSHRUN */
>> - case 0x12: /* SQSHRN, UQSHRN */
>> - case 0x13: /* SQRSHRN, UQRSHRN */
>> - case 0x1f: /* FCVTZS, FCVTZU */
>> - unallocated_encoding(s);
>> - break;
>> - }
>> -}
>> -
>> static void handle_2misc_64(DisasContext *s, int opcode, bool u,
>> TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
>> TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
>> @@ -10489,7 +10443,6 @@ static const AArch64DecodeTable data_proc_simd[] = {
>> { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
>> { 0x0f000400, 0x9f800400, disas_simd_shift_imm },
>> { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
>> - { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
>> { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
>> { 0x00000000, 0x00000000, NULL }
>> };
>> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
>> index 707715f433..197555555e 100644
>> --- a/target/arm/tcg/a64.decode
>> +++ b/target/arm/tcg/a64.decode
>> @@ -1699,6 +1699,14 @@ FCVTAU_f 0111 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
>> @fcvt_fixed_d .... .... . 1 ...... ...... rn:5 rd:5 \
>> &fcvt sf=0 esz=3 shift=%fcvt_f_sh_d
>>
>> +SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_h
>> +SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_s
>> +SCVTF_f 0101 1111 0 ....... 111001 ..... ..... @fcvt_fixed_d
>> +
>> +UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_h
>> +UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_s
>> +UCVTF_f 0111 1111 0 ....... 111001 ..... ..... @fcvt_fixed_d
>> +
>> FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_h
>> FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_s
>> FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_d
>
> Aren't we missing the new trans functions for these insns ?
No, we're sharing the trans functions with the previous patch.
The (vector, integer) insns decode with shift=0.
These (vector, fixed-point) insns decode a proper shift field.
r~
^ permalink raw reply [flat|nested] 147+ messages in thread
* [PATCH 59/67] target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (57 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 58/67] target/arm: Convert [US]CVTF (vector, fixed-point) " Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-06 16:28 ` Peter Maydell
2024-12-01 15:05 ` [PATCH 60/67] target/arm: Convert [US]CVTF (vector) to decodetree Richard Henderson
` (8 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Emphasize that these functions use round-to-zero mode.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 8 ++++----
target/arm/tcg/translate-neon.c | 8 ++++----
target/arm/tcg/vec_helper.c | 8 ++++----
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 04e422ab08..f2cfee40de 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -650,13 +650,13 @@ DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_4(gvec_vcvt_fs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_4(gvec_vcvt_fu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_4(gvec_vcvt_hs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_4(gvec_vcvt_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index 0821f10fad..cea400e1f5 100644
--- a/target/arm/tcg/translate-neon.c
+++ b/target/arm/tcg/translate-neon.c
@@ -1409,13 +1409,13 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
DO_FP_2SH(VCVT_SF, gen_helper_gvec_vcvt_sf)
DO_FP_2SH(VCVT_UF, gen_helper_gvec_vcvt_uf)
-DO_FP_2SH(VCVT_FS, gen_helper_gvec_vcvt_fs)
-DO_FP_2SH(VCVT_FU, gen_helper_gvec_vcvt_fu)
+DO_FP_2SH(VCVT_FS, gen_helper_gvec_vcvt_rz_fs)
+DO_FP_2SH(VCVT_FU, gen_helper_gvec_vcvt_rz_fu)
DO_FP_2SH(VCVT_SH, gen_helper_gvec_vcvt_sh)
DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
-DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
-DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
+DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_rz_hs)
+DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_rz_hu)
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
GVecGen2iFn *fn)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 60381258cf..282dba4bfd 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2507,12 +2507,12 @@ DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4)
DO_VCVT_FIXED(gvec_vcvt_sf, helper_vfp_sltos, uint32_t)
DO_VCVT_FIXED(gvec_vcvt_uf, helper_vfp_ultos, uint32_t)
-DO_VCVT_FIXED(gvec_vcvt_fs, helper_vfp_tosls_round_to_zero, uint32_t)
-DO_VCVT_FIXED(gvec_vcvt_fu, helper_vfp_touls_round_to_zero, uint32_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_fs, helper_vfp_tosls_round_to_zero, uint32_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_fu, helper_vfp_touls_round_to_zero, uint32_t)
DO_VCVT_FIXED(gvec_vcvt_sh, helper_vfp_shtoh, uint16_t)
DO_VCVT_FIXED(gvec_vcvt_uh, helper_vfp_uhtoh, uint16_t)
-DO_VCVT_FIXED(gvec_vcvt_hs, helper_vfp_toshh_round_to_zero, uint16_t)
-DO_VCVT_FIXED(gvec_vcvt_hu, helper_vfp_touhh_round_to_zero, uint16_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_hs, helper_vfp_toshh_round_to_zero, uint16_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_hu, helper_vfp_touhh_round_to_zero, uint16_t)
#undef DO_VCVT_FIXED
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 60/67] target/arm: Convert [US]CVTF (vector) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (58 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 59/67] target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz Richard Henderson
@ 2024-12-01 15:05 ` Richard Henderson
2024-12-01 15:06 ` [PATCH 61/67] target/arm: Convert FCVTZ[SU] (vector, fixed-point) " Richard Henderson
` (7 subsequent siblings)
67 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:05 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove handle_simd_intfp_conv and handle_simd_shift_intfp_conv
as these were the last insns decoded by those functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 3 +
target/arm/tcg/translate-a64.c | 201 ++++++---------------------------
target/arm/tcg/vec_helper.c | 7 +-
target/arm/tcg/a64.decode | 22 ++++
4 files changed, 66 insertions(+), 167 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index f2cfee40de..b227ac54d9 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -658,6 +658,9 @@ DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index ea178f85c2..26ae38b99e 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9305,141 +9305,44 @@ TRANS_FEAT(FRINT64Z_v, aa64_frint, do_fp1_vector, a,
&f_scalar_frint64, FPROUNDING_ZERO)
TRANS_FEAT(FRINT64X_v, aa64_frint, do_fp1_vector, a, &f_scalar_frint64, -1)
-/* Common vector code for handling integer to FP conversion */
-static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
- int elements, int is_signed,
- int fracbits, int size)
+static bool do_gvec_op2_fpst(DisasContext *s, MemOp esz, bool is_q,
+ int rd, int rn, int data,
+ gen_helper_gvec_2_ptr * const fns[3])
{
- TCGv_ptr tcg_fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
- TCGv_i32 tcg_shift = NULL;
+ int check = fp_access_check_vector_hsd(s, is_q, esz);
+ TCGv_ptr fpst;
- MemOp mop = size | (is_signed ? MO_SIGN : 0);
- int pass;
-
- if (fracbits || size == MO_64) {
- tcg_shift = tcg_constant_i32(fracbits);
+ if (check <= 0) {
+ return check == 0;
}
- if (size == MO_64) {
- TCGv_i64 tcg_int64 = tcg_temp_new_i64();
- TCGv_i64 tcg_double = tcg_temp_new_i64();
-
- for (pass = 0; pass < elements; pass++) {
- read_vec_element(s, tcg_int64, rn, pass, mop);
-
- if (is_signed) {
- gen_helper_vfp_sqtod(tcg_double, tcg_int64,
- tcg_shift, tcg_fpst);
- } else {
- gen_helper_vfp_uqtod(tcg_double, tcg_int64,
- tcg_shift, tcg_fpst);
- }
- if (elements == 1) {
- write_fp_dreg(s, rd, tcg_double);
- } else {
- write_vec_element(s, tcg_double, rd, pass, MO_64);
- }
- }
- } else {
- TCGv_i32 tcg_int32 = tcg_temp_new_i32();
- TCGv_i32 tcg_float = tcg_temp_new_i32();
-
- for (pass = 0; pass < elements; pass++) {
- read_vec_element_i32(s, tcg_int32, rn, pass, mop);
-
- switch (size) {
- case MO_32:
- if (fracbits) {
- if (is_signed) {
- gen_helper_vfp_sltos(tcg_float, tcg_int32,
- tcg_shift, tcg_fpst);
- } else {
- gen_helper_vfp_ultos(tcg_float, tcg_int32,
- tcg_shift, tcg_fpst);
- }
- } else {
- if (is_signed) {
- gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);
- } else {
- gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);
- }
- }
- break;
- case MO_16:
- if (fracbits) {
- if (is_signed) {
- gen_helper_vfp_sltoh(tcg_float, tcg_int32,
- tcg_shift, tcg_fpst);
- } else {
- gen_helper_vfp_ultoh(tcg_float, tcg_int32,
- tcg_shift, tcg_fpst);
- }
- } else {
- if (is_signed) {
- gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);
- } else {
- gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);
- }
- }
- break;
- default:
- g_assert_not_reached();
- }
-
- if (elements == 1) {
- write_fp_sreg(s, rd, tcg_float);
- } else {
- write_vec_element_i32(s, tcg_float, rd, pass, size);
- }
- }
- }
-
- clear_vec_high(s, elements << size == 16, rd);
+ fpst = fpstatus_ptr(esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), fpst,
+ is_q ? 16 : 8, vec_full_reg_size(s),
+ data, fns[esz - 1]);
+ return true;
}
-/* UCVTF/SCVTF - Integer to FP conversion */
-static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
- bool is_q, bool is_u,
- int immh, int immb, int opcode,
- int rn, int rd)
-{
- int size, elements, fracbits;
- int immhb = immh << 3 | immb;
+static gen_helper_gvec_2_ptr * const f_scvtf_v[] = {
+ gen_helper_gvec_vcvt_sh,
+ gen_helper_gvec_vcvt_sf,
+ gen_helper_gvec_vcvt_sd,
+};
+TRANS(SCVTF_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, 0, f_scvtf_v)
+TRANS(SCVTF_vf, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, a->shift, f_scvtf_v)
- if (immh & 8) {
- size = MO_64;
- if (!is_scalar && !is_q) {
- unallocated_encoding(s);
- return;
- }
- } else if (immh & 4) {
- size = MO_32;
- } else if (immh & 2) {
- size = MO_16;
- if (!dc_isar_feature(aa64_fp16, s)) {
- unallocated_encoding(s);
- return;
- }
- } else {
- /* immh == 0 would be a failure of the decode logic */
- g_assert(immh == 1);
- unallocated_encoding(s);
- return;
- }
-
- if (is_scalar) {
- elements = 1;
- } else {
- elements = (8 << is_q) >> size;
- }
- fracbits = (16 << size) - immhb;
-
- if (!fp_access_check(s)) {
- return;
- }
-
- handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
-}
+static gen_helper_gvec_2_ptr * const f_ucvtf_v[] = {
+ gen_helper_gvec_vcvt_uh,
+ gen_helper_gvec_vcvt_uf,
+ gen_helper_gvec_vcvt_ud,
+};
+TRANS(UCVTF_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, 0, f_ucvtf_v)
+TRANS(UCVTF_vf, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, a->shift, f_ucvtf_v)
/* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
@@ -9890,10 +9793,6 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
}
switch (opcode) {
- case 0x1c: /* SCVTF / UCVTF */
- handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
- opcode, rn, rd);
- break;
case 0x1f: /* FCVTZS/ FCVTZU */
handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd);
return;
@@ -9911,6 +9810,7 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
case 0x12: /* SQSHRN / UQSHRN */
case 0x13: /* SQRSHRN / UQRSHRN */
case 0x14: /* SSHLL / USHLL */
+ case 0x1c: /* SCVTF / UCVTF */
unallocated_encoding(s);
return;
}
@@ -9990,21 +9890,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
size = is_double ? 3 : 2;
switch (opcode) {
- case 0x1d: /* SCVTF */
- case 0x5d: /* UCVTF */
- {
- bool is_signed = (opcode == 0x1d) ? true : false;
- int elements = is_double ? 2 : is_q ? 4 : 2;
- if (is_double && !is_q) {
- unallocated_encoding(s);
- return;
- }
- if (!fp_access_check(s)) {
- return;
- }
- handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size);
- return;
- }
case 0x2c: /* FCMGT (zero) */
case 0x2d: /* FCMEQ (zero) */
case 0x2e: /* FCMLT (zero) */
@@ -10087,6 +9972,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x1f: /* FRINT64Z */
case 0x5e: /* FRINT32X */
case 0x5f: /* FRINT64X */
+ case 0x1d: /* SCVTF */
+ case 0x5d: /* UCVTF */
unallocated_encoding(s);
return;
}
@@ -10252,24 +10139,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
fpop = deposit32(fpop, 6, 1, u);
switch (fpop) {
- case 0x1d: /* SCVTF */
- case 0x5d: /* UCVTF */
- {
- int elements;
-
- if (is_scalar) {
- elements = 1;
- } else {
- elements = (is_q ? 8 : 4);
- }
-
- if (!fp_access_check(s)) {
- return;
- }
- handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);
- return;
- }
- break;
case 0x2c: /* FCMGT (zero) */
case 0x2d: /* FCMEQ (zero) */
case 0x2e: /* FCMLT (zero) */
@@ -10323,6 +10192,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x58: /* FRINTA */
case 0x59: /* FRINTX */
case 0x79: /* FRINTI */
+ case 0x1d: /* SCVTF */
+ case 0x5d: /* UCVTF */
unallocated_encoding(s);
return;
}
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 282dba4bfd..aa85cea0ca 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2505,12 +2505,15 @@ DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4)
clear_tail(d, oprsz, simd_maxsz(desc)); \
}
+DO_VCVT_FIXED(gvec_vcvt_sd, helper_vfp_sqtod, uint64_t)
+DO_VCVT_FIXED(gvec_vcvt_ud, helper_vfp_uqtod, uint64_t)
DO_VCVT_FIXED(gvec_vcvt_sf, helper_vfp_sltos, uint32_t)
DO_VCVT_FIXED(gvec_vcvt_uf, helper_vfp_ultos, uint32_t)
-DO_VCVT_FIXED(gvec_vcvt_rz_fs, helper_vfp_tosls_round_to_zero, uint32_t)
-DO_VCVT_FIXED(gvec_vcvt_rz_fu, helper_vfp_touls_round_to_zero, uint32_t)
DO_VCVT_FIXED(gvec_vcvt_sh, helper_vfp_shtoh, uint16_t)
DO_VCVT_FIXED(gvec_vcvt_uh, helper_vfp_uhtoh, uint16_t)
+
+DO_VCVT_FIXED(gvec_vcvt_rz_fs, helper_vfp_tosls_round_to_zero, uint32_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_fu, helper_vfp_touls_round_to_zero, uint32_t)
DO_VCVT_FIXED(gvec_vcvt_rz_hs, helper_vfp_toshh_round_to_zero, uint16_t)
DO_VCVT_FIXED(gvec_vcvt_rz_hu, helper_vfp_touhh_round_to_zero, uint16_t)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 197555555e..bb94374f22 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1786,3 +1786,25 @@ FRINT32Z_v 0.00 1110 0.1 00001 11101 0 ..... ..... @qrr_sd
FRINT32X_v 0.10 1110 0.1 00001 11101 0 ..... ..... @qrr_sd
FRINT64Z_v 0.00 1110 0.1 00001 11111 0 ..... ..... @qrr_sd
FRINT64X_v 0.10 1110 0.1 00001 11111 0 ..... ..... @qrr_sd
+
+SCVTF_vi 0.00 1110 011 11001 11011 0 ..... ..... @qrr_h
+SCVTF_vi 0.00 1110 0.1 00001 11011 0 ..... ..... @qrr_sd
+
+UCVTF_vi 0.10 1110 011 11001 11011 0 ..... ..... @qrr_h
+UCVTF_vi 0.10 1110 0.1 00001 11011 0 ..... ..... @qrr_sd
+
+&fcvt_q rd rn esz q shift
+@fcvtq_h . q:1 . ...... 001 .... ...... rn:5 rd:5 \
+ &fcvt_q esz=1 shift=%fcvt_f_sh_h
+@fcvtq_s . q:1 . ...... 01 ..... ...... rn:5 rd:5 \
+ &fcvt_q esz=2 shift=%fcvt_f_sh_s
+@fcvtq_d . q:1 . ...... 1 ...... ...... rn:5 rd:5 \
+ &fcvt_q esz=3 shift=%fcvt_f_sh_d
+
+SCVTF_vf 0.00 11110 ....... 111001 ..... ..... @fcvtq_h
+SCVTF_vf 0.00 11110 ....... 111001 ..... ..... @fcvtq_s
+SCVTF_vf 0.00 11110 ....... 111001 ..... ..... @fcvtq_d
+
+UCVTF_vf 0.10 11110 ....... 111001 ..... ..... @fcvtq_h
+UCVTF_vf 0.10 11110 ....... 111001 ..... ..... @fcvtq_s
+UCVTF_vf 0.10 11110 ....... 111001 ..... ..... @fcvtq_d
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 61/67] target/arm: Convert FCVTZ[SU] (vector, fixed-point) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (59 preceding siblings ...)
2024-12-01 15:05 ` [PATCH 60/67] target/arm: Convert [US]CVTF (vector) to decodetree Richard Henderson
@ 2024-12-01 15:06 ` Richard Henderson
2024-12-01 15:06 ` [PATCH 62/67] target/arm: Convert FCVT* (vector, integer) " Richard Henderson
` (6 subsequent siblings)
67 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:06 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove handle_simd_shift_fpint_conv and disas_simd_shift_imm
as these were the last insns decoded by those functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 4 +
target/arm/tcg/translate-a64.c | 160 +++------------------------------
target/arm/tcg/vec_helper.c | 2 +
target/arm/vfp_helper.c | 4 +
target/arm/tcg/a64.decode | 8 ++
5 files changed, 32 insertions(+), 146 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index b227ac54d9..0c8a56c3ae 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -178,8 +178,10 @@ DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr)
DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, ptr)
DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
+DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, ptr)
DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
+DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, ptr)
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
@@ -660,6 +662,8 @@ DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 26ae38b99e..f49c86a114 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9344,107 +9344,21 @@ TRANS(UCVTF_vi, do_gvec_op2_fpst,
TRANS(UCVTF_vf, do_gvec_op2_fpst,
a->esz, a->q, a->rd, a->rn, a->shift, f_ucvtf_v)
-/* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
-static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
- bool is_q, bool is_u,
- int immh, int immb, int rn, int rd)
-{
- int immhb = immh << 3 | immb;
- int pass, size, fracbits;
- TCGv_ptr tcg_fpstatus;
- TCGv_i32 tcg_rmode, tcg_shift;
+static gen_helper_gvec_2_ptr * const f_fcvtzs_vf[] = {
+ gen_helper_gvec_vcvt_rz_hs,
+ gen_helper_gvec_vcvt_rz_fs,
+ gen_helper_gvec_vcvt_rz_ds,
+};
+TRANS(FCVTZS_vf, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, a->shift, f_fcvtzs_vf)
- if (immh & 0x8) {
- size = MO_64;
- if (!is_scalar && !is_q) {
- unallocated_encoding(s);
- return;
- }
- } else if (immh & 0x4) {
- size = MO_32;
- } else if (immh & 0x2) {
- size = MO_16;
- if (!dc_isar_feature(aa64_fp16, s)) {
- unallocated_encoding(s);
- return;
- }
- } else {
- /* Should have split out AdvSIMD modified immediate earlier. */
- assert(immh == 1);
- unallocated_encoding(s);
- return;
- }
-
- if (!fp_access_check(s)) {
- return;
- }
-
- assert(!(is_scalar && is_q));
-
- tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
- tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, tcg_fpstatus);
- fracbits = (16 << size) - immhb;
- tcg_shift = tcg_constant_i32(fracbits);
-
- if (size == MO_64) {
- int maxpass = is_scalar ? 1 : 2;
-
- for (pass = 0; pass < maxpass; pass++) {
- TCGv_i64 tcg_op = tcg_temp_new_i64();
-
- read_vec_element(s, tcg_op, rn, pass, MO_64);
- if (is_u) {
- gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
- } else {
- gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
- }
- write_vec_element(s, tcg_op, rd, pass, MO_64);
- }
- clear_vec_high(s, is_q, rd);
- } else {
- void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
- int maxpass = is_scalar ? 1 : ((8 << is_q) >> size);
-
- switch (size) {
- case MO_16:
- if (is_u) {
- fn = gen_helper_vfp_touhh;
- } else {
- fn = gen_helper_vfp_toshh;
- }
- break;
- case MO_32:
- if (is_u) {
- fn = gen_helper_vfp_touls;
- } else {
- fn = gen_helper_vfp_tosls;
- }
- break;
- default:
- g_assert_not_reached();
- }
-
- for (pass = 0; pass < maxpass; pass++) {
- TCGv_i32 tcg_op = tcg_temp_new_i32();
-
- read_vec_element_i32(s, tcg_op, rn, pass, size);
- fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
- if (is_scalar) {
- if (size == MO_16 && !is_u) {
- tcg_gen_ext16u_i32(tcg_op, tcg_op);
- }
- write_fp_sreg(s, rd, tcg_op);
- } else {
- write_vec_element_i32(s, tcg_op, rd, pass, size);
- }
- }
- if (!is_scalar) {
- clear_vec_high(s, is_q, rd);
- }
- }
-
- gen_restore_rmode(tcg_rmode, tcg_fpstatus);
-}
+static gen_helper_gvec_2_ptr * const f_fcvtzu_vf[] = {
+ gen_helper_gvec_vcvt_rz_hu,
+ gen_helper_gvec_vcvt_rz_fu,
+ gen_helper_gvec_vcvt_rz_du,
+};
+TRANS(FCVTZU_vf, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, a->shift, f_fcvtzu_vf)
static void handle_2misc_64(DisasContext *s, int opcode, bool u,
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
@@ -9771,51 +9685,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
g_assert_not_reached();
}
-/* AdvSIMD shift by immediate
- * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
- * +---+---+---+-------------+------+------+--------+---+------+------+
- * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
- * +---+---+---+-------------+------+------+--------+---+------+------+
- */
-static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
-{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int opcode = extract32(insn, 11, 5);
- int immb = extract32(insn, 16, 3);
- int immh = extract32(insn, 19, 4);
- bool is_u = extract32(insn, 29, 1);
- bool is_q = extract32(insn, 30, 1);
-
- if (immh == 0) {
- unallocated_encoding(s);
- return;
- }
-
- switch (opcode) {
- case 0x1f: /* FCVTZS/ FCVTZU */
- handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd);
- return;
- default:
- case 0x00: /* SSHR / USHR */
- case 0x02: /* SSRA / USRA (accumulate) */
- case 0x04: /* SRSHR / URSHR (rounding) */
- case 0x06: /* SRSRA / URSRA (accum + rounding) */
- case 0x08: /* SRI */
- case 0x0a: /* SHL / SLI */
- case 0x0c: /* SQSHLU */
- case 0x0e: /* SQSHL, UQSHL */
- case 0x10: /* SHRN / SQSHRUN */
- case 0x11: /* RSHRN / SQRSHRUN */
- case 0x12: /* SQSHRN / UQSHRN */
- case 0x13: /* SQRSHRN / UQRSHRN */
- case 0x14: /* SSHLL / USHLL */
- case 0x1c: /* SCVTF / UCVTF */
- unallocated_encoding(s);
- return;
- }
-}
-
static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
int size, int rn, int rd)
{
@@ -10312,7 +10181,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
static const AArch64DecodeTable data_proc_simd[] = {
/* pattern , mask , fn */
{ 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
- { 0x0f000400, 0x9f800400, disas_simd_shift_imm },
{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
{ 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
{ 0x00000000, 0x00000000, NULL }
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index aa85cea0ca..9b269a4f18 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2512,6 +2512,8 @@ DO_VCVT_FIXED(gvec_vcvt_uf, helper_vfp_ultos, uint32_t)
DO_VCVT_FIXED(gvec_vcvt_sh, helper_vfp_shtoh, uint16_t)
DO_VCVT_FIXED(gvec_vcvt_uh, helper_vfp_uhtoh, uint16_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_ds, helper_vfp_tosqd_round_to_zero, uint64_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_du, helper_vfp_touqd_round_to_zero, uint64_t)
DO_VCVT_FIXED(gvec_vcvt_rz_fs, helper_vfp_tosls_round_to_zero, uint32_t)
DO_VCVT_FIXED(gvec_vcvt_rz_fu, helper_vfp_touls_round_to_zero, uint32_t)
DO_VCVT_FIXED(gvec_vcvt_rz_hs, helper_vfp_toshh_round_to_zero, uint16_t)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index f24992c798..5a19af509c 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -495,6 +495,10 @@ VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64)
VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16)
VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32)
VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64)
+VFP_CONV_FLOAT_FIX_ROUND(sq, d, 64, float64, 64, int64,
+ float_round_to_zero, _round_to_zero)
+VFP_CONV_FLOAT_FIX_ROUND(uq, d, 64, float64, 64, uint64,
+ float_round_to_zero, _round_to_zero)
#undef VFP_CONV_FIX
#undef VFP_CONV_FIX_FLOAT
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index bb94374f22..ea838ad04f 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1808,3 +1808,11 @@ SCVTF_vf 0.00 11110 ....... 111001 ..... ..... @fcvtq_d
UCVTF_vf 0.10 11110 ....... 111001 ..... ..... @fcvtq_h
UCVTF_vf 0.10 11110 ....... 111001 ..... ..... @fcvtq_s
UCVTF_vf 0.10 11110 ....... 111001 ..... ..... @fcvtq_d
+
+FCVTZS_vf 0.00 11110 ....... 111111 ..... ..... @fcvtq_h
+FCVTZS_vf 0.00 11110 ....... 111111 ..... ..... @fcvtq_s
+FCVTZS_vf 0.00 11110 ....... 111111 ..... ..... @fcvtq_d
+
+FCVTZU_vf 0.10 11110 ....... 111111 ..... ..... @fcvtq_h
+FCVTZU_vf 0.10 11110 ....... 111111 ..... ..... @fcvtq_s
+FCVTZU_vf 0.10 11110 ....... 111111 ..... ..... @fcvtq_d
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 62/67] target/arm: Convert FCVT* (vector, integer) to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (60 preceding siblings ...)
2024-12-01 15:06 ` [PATCH 61/67] target/arm: Convert FCVTZ[SU] (vector, fixed-point) " Richard Henderson
@ 2024-12-01 15:06 ` Richard Henderson
2024-12-01 15:06 ` [PATCH 63/67] target/arm: Convert handle_2misc_fcmp_zero " Richard Henderson
` (5 subsequent siblings)
67 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:06 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove handle_2misc_64 as these were the last insns decoded
by that function. Remove helper_advsimd_f16to[su]inth as unused;
we now always go through helper_vfp_to[su]hh or a specialized
vector function instead.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 2 +
target/arm/tcg/helper-a64.h | 2 -
target/arm/tcg/helper-a64.c | 32 -----
target/arm/tcg/translate-a64.c | 227 +++++++++++----------------------
target/arm/tcg/vec_helper.c | 2 +
target/arm/tcg/a64.decode | 25 ++++
6 files changed, 102 insertions(+), 188 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 0c8a56c3ae..64aa603465 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -665,6 +665,8 @@ DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
index ac7ca190fa..3c0774139b 100644
--- a/target/arm/tcg/helper-a64.h
+++ b/target/arm/tcg/helper-a64.h
@@ -74,8 +74,6 @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
-DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
-DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
DEF_HELPER_2(exception_return, void, env, i64)
DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64)
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 3de564e0fe..28de7468cd 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -618,38 +618,6 @@ uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
return ret;
}
-/*
- * Half-precision floating point conversion functions
- *
- * There are a multitude of conversion functions with various
- * different rounding modes. This is dealt with by the calling code
- * setting the mode appropriately before calling the helper.
- */
-
-uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
-{
- float_status *fpst = fpstp;
-
- /* Invalid if we are passed a NaN */
- if (float16_is_any_nan(a)) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_int16(a, fpst);
-}
-
-uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
-{
- float_status *fpst = fpstp;
-
- /* Invalid if we are passed a NaN */
- if (float16_is_any_nan(a)) {
- float_raise(float_flag_invalid, fpst);
- return 0;
- }
- return float16_to_uint16(a, fpst);
-}
-
static int el_from_spsr(uint32_t spsr)
{
/* Return the exception level that this SPSR is requesting a return to,
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index f49c86a114..a570ae1153 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9360,56 +9360,38 @@ static gen_helper_gvec_2_ptr * const f_fcvtzu_vf[] = {
TRANS(FCVTZU_vf, do_gvec_op2_fpst,
a->esz, a->q, a->rd, a->rn, a->shift, f_fcvtzu_vf)
-static void handle_2misc_64(DisasContext *s, int opcode, bool u,
- TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
- TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
-{
- /* Handle 64->64 opcodes which are shared between the scalar and
- * vector 2-reg-misc groups. We cover every integer opcode where size == 3
- * is valid in either group and also the double-precision fp ops.
- * The caller only need provide tcg_rmode and tcg_fpstatus if the op
- * requires them.
- */
- switch (opcode) {
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
- break;
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x5c: /* FCVTAU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
- break;
- default:
- case 0x4: /* CLS, CLZ */
- case 0x5: /* NOT */
- case 0x7: /* SQABS, SQNEG */
- case 0x8: /* CMGT, CMGE */
- case 0x9: /* CMEQ, CMLE */
- case 0xa: /* CMLT */
- case 0xb: /* ABS, NEG */
- case 0x2f: /* FABS */
- case 0x6f: /* FNEG */
- case 0x7f: /* FSQRT */
- case 0x18: /* FRINTN */
- case 0x19: /* FRINTM */
- case 0x38: /* FRINTP */
- case 0x39: /* FRINTZ */
- case 0x58: /* FRINTA */
- case 0x79: /* FRINTI */
- case 0x59: /* FRINTX */
- case 0x1e: /* FRINT32Z */
- case 0x5e: /* FRINT32X */
- case 0x1f: /* FRINT64Z */
- case 0x5f: /* FRINT64X */
- g_assert_not_reached();
- }
-}
+static gen_helper_gvec_2_ptr * const f_fcvt_s_vi[] = {
+ gen_helper_gvec_vcvt_rm_sh,
+ gen_helper_gvec_vcvt_rm_ss,
+ gen_helper_gvec_vcvt_rm_sd,
+};
+
+static gen_helper_gvec_2_ptr * const f_fcvt_u_vi[] = {
+ gen_helper_gvec_vcvt_rm_uh,
+ gen_helper_gvec_vcvt_rm_us,
+ gen_helper_gvec_vcvt_rm_ud,
+};
+
+TRANS(FCVTNS_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, float_round_nearest_even, f_fcvt_s_vi)
+TRANS(FCVTNU_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, float_round_nearest_even, f_fcvt_u_vi)
+TRANS(FCVTPS_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, float_round_up, f_fcvt_s_vi)
+TRANS(FCVTPU_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, float_round_up, f_fcvt_u_vi)
+TRANS(FCVTMS_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, float_round_down, f_fcvt_s_vi)
+TRANS(FCVTMU_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, float_round_down, f_fcvt_u_vi)
+TRANS(FCVTZS_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, float_round_to_zero, f_fcvt_s_vi)
+TRANS(FCVTZU_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, float_round_to_zero, f_fcvt_u_vi)
+TRANS(FCVTAS_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, float_round_ties_away, f_fcvt_s_vi)
+TRANS(FCVTAU_vi, do_gvec_op2_fpst,
+ a->esz, a->q, a->rd, a->rn, float_round_ties_away, f_fcvt_u_vi)
static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
bool is_scalar, bool is_u, bool is_q,
@@ -9770,30 +9752,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
return;
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- need_fpstatus = true;
- rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- break;
- case 0x5c: /* FCVTAU */
- case 0x1c: /* FCVTAS */
- need_fpstatus = true;
- rmode = FPROUNDING_TIEAWAY;
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- break;
case 0x3c: /* URECPE */
if (size == 3) {
unallocated_encoding(s);
@@ -9843,6 +9801,16 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x5f: /* FRINT64X */
case 0x1d: /* SCVTF */
case 0x5d: /* UCVTF */
+ case 0x1a: /* FCVTNS */
+ case 0x1b: /* FCVTMS */
+ case 0x3a: /* FCVTPS */
+ case 0x3b: /* FCVTZS */
+ case 0x5a: /* FCVTNU */
+ case 0x5b: /* FCVTMU */
+ case 0x7a: /* FCVTPU */
+ case 0x7b: /* FCVTZU */
+ case 0x5c: /* FCVTAU */
+ case 0x1c: /* FCVTAS */
unallocated_encoding(s);
return;
}
@@ -9883,26 +9851,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
tcg_rmode = NULL;
}
- if (size == 3) {
- /* All 64-bit element operations can be shared with scalar 2misc */
- int pass;
-
- /* Coverity claims (size == 3 && !is_q) has been eliminated
- * from all paths leading to here.
- */
- tcg_debug_assert(is_q);
- for (pass = 0; pass < 2; pass++) {
- TCGv_i64 tcg_op = tcg_temp_new_i64();
- TCGv_i64 tcg_res = tcg_temp_new_i64();
-
- read_vec_element(s, tcg_op, rn, pass, MO_64);
-
- handle_2misc_64(s, opcode, u, tcg_res, tcg_op,
- tcg_rmode, tcg_fpstatus);
-
- write_vec_element(s, tcg_res, rd, pass, MO_64);
- }
- } else {
+ {
int pass;
assert(size == 2);
@@ -9915,22 +9864,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
{
/* Special cases for 32 bit elements */
switch (opcode) {
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- gen_helper_vfp_tosls(tcg_res, tcg_op,
- tcg_constant_i32(0), tcg_fpstatus);
- break;
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x5c: /* FCVTAU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- gen_helper_vfp_touls(tcg_res, tcg_op,
- tcg_constant_i32(0), tcg_fpstatus);
- break;
case 0x7c: /* URSQRTE */
gen_helper_rsqrte_u32(tcg_res, tcg_op);
break;
@@ -9950,6 +9883,16 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x5e: /* FRINT32X */
case 0x1f: /* FRINT64Z */
case 0x5f: /* FRINT64X */
+ case 0x1a: /* FCVTNS */
+ case 0x1b: /* FCVTMS */
+ case 0x1c: /* FCVTAS */
+ case 0x3a: /* FCVTPS */
+ case 0x3b: /* FCVTZS */
+ case 0x5a: /* FCVTNU */
+ case 0x5b: /* FCVTMU */
+ case 0x5c: /* FCVTAU */
+ case 0x7a: /* FCVTPU */
+ case 0x7b: /* FCVTZU */
g_assert_not_reached();
}
}
@@ -10018,36 +9961,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x3d: /* FRECPE */
case 0x3f: /* FRECPX */
break;
- case 0x1a: /* FCVTNS */
- rmode = FPROUNDING_TIEEVEN;
- break;
- case 0x1b: /* FCVTMS */
- rmode = FPROUNDING_NEGINF;
- break;
- case 0x1c: /* FCVTAS */
- rmode = FPROUNDING_TIEAWAY;
- break;
- case 0x3a: /* FCVTPS */
- rmode = FPROUNDING_POSINF;
- break;
- case 0x3b: /* FCVTZS */
- rmode = FPROUNDING_ZERO;
- break;
- case 0x5a: /* FCVTNU */
- rmode = FPROUNDING_TIEEVEN;
- break;
- case 0x5b: /* FCVTMU */
- rmode = FPROUNDING_NEGINF;
- break;
- case 0x5c: /* FCVTAU */
- rmode = FPROUNDING_TIEAWAY;
- break;
- case 0x7a: /* FCVTPU */
- rmode = FPROUNDING_POSINF;
- break;
- case 0x7b: /* FCVTZU */
- rmode = FPROUNDING_ZERO;
- break;
case 0x7d: /* FRSQRTE */
break;
default:
@@ -10063,6 +9976,16 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x79: /* FRINTI */
case 0x1d: /* SCVTF */
case 0x5d: /* UCVTF */
+ case 0x1a: /* FCVTNS */
+ case 0x1b: /* FCVTMS */
+ case 0x1c: /* FCVTAS */
+ case 0x3a: /* FCVTPS */
+ case 0x3b: /* FCVTZS */
+ case 0x5a: /* FCVTNU */
+ case 0x5b: /* FCVTMU */
+ case 0x5c: /* FCVTAU */
+ case 0x7a: /* FCVTPU */
+ case 0x7b: /* FCVTZU */
unallocated_encoding(s);
return;
}
@@ -10128,23 +10051,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
switch (fpop) {
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
- break;
case 0x3d: /* FRECPE */
gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x5c: /* FCVTAU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
- break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
@@ -10159,6 +10068,16 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x58: /* FRINTA */
case 0x79: /* FRINTI */
case 0x59: /* FRINTX */
+ case 0x1a: /* FCVTNS */
+ case 0x1b: /* FCVTMS */
+ case 0x1c: /* FCVTAS */
+ case 0x3a: /* FCVTPS */
+ case 0x3b: /* FCVTZS */
+ case 0x5a: /* FCVTNU */
+ case 0x5b: /* FCVTMU */
+ case 0x5c: /* FCVTAU */
+ case 0x7a: /* FCVTPU */
+ case 0x7b: /* FCVTZU */
g_assert_not_reached();
}
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 9b269a4f18..0aee38a3bc 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2537,6 +2537,8 @@ DO_VCVT_FIXED(gvec_vcvt_rz_hu, helper_vfp_touhh_round_to_zero, uint16_t)
clear_tail(d, oprsz, simd_maxsz(desc)); \
}
+DO_VCVT_RMODE(gvec_vcvt_rm_sd, helper_vfp_tosqd, uint64_t)
+DO_VCVT_RMODE(gvec_vcvt_rm_ud, helper_vfp_touqd, uint64_t)
DO_VCVT_RMODE(gvec_vcvt_rm_ss, helper_vfp_tosls, uint32_t)
DO_VCVT_RMODE(gvec_vcvt_rm_us, helper_vfp_touls, uint32_t)
DO_VCVT_RMODE(gvec_vcvt_rm_sh, helper_vfp_toshh, uint16_t)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index ea838ad04f..4f85ffb8be 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1793,6 +1793,31 @@ SCVTF_vi 0.00 1110 0.1 00001 11011 0 ..... ..... @qrr_sd
UCVTF_vi 0.10 1110 011 11001 11011 0 ..... ..... @qrr_h
UCVTF_vi 0.10 1110 0.1 00001 11011 0 ..... ..... @qrr_sd
+FCVTNS_vi 0.00 1110 011 11001 10101 0 ..... ..... @qrr_h
+FCVTNS_vi 0.00 1110 0.1 00001 10101 0 ..... ..... @qrr_sd
+FCVTNU_vi 0.10 1110 011 11001 10101 0 ..... ..... @qrr_h
+FCVTNU_vi 0.10 1110 0.1 00001 10101 0 ..... ..... @qrr_sd
+
+FCVTPS_vi 0.00 1110 111 11001 10101 0 ..... ..... @qrr_h
+FCVTPS_vi 0.00 1110 1.1 00001 10101 0 ..... ..... @qrr_sd
+FCVTPU_vi 0.10 1110 111 11001 10101 0 ..... ..... @qrr_h
+FCVTPU_vi 0.10 1110 1.1 00001 10101 0 ..... ..... @qrr_sd
+
+FCVTMS_vi 0.00 1110 011 11001 10111 0 ..... ..... @qrr_h
+FCVTMS_vi 0.00 1110 0.1 00001 10111 0 ..... ..... @qrr_sd
+FCVTMU_vi 0.10 1110 011 11001 10111 0 ..... ..... @qrr_h
+FCVTMU_vi 0.10 1110 0.1 00001 10111 0 ..... ..... @qrr_sd
+
+FCVTZS_vi 0.00 1110 111 11001 10111 0 ..... ..... @qrr_h
+FCVTZS_vi 0.00 1110 1.1 00001 10111 0 ..... ..... @qrr_sd
+FCVTZU_vi 0.10 1110 111 11001 10111 0 ..... ..... @qrr_h
+FCVTZU_vi 0.10 1110 1.1 00001 10111 0 ..... ..... @qrr_sd
+
+FCVTAS_vi 0.00 1110 011 11001 11001 0 ..... ..... @qrr_h
+FCVTAS_vi 0.00 1110 0.1 00001 11001 0 ..... ..... @qrr_sd
+FCVTAU_vi 0.10 1110 011 11001 11001 0 ..... ..... @qrr_h
+FCVTAU_vi 0.10 1110 0.1 00001 11001 0 ..... ..... @qrr_sd
+
&fcvt_q rd rn esz q shift
@fcvtq_h . q:1 . ...... 001 .... ...... rn:5 rd:5 \
&fcvt_q esz=1 shift=%fcvt_f_sh_h
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 63/67] target/arm: Convert handle_2misc_fcmp_zero to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (61 preceding siblings ...)
2024-12-01 15:06 ` [PATCH 62/67] target/arm: Convert FCVT* (vector, integer) " Richard Henderson
@ 2024-12-01 15:06 ` Richard Henderson
2024-12-06 16:29 ` Peter Maydell
2024-12-01 15:06 ` [PATCH 64/67] target/arm: Convert FRECPE, FRECPX, FRSQRTE " Richard Henderson
` (4 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:06 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
This includes FCMEQ, FCMGT, FCMGE, FCMLT, FCMLE.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 5 +
target/arm/tcg/translate-a64.c | 249 +++++++++++++--------------------
target/arm/tcg/vec_helper.c | 4 +-
target/arm/tcg/a64.decode | 30 ++++
4 files changed, 138 insertions(+), 150 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 64aa603465..1132a5cab6 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -688,18 +688,23 @@ DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index a570ae1153..211e313cb3 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5250,6 +5250,61 @@ static const FPScalar f_scalar_frsqrts = {
};
TRANS(FRSQRTS_s, do_fp3_scalar, a, &f_scalar_frsqrts)
+static bool do_fcmp0_s(DisasContext *s, arg_rr_e *a,
+ const FPScalar *f, bool swap)
+{
+ switch (a->esz) {
+ case MO_64:
+ if (fp_access_check(s)) {
+ TCGv_i64 t0 = read_fp_dreg(s, a->rn);
+ TCGv_i64 t1 = tcg_constant_i64(0);
+ if (swap) {
+ f->gen_d(t0, t1, t0, fpstatus_ptr(FPST_FPCR));
+ } else {
+ f->gen_d(t0, t0, t1, fpstatus_ptr(FPST_FPCR));
+ }
+ write_fp_dreg(s, a->rd, t0);
+ }
+ break;
+ case MO_32:
+ if (fp_access_check(s)) {
+ TCGv_i32 t0 = read_fp_sreg(s, a->rn);
+ TCGv_i32 t1 = tcg_constant_i32(0);
+ if (swap) {
+ f->gen_s(t0, t1, t0, fpstatus_ptr(FPST_FPCR));
+ } else {
+ f->gen_s(t0, t0, t1, fpstatus_ptr(FPST_FPCR));
+ }
+ write_fp_sreg(s, a->rd, t0);
+ }
+ break;
+ case MO_16:
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ return false;
+ }
+ if (fp_access_check(s)) {
+ TCGv_i32 t0 = read_fp_hreg(s, a->rn);
+ TCGv_i32 t1 = tcg_constant_i32(0);
+ if (swap) {
+ f->gen_h(t0, t1, t0, fpstatus_ptr(FPST_FPCR_F16));
+ } else {
+ f->gen_h(t0, t0, t1, fpstatus_ptr(FPST_FPCR_F16));
+ }
+ write_fp_sreg(s, a->rd, t0);
+ }
+ break;
+ default:
+ return false;
+ }
+ return true;
+}
+
+TRANS(FCMEQ0_s, do_fcmp0_s, a, &f_scalar_fcmeq, false)
+TRANS(FCMGT0_s, do_fcmp0_s, a, &f_scalar_fcmgt, false)
+TRANS(FCMGE0_s, do_fcmp0_s, a, &f_scalar_fcmge, false)
+TRANS(FCMLT0_s, do_fcmp0_s, a, &f_scalar_fcmgt, true)
+TRANS(FCMLE0_s, do_fcmp0_s, a, &f_scalar_fcmge, true)
+
static bool do_satacc_s(DisasContext *s, arg_rrr_e *a,
MemOp sgn_n, MemOp sgn_m,
void (*gen_bhs)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, MemOp),
@@ -9393,134 +9448,40 @@ TRANS(FCVTAS_vi, do_gvec_op2_fpst,
TRANS(FCVTAU_vi, do_gvec_op2_fpst,
a->esz, a->q, a->rd, a->rn, float_round_ties_away, f_fcvt_u_vi)
-static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
- bool is_scalar, bool is_u, bool is_q,
- int size, int rn, int rd)
-{
- bool is_double = (size == MO_64);
- TCGv_ptr fpst;
+static gen_helper_gvec_2_ptr * const f_fceq0[] = {
+ gen_helper_gvec_fceq0_h,
+ gen_helper_gvec_fceq0_s,
+ gen_helper_gvec_fceq0_d,
+};
+TRANS(FCMEQ0_v, do_gvec_op2_fpst, a->esz, a->q, a->rd, a->rn, 0, f_fceq0)
- if (!fp_access_check(s)) {
- return;
- }
+static gen_helper_gvec_2_ptr * const f_fcgt0[] = {
+ gen_helper_gvec_fcgt0_h,
+ gen_helper_gvec_fcgt0_s,
+ gen_helper_gvec_fcgt0_d,
+};
+TRANS(FCMGT0_v, do_gvec_op2_fpst, a->esz, a->q, a->rd, a->rn, 0, f_fcgt0)
- fpst = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
+static gen_helper_gvec_2_ptr * const f_fcge0[] = {
+ gen_helper_gvec_fcge0_h,
+ gen_helper_gvec_fcge0_s,
+ gen_helper_gvec_fcge0_d,
+};
+TRANS(FCMGE0_v, do_gvec_op2_fpst, a->esz, a->q, a->rd, a->rn, 0, f_fcge0)
- if (is_double) {
- TCGv_i64 tcg_op = tcg_temp_new_i64();
- TCGv_i64 tcg_zero = tcg_constant_i64(0);
- TCGv_i64 tcg_res = tcg_temp_new_i64();
- NeonGenTwoDoubleOpFn *genfn;
- bool swap = false;
- int pass;
+static gen_helper_gvec_2_ptr * const f_fclt0[] = {
+ gen_helper_gvec_fclt0_h,
+ gen_helper_gvec_fclt0_s,
+ gen_helper_gvec_fclt0_d,
+};
+TRANS(FCMLT0_v, do_gvec_op2_fpst, a->esz, a->q, a->rd, a->rn, 0, f_fclt0)
- switch (opcode) {
- case 0x2e: /* FCMLT (zero) */
- swap = true;
- /* fallthrough */
- case 0x2c: /* FCMGT (zero) */
- genfn = gen_helper_neon_cgt_f64;
- break;
- case 0x2d: /* FCMEQ (zero) */
- genfn = gen_helper_neon_ceq_f64;
- break;
- case 0x6d: /* FCMLE (zero) */
- swap = true;
- /* fall through */
- case 0x6c: /* FCMGE (zero) */
- genfn = gen_helper_neon_cge_f64;
- break;
- default:
- g_assert_not_reached();
- }
-
- for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
- read_vec_element(s, tcg_op, rn, pass, MO_64);
- if (swap) {
- genfn(tcg_res, tcg_zero, tcg_op, fpst);
- } else {
- genfn(tcg_res, tcg_op, tcg_zero, fpst);
- }
- write_vec_element(s, tcg_res, rd, pass, MO_64);
- }
-
- clear_vec_high(s, !is_scalar, rd);
- } else {
- TCGv_i32 tcg_op = tcg_temp_new_i32();
- TCGv_i32 tcg_zero = tcg_constant_i32(0);
- TCGv_i32 tcg_res = tcg_temp_new_i32();
- NeonGenTwoSingleOpFn *genfn;
- bool swap = false;
- int pass, maxpasses;
-
- if (size == MO_16) {
- switch (opcode) {
- case 0x2e: /* FCMLT (zero) */
- swap = true;
- /* fall through */
- case 0x2c: /* FCMGT (zero) */
- genfn = gen_helper_advsimd_cgt_f16;
- break;
- case 0x2d: /* FCMEQ (zero) */
- genfn = gen_helper_advsimd_ceq_f16;
- break;
- case 0x6d: /* FCMLE (zero) */
- swap = true;
- /* fall through */
- case 0x6c: /* FCMGE (zero) */
- genfn = gen_helper_advsimd_cge_f16;
- break;
- default:
- g_assert_not_reached();
- }
- } else {
- switch (opcode) {
- case 0x2e: /* FCMLT (zero) */
- swap = true;
- /* fall through */
- case 0x2c: /* FCMGT (zero) */
- genfn = gen_helper_neon_cgt_f32;
- break;
- case 0x2d: /* FCMEQ (zero) */
- genfn = gen_helper_neon_ceq_f32;
- break;
- case 0x6d: /* FCMLE (zero) */
- swap = true;
- /* fall through */
- case 0x6c: /* FCMGE (zero) */
- genfn = gen_helper_neon_cge_f32;
- break;
- default:
- g_assert_not_reached();
- }
- }
-
- if (is_scalar) {
- maxpasses = 1;
- } else {
- int vector_size = 8 << is_q;
- maxpasses = vector_size >> size;
- }
-
- for (pass = 0; pass < maxpasses; pass++) {
- read_vec_element_i32(s, tcg_op, rn, pass, size);
- if (swap) {
- genfn(tcg_res, tcg_zero, tcg_op, fpst);
- } else {
- genfn(tcg_res, tcg_op, tcg_zero, fpst);
- }
- if (is_scalar) {
- write_fp_sreg(s, rd, tcg_res);
- } else {
- write_vec_element_i32(s, tcg_res, rd, pass, size);
- }
- }
-
- if (!is_scalar) {
- clear_vec_high(s, is_q, rd);
- }
- }
-}
+static gen_helper_gvec_2_ptr * const f_fcle0[] = {
+ gen_helper_gvec_fcle0_h,
+ gen_helper_gvec_fcle0_s,
+ gen_helper_gvec_fcle0_d,
+};
+TRANS(FCMLE0_v, do_gvec_op2_fpst, a->esz, a->q, a->rd, a->rn, 0, f_fcle0)
static void handle_2misc_reciprocal(DisasContext *s, int opcode,
bool is_scalar, bool is_u, bool is_q,
@@ -9619,13 +9580,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
size = extract32(size, 0, 1) ? 3 : 2;
switch (opcode) {
- case 0x2c: /* FCMGT (zero) */
- case 0x2d: /* FCMEQ (zero) */
- case 0x2e: /* FCMLT (zero) */
- case 0x6c: /* FCMGE (zero) */
- case 0x6d: /* FCMLE (zero) */
- handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd);
- return;
case 0x3d: /* FRECPE */
case 0x3f: /* FRECPX */
case 0x7d: /* FRSQRTE */
@@ -9647,6 +9601,11 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x56: /* FCVTXN, FCVTXN2 */
case 0x1d: /* SCVTF */
case 0x5d: /* UCVTF */
+ case 0x2c: /* FCMGT (zero) */
+ case 0x2d: /* FCMEQ (zero) */
+ case 0x2e: /* FCMLT (zero) */
+ case 0x6c: /* FCMGE (zero) */
+ case 0x6d: /* FCMLE (zero) */
default:
unallocated_encoding(s);
return;
@@ -9741,17 +9700,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
size = is_double ? 3 : 2;
switch (opcode) {
- case 0x2c: /* FCMGT (zero) */
- case 0x2d: /* FCMEQ (zero) */
- case 0x2e: /* FCMLT (zero) */
- case 0x6c: /* FCMGE (zero) */
- case 0x6d: /* FCMLE (zero) */
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
- handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
- return;
case 0x3c: /* URECPE */
if (size == 3) {
unallocated_encoding(s);
@@ -9811,6 +9759,11 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x7b: /* FCVTZU */
case 0x5c: /* FCVTAU */
case 0x1c: /* FCVTAS */
+ case 0x2c: /* FCMGT (zero) */
+ case 0x2d: /* FCMEQ (zero) */
+ case 0x2e: /* FCMLT (zero) */
+ case 0x6c: /* FCMGE (zero) */
+ case 0x6d: /* FCMLE (zero) */
unallocated_encoding(s);
return;
}
@@ -9951,13 +9904,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
fpop = deposit32(fpop, 6, 1, u);
switch (fpop) {
- case 0x2c: /* FCMGT (zero) */
- case 0x2d: /* FCMEQ (zero) */
- case 0x2e: /* FCMLT (zero) */
- case 0x6c: /* FCMGE (zero) */
- case 0x6d: /* FCMLE (zero) */
- handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
- return;
case 0x3d: /* FRECPE */
case 0x3f: /* FRECPX */
break;
@@ -9986,6 +9932,11 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
+ case 0x2c: /* FCMGT (zero) */
+ case 0x2d: /* FCMEQ (zero) */
+ case 0x2e: /* FCMLT (zero) */
+ case 0x6c: /* FCMGE (zero) */
+ case 0x6d: /* FCMLE (zero) */
unallocated_encoding(s);
return;
}
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 0aee38a3bc..0f4b5670f3 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -1253,8 +1253,10 @@ DO_2OP(gvec_touszh, vfp_touszh, float16)
#define DO_2OP_CMP0(FN, CMPOP, DIRN) \
WRAP_CMP0_##DIRN(FN, CMPOP, float16) \
WRAP_CMP0_##DIRN(FN, CMPOP, float32) \
+ WRAP_CMP0_##DIRN(FN, CMPOP, float64) \
DO_2OP(gvec_f##FN##0_h, float16_##FN##0, float16) \
- DO_2OP(gvec_f##FN##0_s, float32_##FN##0, float32)
+ DO_2OP(gvec_f##FN##0_s, float32_##FN##0, float32) \
+ DO_2OP(gvec_f##FN##0_d, float64_##FN##0, float64)
DO_2OP_CMP0(cgt, cgt, FWD)
DO_2OP_CMP0(cge, cge, FWD)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 4f85ffb8be..640b2726c8 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1652,6 +1652,21 @@ UQXTN_s 0111 1110 ..1 00001 01001 0 ..... ..... @rr_e
FCVTXN_s 0111 1110 011 00001 01101 0 ..... ..... @rr_s
+FCMGT0_s 0101 1110 111 11000 11001 0 ..... ..... @rr_h
+FCMGT0_s 0101 1110 1.1 00000 11001 0 ..... ..... @rr_sd
+
+FCMGE0_s 0111 1110 111 11000 11001 0 ..... ..... @rr_h
+FCMGE0_s 0111 1110 1.1 00000 11001 0 ..... ..... @rr_sd
+
+FCMEQ0_s 0101 1110 111 11000 11011 0 ..... ..... @rr_h
+FCMEQ0_s 0101 1110 1.1 00000 11011 0 ..... ..... @rr_sd
+
+FCMLE0_s 0111 1110 111 11000 11011 0 ..... ..... @rr_h
+FCMLE0_s 0111 1110 1.1 00000 11011 0 ..... ..... @rr_sd
+
+FCMLT0_s 0101 1110 111 11000 11101 0 ..... ..... @rr_h
+FCMLT0_s 0101 1110 1.1 00000 11101 0 ..... ..... @rr_sd
+
@icvt_h . ....... .. ...... ...... rn:5 rd:5 \
&fcvt sf=0 esz=1 shift=0
@icvt_sd . ....... .. ...... ...... rn:5 rd:5 \
@@ -1818,6 +1833,21 @@ FCVTAS_vi 0.00 1110 0.1 00001 11001 0 ..... ..... @qrr_sd
FCVTAU_vi 0.10 1110 011 11001 11001 0 ..... ..... @qrr_h
FCVTAU_vi 0.10 1110 0.1 00001 11001 0 ..... ..... @qrr_sd
+FCMGT0_v 0.00 1110 111 11000 11001 0 ..... ..... @qrr_h
+FCMGT0_v 0.00 1110 1.1 00000 11001 0 ..... ..... @qrr_sd
+
+FCMGE0_v 0.10 1110 111 11000 11001 0 ..... ..... @qrr_h
+FCMGE0_v 0.10 1110 1.1 00000 11001 0 ..... ..... @qrr_sd
+
+FCMEQ0_v 0.00 1110 111 11000 11011 0 ..... ..... @qrr_h
+FCMEQ0_v 0.00 1110 1.1 00000 11011 0 ..... ..... @qrr_sd
+
+FCMLE0_v 0.10 1110 111 11000 11011 0 ..... ..... @qrr_h
+FCMLE0_v 0.10 1110 1.1 00000 11011 0 ..... ..... @qrr_sd
+
+FCMLT0_v 0.00 1110 111 11000 11101 0 ..... ..... @qrr_h
+FCMLT0_v 0.00 1110 1.1 00000 11101 0 ..... ..... @qrr_sd
+
&fcvt_q rd rn esz q shift
@fcvtq_h . q:1 . ...... 001 .... ...... rn:5 rd:5 \
&fcvt_q esz=1 shift=%fcvt_f_sh_h
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 64/67] target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (62 preceding siblings ...)
2024-12-01 15:06 ` [PATCH 63/67] target/arm: Convert handle_2misc_fcmp_zero " Richard Henderson
@ 2024-12-01 15:06 ` Richard Henderson
2024-12-06 16:31 ` Peter Maydell
2024-12-01 15:06 ` [PATCH 65/67] target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte Richard Henderson
` (3 subsequent siblings)
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:06 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove disas_simd_scalar_two_reg_misc and
disas_simd_two_reg_misc_fp16 as these were the
last insns decoded by those functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 330 ++++-----------------------------
target/arm/tcg/a64.decode | 15 ++
2 files changed, 53 insertions(+), 292 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 211e313cb3..c60e9a35cf 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8505,6 +8505,27 @@ TRANS_FEAT(FRINT64Z_s, aa64_frint, do_fp1_scalar, a,
&f_scalar_frint64, FPROUNDING_ZERO)
TRANS_FEAT(FRINT64X_s, aa64_frint, do_fp1_scalar, a, &f_scalar_frint64, -1)
+static const FPScalar1 f_scalar_frecpe = {
+ gen_helper_recpe_f16,
+ gen_helper_recpe_f32,
+ gen_helper_recpe_f64,
+};
+TRANS(FRECPE_s, do_fp1_scalar, a, &f_scalar_frecpe, -1)
+
+static const FPScalar1 f_scalar_frecpx = {
+ gen_helper_frecpx_f16,
+ gen_helper_frecpx_f32,
+ gen_helper_frecpx_f64,
+};
+TRANS(FRECPX_s, do_fp1_scalar, a, &f_scalar_frecpx, -1)
+
+static const FPScalar1 f_scalar_frsqrte = {
+ gen_helper_rsqrte_f16,
+ gen_helper_rsqrte_f32,
+ gen_helper_rsqrte_f64,
+};
+TRANS(FRSQRTE_s, do_fp1_scalar, a, &f_scalar_frsqrte, -1)
+
static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *a)
{
if (fp_access_check(s)) {
@@ -9483,36 +9504,28 @@ static gen_helper_gvec_2_ptr * const f_fcle0[] = {
};
TRANS(FCMLE0_v, do_gvec_op2_fpst, a->esz, a->q, a->rd, a->rn, 0, f_fcle0)
+static gen_helper_gvec_2_ptr * const f_frecpe[] = {
+ gen_helper_gvec_frecpe_h,
+ gen_helper_gvec_frecpe_s,
+ gen_helper_gvec_frecpe_d,
+};
+TRANS(FRECPE_v, do_gvec_op2_fpst, a->esz, a->q, a->rd, a->rn, 0, f_frecpe)
+
+static gen_helper_gvec_2_ptr * const f_frsqrte[] = {
+ gen_helper_gvec_frsqrte_h,
+ gen_helper_gvec_frsqrte_s,
+ gen_helper_gvec_frsqrte_d,
+};
+TRANS(FRSQRTE_v, do_gvec_op2_fpst, a->esz, a->q, a->rd, a->rn, 0, f_frsqrte)
+
static void handle_2misc_reciprocal(DisasContext *s, int opcode,
bool is_scalar, bool is_u, bool is_q,
int size, int rn, int rd)
{
bool is_double = (size == 3);
- TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
if (is_double) {
- TCGv_i64 tcg_op = tcg_temp_new_i64();
- TCGv_i64 tcg_res = tcg_temp_new_i64();
- int pass;
-
- for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
- read_vec_element(s, tcg_op, rn, pass, MO_64);
- switch (opcode) {
- case 0x3d: /* FRECPE */
- gen_helper_recpe_f64(tcg_res, tcg_op, fpst);
- break;
- case 0x3f: /* FRECPX */
- gen_helper_frecpx_f64(tcg_res, tcg_op, fpst);
- break;
- case 0x7d: /* FRSQRTE */
- gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst);
- break;
- default:
- g_assert_not_reached();
- }
- write_vec_element(s, tcg_res, rd, pass, MO_64);
- }
- clear_vec_high(s, !is_scalar, rd);
+ g_assert_not_reached();
} else {
TCGv_i32 tcg_op = tcg_temp_new_i32();
TCGv_i32 tcg_res = tcg_temp_new_i32();
@@ -9532,14 +9545,8 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
gen_helper_recpe_u32(tcg_res, tcg_op);
break;
case 0x3d: /* FRECPE */
- gen_helper_recpe_f32(tcg_res, tcg_op, fpst);
- break;
case 0x3f: /* FRECPX */
- gen_helper_frecpx_f32(tcg_res, tcg_op, fpst);
- break;
case 0x7d: /* FRSQRTE */
- gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst);
- break;
default:
g_assert_not_reached();
}
@@ -9556,76 +9563,6 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
}
}
-/* AdvSIMD scalar two reg misc
- * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
- * +-----+---+-----------+------+-----------+--------+-----+------+------+
- * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
- * +-----+---+-----------+------+-----------+--------+-----+------+------+
- */
-static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
-{
- int rd = extract32(insn, 0, 5);
- int rn = extract32(insn, 5, 5);
- int opcode = extract32(insn, 12, 5);
- int size = extract32(insn, 22, 2);
- bool u = extract32(insn, 29, 1);
-
- switch (opcode) {
- case 0xc ... 0xf:
- case 0x16 ... 0x1d:
- case 0x1f:
- /* Floating point: U, size[1] and opcode indicate operation;
- * size[0] indicates single or double precision.
- */
- opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
- size = extract32(size, 0, 1) ? 3 : 2;
- switch (opcode) {
- case 0x3d: /* FRECPE */
- case 0x3f: /* FRECPX */
- case 0x7d: /* FRSQRTE */
- if (!fp_access_check(s)) {
- return;
- }
- handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd);
- return;
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- case 0x1c: /* FCVTAS */
- case 0x5c: /* FCVTAU */
- case 0x56: /* FCVTXN, FCVTXN2 */
- case 0x1d: /* SCVTF */
- case 0x5d: /* UCVTF */
- case 0x2c: /* FCMGT (zero) */
- case 0x2d: /* FCMEQ (zero) */
- case 0x2e: /* FCMLT (zero) */
- case 0x6c: /* FCMGE (zero) */
- case 0x6d: /* FCMLE (zero) */
- default:
- unallocated_encoding(s);
- return;
- }
- break;
- default:
- case 0x3: /* USQADD / SUQADD */
- case 0x7: /* SQABS / SQNEG */
- case 0x8: /* CMGT, CMGE */
- case 0x9: /* CMEQ, CMLE */
- case 0xa: /* CMLT */
- case 0xb: /* ABS, NEG */
- case 0x12: /* SQXTUN */
- case 0x14: /* SQXTN, UQXTN */
- unallocated_encoding(s);
- return;
- }
- g_assert_not_reached();
-}
-
static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
int size, int rn, int rd)
{
@@ -9705,13 +9642,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
return;
}
- /* fall through */
- case 0x3d: /* FRECPE */
- case 0x7d: /* FRSQRTE */
- if (size == 3 && !is_q) {
- unallocated_encoding(s);
- return;
- }
if (!fp_access_check(s)) {
return;
}
@@ -9764,6 +9694,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x2e: /* FCMLT (zero) */
case 0x6c: /* FCMGE (zero) */
case 0x6d: /* FCMLE (zero) */
+ case 0x3d: /* FRECPE */
+ case 0x7d: /* FRSQRTE */
unallocated_encoding(s);
return;
}
@@ -9859,190 +9791,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
}
-/* AdvSIMD [scalar] two register miscellaneous (FP16)
- *
- * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
- * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
- * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
- * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
- * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
- * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
- *
- * This actually covers two groups where scalar access is governed by
- * bit 28. A bunch of the instructions (float to integral) only exist
- * in the vector form and are un-allocated for the scalar decode. Also
- * in the scalar decode Q is always 1.
- */
-static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
-{
- int fpop, opcode, a, u;
- int rn, rd;
- bool is_q;
- bool is_scalar;
-
- int pass;
- TCGv_i32 tcg_rmode = NULL;
- TCGv_ptr tcg_fpstatus = NULL;
- bool need_fpst = true;
- int rmode = -1;
-
- if (!dc_isar_feature(aa64_fp16, s)) {
- unallocated_encoding(s);
- return;
- }
-
- rd = extract32(insn, 0, 5);
- rn = extract32(insn, 5, 5);
-
- a = extract32(insn, 23, 1);
- u = extract32(insn, 29, 1);
- is_scalar = extract32(insn, 28, 1);
- is_q = extract32(insn, 30, 1);
-
- opcode = extract32(insn, 12, 5);
- fpop = deposit32(opcode, 5, 1, a);
- fpop = deposit32(fpop, 6, 1, u);
-
- switch (fpop) {
- case 0x3d: /* FRECPE */
- case 0x3f: /* FRECPX */
- break;
- case 0x7d: /* FRSQRTE */
- break;
- default:
- case 0x2f: /* FABS */
- case 0x6f: /* FNEG */
- case 0x7f: /* FSQRT (vector) */
- case 0x18: /* FRINTN */
- case 0x19: /* FRINTM */
- case 0x38: /* FRINTP */
- case 0x39: /* FRINTZ */
- case 0x58: /* FRINTA */
- case 0x59: /* FRINTX */
- case 0x79: /* FRINTI */
- case 0x1d: /* SCVTF */
- case 0x5d: /* UCVTF */
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x5c: /* FCVTAU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- case 0x2c: /* FCMGT (zero) */
- case 0x2d: /* FCMEQ (zero) */
- case 0x2e: /* FCMLT (zero) */
- case 0x6c: /* FCMGE (zero) */
- case 0x6d: /* FCMLE (zero) */
- unallocated_encoding(s);
- return;
- }
-
-
- /* Check additional constraints for the scalar encoding */
- if (is_scalar) {
- if (!is_q) {
- unallocated_encoding(s);
- return;
- }
- }
-
- if (!fp_access_check(s)) {
- return;
- }
-
- if (rmode >= 0 || need_fpst) {
- tcg_fpstatus = fpstatus_ptr(FPST_FPCR_F16);
- }
-
- if (rmode >= 0) {
- tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
- }
-
- if (is_scalar) {
- TCGv_i32 tcg_op = read_fp_hreg(s, rn);
- TCGv_i32 tcg_res = tcg_temp_new_i32();
-
- switch (fpop) {
- case 0x3d: /* FRECPE */
- gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
- break;
- case 0x3f: /* FRECPX */
- gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
- break;
- case 0x7d: /* FRSQRTE */
- gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
- break;
- default:
- case 0x6f: /* FNEG */
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x5c: /* FCVTAU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- g_assert_not_reached();
- }
-
- /* limit any sign extension going on */
- tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff);
- write_fp_sreg(s, rd, tcg_res);
- } else {
- for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
- TCGv_i32 tcg_op = tcg_temp_new_i32();
- TCGv_i32 tcg_res = tcg_temp_new_i32();
-
- read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
-
- switch (fpop) {
- case 0x3d: /* FRECPE */
- gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
- break;
- case 0x7d: /* FRSQRTE */
- gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
- break;
- default:
- case 0x2f: /* FABS */
- case 0x6f: /* FNEG */
- case 0x7f: /* FSQRT */
- case 0x18: /* FRINTN */
- case 0x19: /* FRINTM */
- case 0x38: /* FRINTP */
- case 0x39: /* FRINTZ */
- case 0x58: /* FRINTA */
- case 0x79: /* FRINTI */
- case 0x59: /* FRINTX */
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x5c: /* FCVTAU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- g_assert_not_reached();
- }
-
- write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
- }
-
- clear_vec_high(s, is_q, rd);
- }
-
- if (tcg_rmode) {
- gen_restore_rmode(tcg_rmode, tcg_fpstatus);
- }
-}
-
/* C3.6 Data processing - SIMD, inc Crypto
*
* As the decode gets a little complex we are using a table based
@@ -10051,8 +9799,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
static const AArch64DecodeTable data_proc_simd[] = {
/* pattern , mask , fn */
{ 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
- { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
- { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
{ 0x00000000, 0x00000000, NULL }
};
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 640b2726c8..1e6bf15510 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1667,6 +1667,15 @@ FCMLE0_s 0111 1110 1.1 00000 11011 0 ..... ..... @rr_sd
FCMLT0_s 0101 1110 111 11000 11101 0 ..... ..... @rr_h
FCMLT0_s 0101 1110 1.1 00000 11101 0 ..... ..... @rr_sd
+FRECPE_s 0101 1110 111 11001 11011 0 ..... ..... @rr_h
+FRECPE_s 0101 1110 1.1 00001 11011 0 ..... ..... @rr_sd
+
+FRECPX_s 0101 1110 111 11001 11111 0 ..... ..... @rr_h
+FRECPX_s 0101 1110 1.1 00001 11111 0 ..... ..... @rr_sd
+
+FRSQRTE_s 0111 1110 111 11001 11011 0 ..... ..... @rr_h
+FRSQRTE_s 0111 1110 1.1 00001 11011 0 ..... ..... @rr_sd
+
@icvt_h . ....... .. ...... ...... rn:5 rd:5 \
&fcvt sf=0 esz=1 shift=0
@icvt_sd . ....... .. ...... ...... rn:5 rd:5 \
@@ -1848,6 +1857,12 @@ FCMLE0_v 0.10 1110 1.1 00000 11011 0 ..... ..... @qrr_sd
FCMLT0_v 0.00 1110 111 11000 11101 0 ..... ..... @qrr_h
FCMLT0_v 0.00 1110 1.1 00000 11101 0 ..... ..... @qrr_sd
+FRECPE_v 0.00 1110 111 11001 11011 0 ..... ..... @qrr_h
+FRECPE_v 0.00 1110 1.1 00001 11011 0 ..... ..... @qrr_sd
+
+FRSQRTE_v 0.10 1110 111 11001 11011 0 ..... ..... @qrr_h
+FRSQRTE_v 0.10 1110 1.1 00001 11011 0 ..... ..... @qrr_sd
+
&fcvt_q rd rn esz q shift
@fcvtq_h . q:1 . ...... 001 .... ...... rn:5 rd:5 \
&fcvt_q esz=1 shift=%fcvt_f_sh_h
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 65/67] target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (63 preceding siblings ...)
2024-12-01 15:06 ` [PATCH 64/67] target/arm: Convert FRECPE, FRECPX, FRSQRTE " Richard Henderson
@ 2024-12-01 15:06 ` Richard Henderson
2024-12-01 15:06 ` [PATCH 66/67] target/arm: Convert URECPE and URSQRTE to decodetree Richard Henderson
` (2 subsequent siblings)
67 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:06 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.h | 3 +++
target/arm/tcg/translate.h | 5 +++++
target/arm/tcg/gengvec.c | 16 ++++++++++++++++
target/arm/tcg/translate-neon.c | 4 ++--
target/arm/tcg/vec_helper.c | 22 ++++++++++++++++++++++
5 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 1132a5cab6..9919b1367b 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -1121,6 +1121,9 @@ DEF_HELPER_FLAGS_4(gvec_uminp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_uminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_uminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_urecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_ursqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
#ifdef TARGET_AARCH64
#include "tcg/helper-a64.h"
#include "tcg/helper-sve.h"
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index edd775d564..228b195a22 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -602,6 +602,11 @@ void gen_gvec_uaddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
void gen_gvec_uadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_urecpe(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+void gen_gvec_ursqrte(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz);
+
/*
* Forward to the isar_feature_* tests given a DisasContext pointer.
*/
diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c
index 2755da8ac7..a6935a7188 100644
--- a/target/arm/tcg/gengvec.c
+++ b/target/arm/tcg/gengvec.c
@@ -2697,3 +2697,19 @@ void gen_gvec_uadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
assert(vece <= MO_32);
tcg_gen_gvec_2(rd_ofs, rn_ofs, opr_sz, max_sz, &g[vece]);
}
+
+void gen_gvec_urecpe(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ assert(vece == MO_32);
+ tcg_gen_gvec_2_ool(rd_ofs, rn_ofs, opr_sz, max_sz, 0,
+ gen_helper_gvec_urecpe_s);
+}
+
+void gen_gvec_ursqrte(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t opr_sz, uint32_t max_sz)
+{
+ assert(vece == MO_32);
+ tcg_gen_gvec_2_ool(rd_ofs, rn_ofs, opr_sz, max_sz, 0,
+ gen_helper_gvec_ursqrte_s);
+}
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index cea400e1f5..af06c0887b 100644
--- a/target/arm/tcg/translate-neon.c
+++ b/target/arm/tcg/translate-neon.c
@@ -3086,7 +3086,7 @@ static bool trans_VRECPE(DisasContext *s, arg_2misc *a)
if (a->size != 2) {
return false;
}
- return do_2misc(s, a, gen_helper_recpe_u32);
+ return do_2misc_vec(s, a, gen_gvec_urecpe);
}
static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a)
@@ -3094,7 +3094,7 @@ static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a)
if (a->size != 2) {
return false;
}
- return do_2misc(s, a, gen_helper_rsqrte_u32);
+ return do_2misc_vec(s, a, gen_gvec_ursqrte);
}
#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 0f4b5670f3..c824e8307b 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -3105,3 +3105,25 @@ void HELPER(gvec_rbit_b)(void *vd, void *vn, uint32_t desc)
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
+
+void HELPER(gvec_urecpe_s)(void *vd, void *vn, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ uint32_t *d = vd, *n = vn;
+
+ for (i = 0; i < opr_sz / 4; ++i) {
+ d[i] = helper_recpe_u32(n[i]);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_ursqrte_s)(void *vd, void *vn, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ uint32_t *d = vd, *n = vn;
+
+ for (i = 0; i < opr_sz / 4; ++i) {
+ d[i] = helper_rsqrte_u32(n[i]);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 66/67] target/arm: Convert URECPE and URSQRTE to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (64 preceding siblings ...)
2024-12-01 15:06 ` [PATCH 65/67] target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte Richard Henderson
@ 2024-12-01 15:06 ` Richard Henderson
2024-12-01 15:06 ` [PATCH 67/67] target/arm: Convert FCVTL " Richard Henderson
2024-12-09 10:29 ` [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Peter Maydell
67 siblings, 0 replies; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:06 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove handle_2misc_reciprocal as these were the last
insns decoded by that function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 139 ++-------------------------------
target/arm/tcg/a64.decode | 3 +
2 files changed, 8 insertions(+), 134 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index c60e9a35cf..78ad72061d 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -9167,6 +9167,8 @@ TRANS(CMLE0_v, do_gvec_fn2, a, gen_gvec_cle0)
TRANS(CMEQ0_v, do_gvec_fn2, a, gen_gvec_ceq0)
TRANS(REV16_v, do_gvec_fn2, a, gen_gvec_rev16)
TRANS(REV32_v, do_gvec_fn2, a, gen_gvec_rev32)
+TRANS(URECPE_v, do_gvec_fn2, a, gen_gvec_urecpe)
+TRANS(URSQRTE_v, do_gvec_fn2, a, gen_gvec_ursqrte)
static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
@@ -9518,51 +9520,6 @@ static gen_helper_gvec_2_ptr * const f_frsqrte[] = {
};
TRANS(FRSQRTE_v, do_gvec_op2_fpst, a->esz, a->q, a->rd, a->rn, 0, f_frsqrte)
-static void handle_2misc_reciprocal(DisasContext *s, int opcode,
- bool is_scalar, bool is_u, bool is_q,
- int size, int rn, int rd)
-{
- bool is_double = (size == 3);
-
- if (is_double) {
- g_assert_not_reached();
- } else {
- TCGv_i32 tcg_op = tcg_temp_new_i32();
- TCGv_i32 tcg_res = tcg_temp_new_i32();
- int pass, maxpasses;
-
- if (is_scalar) {
- maxpasses = 1;
- } else {
- maxpasses = is_q ? 4 : 2;
- }
-
- for (pass = 0; pass < maxpasses; pass++) {
- read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
-
- switch (opcode) {
- case 0x3c: /* URECPE */
- gen_helper_recpe_u32(tcg_res, tcg_op);
- break;
- case 0x3d: /* FRECPE */
- case 0x3f: /* FRECPX */
- case 0x7d: /* FRSQRTE */
- default:
- g_assert_not_reached();
- }
-
- if (is_scalar) {
- write_fp_sreg(s, rd, tcg_res);
- } else {
- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
- }
- }
- if (!is_scalar) {
- clear_vec_high(s, is_q, rd);
- }
- }
-}
-
static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
int size, int rn, int rd)
{
@@ -9621,10 +9578,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
bool is_q = extract32(insn, 30, 1);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
- bool need_fpstatus = false;
- int rmode = -1;
- TCGv_i32 tcg_rmode;
- TCGv_ptr tcg_fpstatus;
switch (opcode) {
case 0xc ... 0xf:
@@ -9637,28 +9590,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
size = is_double ? 3 : 2;
switch (opcode) {
- case 0x3c: /* URECPE */
- if (size == 3) {
- unallocated_encoding(s);
- return;
- }
- if (!fp_access_check(s)) {
- return;
- }
- handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd);
- return;
case 0x17: /* FCVTL, FCVTL2 */
if (!fp_access_check(s)) {
return;
}
handle_2misc_widening(s, opcode, is_q, size, rn, rd);
return;
- case 0x7c: /* URSQRTE */
- if (size == 3) {
- unallocated_encoding(s);
- return;
- }
- break;
default:
case 0x16: /* FCVTN, FCVTN2 */
case 0x36: /* BFCVTN, BFCVTN2 */
@@ -9696,6 +9633,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x6d: /* FCMLE (zero) */
case 0x3d: /* FRECPE */
case 0x7d: /* FRSQRTE */
+ case 0x3c: /* URECPE */
+ case 0x7c: /* URSQRTE */
unallocated_encoding(s);
return;
}
@@ -9720,75 +9659,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
return;
}
-
- if (!fp_access_check(s)) {
- return;
- }
-
- if (need_fpstatus || rmode >= 0) {
- tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
- } else {
- tcg_fpstatus = NULL;
- }
- if (rmode >= 0) {
- tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
- } else {
- tcg_rmode = NULL;
- }
-
- {
- int pass;
-
- assert(size == 2);
- for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
- TCGv_i32 tcg_op = tcg_temp_new_i32();
- TCGv_i32 tcg_res = tcg_temp_new_i32();
-
- read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
-
- {
- /* Special cases for 32 bit elements */
- switch (opcode) {
- case 0x7c: /* URSQRTE */
- gen_helper_rsqrte_u32(tcg_res, tcg_op);
- break;
- default:
- case 0x7: /* SQABS, SQNEG */
- case 0x2f: /* FABS */
- case 0x6f: /* FNEG */
- case 0x7f: /* FSQRT */
- case 0x18: /* FRINTN */
- case 0x19: /* FRINTM */
- case 0x38: /* FRINTP */
- case 0x39: /* FRINTZ */
- case 0x58: /* FRINTA */
- case 0x79: /* FRINTI */
- case 0x59: /* FRINTX */
- case 0x1e: /* FRINT32Z */
- case 0x5e: /* FRINT32X */
- case 0x1f: /* FRINT64Z */
- case 0x5f: /* FRINT64X */
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x5c: /* FCVTAU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- g_assert_not_reached();
- }
- }
- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
- }
- }
- clear_vec_high(s, is_q, rd);
-
- if (tcg_rmode) {
- gen_restore_rmode(tcg_rmode, tcg_fpstatus);
- }
+ g_assert_not_reached();
}
/* C3.6 Data processing - SIMD, inc Crypto
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 1e6bf15510..5090b857e6 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1863,6 +1863,9 @@ FRECPE_v 0.00 1110 1.1 00001 11011 0 ..... ..... @qrr_sd
FRSQRTE_v 0.10 1110 111 11001 11011 0 ..... ..... @qrr_h
FRSQRTE_v 0.10 1110 1.1 00001 11011 0 ..... ..... @qrr_sd
+URECPE_v 0.00 1110 101 00001 11001 0 ..... ..... @qrr_s
+URSQRTE_v 0.10 1110 101 00001 11001 0 ..... ..... @qrr_s
+
&fcvt_q rd rn esz q shift
@fcvtq_h . q:1 . ...... 001 .... ...... rn:5 rd:5 \
&fcvt_q esz=1 shift=%fcvt_f_sh_h
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* [PATCH 67/67] target/arm: Convert FCVTL to decodetree
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (65 preceding siblings ...)
2024-12-01 15:06 ` [PATCH 66/67] target/arm: Convert URECPE and URSQRTE to decodetree Richard Henderson
@ 2024-12-01 15:06 ` Richard Henderson
2024-12-06 16:33 ` Peter Maydell
2024-12-09 10:29 ` [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Peter Maydell
67 siblings, 1 reply; 147+ messages in thread
From: Richard Henderson @ 2024-12-01 15:06 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Remove lookup_disas_fn, handle_2misc_widening,
disas_simd_two_reg_misc, disas_data_proc_simd,
disas_data_proc_simd_fp, disas_a64_legacy, as
this is the final insn to be converted.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 202 +++------------------------------
target/arm/tcg/a64.decode | 2 +
2 files changed, 18 insertions(+), 186 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 78ad72061d..8f93fc2737 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1465,31 +1465,6 @@ static inline void gen_check_sp_alignment(DisasContext *s)
*/
}
-/*
- * This provides a simple table based table lookup decoder. It is
- * intended to be used when the relevant bits for decode are too
- * awkwardly placed and switch/if based logic would be confusing and
- * deeply nested. Since it's a linear search through the table, tables
- * should be kept small.
- *
- * It returns the first handler where insn & mask == pattern, or
- * NULL if there is no match.
- * The table is terminated by an empty mask (i.e. 0)
- */
-static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
- uint32_t insn)
-{
- const AArch64DecodeTable *tptr = table;
-
- while (tptr->mask) {
- if ((insn & tptr->mask) == tptr->pattern) {
- return tptr->disas_fn;
- }
- tptr++;
- }
- return NULL;
-}
-
/*
* The instruction disassembly implemented here matches
* the instruction encoding classifications in chapter C4
@@ -9520,8 +9495,7 @@ static gen_helper_gvec_2_ptr * const f_frsqrte[] = {
};
TRANS(FRSQRTE_v, do_gvec_op2_fpst, a->esz, a->q, a->rd, a->rn, 0, f_frsqrte)
-static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
- int size, int rn, int rd)
+static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
{
/* Handle 2-reg-misc ops which are widening (so each size element
* in the source becomes a 2*size element in the destination.
@@ -9529,173 +9503,43 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
*/
int pass;
- if (size == 3) {
+ if (!fp_access_check(s)) {
+ return true;
+ }
+
+ if (a->esz == MO_64) {
/* 32 -> 64 bit fp conversion */
TCGv_i64 tcg_res[2];
- int srcelt = is_q ? 2 : 0;
+ TCGv_i32 tcg_op = tcg_temp_new_i32();
+ int srcelt = a->q ? 2 : 0;
for (pass = 0; pass < 2; pass++) {
- TCGv_i32 tcg_op = tcg_temp_new_i32();
tcg_res[pass] = tcg_temp_new_i64();
-
- read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32);
+ read_vec_element_i32(s, tcg_op, a->rn, srcelt + pass, MO_32);
gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, tcg_env);
}
for (pass = 0; pass < 2; pass++) {
- write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
+ write_vec_element(s, tcg_res[pass], a->rd, pass, MO_64);
}
} else {
/* 16 -> 32 bit fp conversion */
- int srcelt = is_q ? 4 : 0;
+ int srcelt = a->q ? 4 : 0;
TCGv_i32 tcg_res[4];
TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
TCGv_i32 ahp = get_ahp_flag();
for (pass = 0; pass < 4; pass++) {
tcg_res[pass] = tcg_temp_new_i32();
-
- read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16);
+ read_vec_element_i32(s, tcg_res[pass], a->rn, srcelt + pass, MO_16);
gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass],
fpst, ahp);
}
for (pass = 0; pass < 4; pass++) {
- write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
+ write_vec_element_i32(s, tcg_res[pass], a->rd, pass, MO_32);
}
}
-}
-
-/* AdvSIMD two reg misc
- * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
- * +---+---+---+-----------+------+-----------+--------+-----+------+------+
- * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
- * +---+---+---+-----------+------+-----------+--------+-----+------+------+
- */
-static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
-{
- int size = extract32(insn, 22, 2);
- int opcode = extract32(insn, 12, 5);
- bool u = extract32(insn, 29, 1);
- bool is_q = extract32(insn, 30, 1);
- int rn = extract32(insn, 5, 5);
- int rd = extract32(insn, 0, 5);
-
- switch (opcode) {
- case 0xc ... 0xf:
- case 0x16 ... 0x1f:
- {
- /* Floating point: U, size[1] and opcode indicate operation;
- * size[0] indicates single or double precision.
- */
- int is_double = extract32(size, 0, 1);
- opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
- size = is_double ? 3 : 2;
- switch (opcode) {
- case 0x17: /* FCVTL, FCVTL2 */
- if (!fp_access_check(s)) {
- return;
- }
- handle_2misc_widening(s, opcode, is_q, size, rn, rd);
- return;
- default:
- case 0x16: /* FCVTN, FCVTN2 */
- case 0x36: /* BFCVTN, BFCVTN2 */
- case 0x56: /* FCVTXN, FCVTXN2 */
- case 0x2f: /* FABS */
- case 0x6f: /* FNEG */
- case 0x7f: /* FSQRT */
- case 0x18: /* FRINTN */
- case 0x19: /* FRINTM */
- case 0x38: /* FRINTP */
- case 0x39: /* FRINTZ */
- case 0x59: /* FRINTX */
- case 0x79: /* FRINTI */
- case 0x58: /* FRINTA */
- case 0x1e: /* FRINT32Z */
- case 0x1f: /* FRINT64Z */
- case 0x5e: /* FRINT32X */
- case 0x5f: /* FRINT64X */
- case 0x1d: /* SCVTF */
- case 0x5d: /* UCVTF */
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- case 0x5c: /* FCVTAU */
- case 0x1c: /* FCVTAS */
- case 0x2c: /* FCMGT (zero) */
- case 0x2d: /* FCMEQ (zero) */
- case 0x2e: /* FCMLT (zero) */
- case 0x6c: /* FCMGE (zero) */
- case 0x6d: /* FCMLE (zero) */
- case 0x3d: /* FRECPE */
- case 0x7d: /* FRSQRTE */
- case 0x3c: /* URECPE */
- case 0x7c: /* URSQRTE */
- unallocated_encoding(s);
- return;
- }
- break;
- }
- default:
- case 0x0: /* REV64 */
- case 0x1: /* REV16, REV32 */
- case 0x2: /* SADDLP, UADDLP */
- case 0x3: /* SUQADD, USQADD */
- case 0x4: /* CLS, CLZ */
- case 0x5: /* CNT, NOT, RBIT */
- case 0x6: /* SADALP, UADALP */
- case 0x7: /* SQABS, SQNEG */
- case 0x8: /* CMGT, CMGE */
- case 0x9: /* CMEQ, CMLE */
- case 0xa: /* CMLT */
- case 0xb: /* ABS, NEG */
- case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
- case 0x13: /* SHLL, SHLL2 */
- case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
- unallocated_encoding(s);
- return;
- }
- g_assert_not_reached();
-}
-
-/* C3.6 Data processing - SIMD, inc Crypto
- *
- * As the decode gets a little complex we are using a table based
- * approach for this part of the decode.
- */
-static const AArch64DecodeTable data_proc_simd[] = {
- /* pattern , mask , fn */
- { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
- { 0x00000000, 0x00000000, NULL }
-};
-
-static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
-{
- /* Note that this is called with all non-FP cases from
- * table C3-6 so it must UNDEF for entries not specifically
- * allocated to instructions in that table.
- */
- AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn);
- if (fn) {
- fn(s, insn);
- } else {
- unallocated_encoding(s);
- }
-}
-
-/* C3.6 Data processing - SIMD and floating point */
-static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
-{
- if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) {
- unallocated_encoding(s); /* in decodetree */
- } else {
- /* SIMD, including crypto */
- disas_data_proc_simd(s, insn);
- }
+ clear_vec_high(s, true, a->rd);
+ return true;
}
static bool trans_OK(DisasContext *s, arg_OK *a)
@@ -9761,20 +9605,6 @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype)
return false;
}
-/* C3.1 A64 instruction index by encoding */
-static void disas_a64_legacy(DisasContext *s, uint32_t insn)
-{
- switch (extract32(insn, 25, 4)) {
- case 0x7:
- case 0xf: /* Data processing - SIMD and floating point */
- disas_data_proc_simd_fp(s, insn);
- break;
- default:
- unallocated_encoding(s);
- break;
- }
-}
-
static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
CPUState *cpu)
{
@@ -9977,7 +9807,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
if (!disas_a64(s, insn) &&
!disas_sme(s, insn) &&
!disas_sve(s, insn)) {
- disas_a64_legacy(s, insn);
+ unallocated_encoding(s);
}
/*
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 5090b857e6..47ca635315 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1866,6 +1866,8 @@ FRSQRTE_v 0.10 1110 1.1 00001 11011 0 ..... ..... @qrr_sd
URECPE_v 0.00 1110 101 00001 11001 0 ..... ..... @qrr_s
URSQRTE_v 0.10 1110 101 00001 11001 0 ..... ..... @qrr_s
+FCVTL_v 0.00 1110 0.1 00001 01111 0 ..... ..... @qrr_sd
+
&fcvt_q rd rn esz q shift
@fcvtq_h . q:1 . ...... 001 .... ...... rn:5 rd:5 \
&fcvt_q esz=1 shift=%fcvt_f_sh_h
--
2.43.0
^ permalink raw reply related [flat|nested] 147+ messages in thread* Re: [PATCH 67/67] target/arm: Convert FCVTL to decodetree
2024-12-01 15:06 ` [PATCH 67/67] target/arm: Convert FCVTL " Richard Henderson
@ 2024-12-06 16:33 ` Peter Maydell
0 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-06 16:33 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:17, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Remove lookup_disas_fn, handle_2misc_widening,
> disas_simd_two_reg_misc, disas_data_proc_simd,
> disas_data_proc_simd_fp, disas_a64_legacy, as
> this is the final insn to be converted.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread
* Re: [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part
2024-12-01 15:04 [PATCH 00/67] target/arm: AArch64 decodetree conversion, final part Richard Henderson
` (66 preceding siblings ...)
2024-12-01 15:06 ` [PATCH 67/67] target/arm: Convert FCVTL " Richard Henderson
@ 2024-12-09 10:29 ` Peter Maydell
67 siblings, 0 replies; 147+ messages in thread
From: Peter Maydell @ 2024-12-09 10:29 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, qemu-arm
On Sun, 1 Dec 2024 at 15:18, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Finish the conversion of all aarch64 instructions to decodetree.
>
I've reviewed most of this now; I'll review anything I
skipped here in the v2.
thanks
-- PMM
^ permalink raw reply [flat|nested] 147+ messages in thread