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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434d52c0cfdsm36598115e9.33.2024.12.04.12.28.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Dec 2024 12:28:08 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , "Michael S. Tsirkin" , Peter Maydell , Laurent Vivier , Mark Cave-Ayland , Alistair Francis , Anton Johansson , Zhao Liu , "Edgar E. Iglesias" , David Hildenbrand , qemu-s390x@nongnu.org, Max Filippov , Paolo Bonzini , Nicholas Piggin , qemu-arm@nongnu.org, Thomas Huth , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 16/20] hw/core/cpu: Expose cpu_datapath_is_big_endian() method Date: Wed, 4 Dec 2024 21:25:58 +0100 Message-ID: <20241204202602.58083-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241204202602.58083-1-philmd@linaro.org> References: <20241204202602.58083-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All target implement their CPUClass::datapath_is_big_endian() helper, we can expose the generic cpu_datapath_is_big_endian() method. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 8 ++++++++ hw/core/cpu-common.c | 7 +++++++ 2 files changed, 15 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 91c6581f814..5c75fe3a842 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -611,6 +611,14 @@ extern __thread CPUState *current_cpu; extern bool mttcg_enabled; #define qemu_tcg_mttcg_enabled() (mttcg_enabled) +/** + * cpu_datapath_is_big_endian: + * @cpu: The CPU whose state is to be inspected. + * + * Returns: %true if the CPU access data in big endian order, %false otherwise. + */ +bool cpu_datapath_is_big_endian(CPUState *cpu); + /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 09c79035949..92c0c4c6125 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -66,6 +66,13 @@ CPUState *cpu_create(const char *typename) return cpu; } +bool cpu_datapath_is_big_endian(CPUState *cpu) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + + return cc->datapath_is_big_endian(cpu); +} + /* Resetting the IRQ comes from across the code base so we take the * BQL here if we need to. cpu_interrupt assumes it is held.*/ void cpu_reset_interrupt(CPUState *cpu, int mask) -- 2.45.2