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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385e49cd788sm13643172f8f.6.2024.12.04.12.27.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Dec 2024 12:27:19 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , "Michael S. Tsirkin" , Peter Maydell , Laurent Vivier , Mark Cave-Ayland , Alistair Francis , Anton Johansson , Zhao Liu , "Edgar E. Iglesias" , David Hildenbrand , qemu-s390x@nongnu.org, Max Filippov , Paolo Bonzini , Nicholas Piggin , qemu-arm@nongnu.org, Thomas Huth , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 07/20] target/riscv: Implement CPUClass::datapath_is_big_endian Date: Wed, 4 Dec 2024 21:25:49 +0100 Message-ID: <20241204202602.58083-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241204202602.58083-1-philmd@linaro.org> References: <20241204202602.58083-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org While the RISC-V data endianness can be changed at runtime, we do not implement that. The current translation code assumes little-endian memory accesses (See commit a2f827ff4f4 "target/riscv: accessors to registers upper part and 128-bit load/store"). Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b52..b31b9b3471d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -60,6 +60,22 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu) return riscv_cpu_mxl(&cpu->env) == MXL_RV32; } +static bool riscv_cpu_datapath_is_big_endian(CPUState *cs) +{ +#ifndef CONFIG_USER_ONLY + /* + * A couple of bits in MSTATUS set the endianness: + * - MSTATUS_UBE (User-mode), + * - MSTATUS_SBE (Supervisor-mode), + * - MSTATUS_MBE (Machine-mode) + * but we don't implement that yet. + */ + return false; +#else + return false; +#endif +} + /* Hash that stores general user set numeric options */ static GHashTable *general_user_opts; @@ -2764,6 +2780,7 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = riscv_cpu_class_by_name; + cc->datapath_is_big_endian = riscv_cpu_datapath_is_big_endian; cc->has_work = riscv_cpu_has_work; cc->mmu_index = riscv_cpu_mmu_index; cc->dump_state = riscv_cpu_dump_state; -- 2.45.2