From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Hervé Poussineau" <hpoussin@reactos.org>,
"Aleksandar Rikalo" <arikalo@gmail.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Bernhard Beschow" <shentey@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 1/6] hw/pci-host/bonito: Expose output IRQ as QDev GPIO
Date: Tue, 21 Jan 2025 17:18:12 +0100 [thread overview]
Message-ID: <20250121161817.33654-2-philmd@linaro.org> (raw)
In-Reply-To: <20250121161817.33654-1-philmd@linaro.org>
Expose IRQ using qdev_init_gpio_out() in bonito_host_realize(),
wire it using qdev_connect_gpio_out() in bonito_init().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/mips/mips.h | 2 +-
hw/mips/fuloong2e.c | 2 +-
hw/pci-host/bonito.c | 14 +++++++-------
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h
index 101799f7d3e..1176291cca6 100644
--- a/include/hw/mips/mips.h
+++ b/include/hw/mips/mips.h
@@ -10,7 +10,7 @@
#include "exec/memory.h"
/* bonito.c */
-PCIBus *bonito_init(qemu_irq *pic);
+PCIBus *bonito_init(qemu_irq irq);
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 16b6a5129e7..160ceb769dc 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -282,7 +282,7 @@ static void mips_fuloong2e_init(MachineState *machine)
cpu_mips_clock_init(cpu);
/* North bridge, Bonito --> IP2 */
- pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));
+ pci_bus = bonito_init(env->irq[2]);
/* South bridge -> IP5 */
pci_dev = pci_new_multifunction(PCI_DEVFN(FULOONG2E_VIA_SLOT, 0),
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 49669148923..6bc66c9e227 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -234,7 +234,7 @@ typedef struct PCIBonitoState PCIBonitoState;
struct BonitoState {
PCIHostState parent_obj;
- qemu_irq *pic;
+ qemu_irq irq;
PCIBonitoState *pci_dev;
MemoryRegion pci_mem;
};
@@ -554,17 +554,16 @@ static const MemoryRegionOps bonito_spciconf_ops = {
static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
{
BonitoState *s = opaque;
- qemu_irq *pic = s->pic;
PCIBonitoState *bonito_state = s->pci_dev;
int internal_irq = irq_num - BONITO_IRQ_BASE;
if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
- qemu_irq_pulse(*pic);
+ qemu_irq_pulse(s->irq);
} else { /* level triggered */
if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
- qemu_irq_raise(*pic);
+ qemu_irq_raise(s->irq);
} else {
- qemu_irq_lower(*pic);
+ qemu_irq_lower(s->irq);
}
}
}
@@ -631,6 +630,7 @@ static void bonito_host_realize(DeviceState *dev, Error **errp)
BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
+ qdev_init_gpio_out(dev, &bs->irq, 1);
memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
phb->bus = pci_register_root_bus(dev, "pci",
pci_bonito_set_irq, pci_bonito_map_irq,
@@ -734,7 +734,7 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
}
-PCIBus *bonito_init(qemu_irq *pic)
+PCIBus *bonito_init(qemu_irq irq)
{
DeviceState *dev;
BonitoState *pcihost;
@@ -745,8 +745,8 @@ PCIBus *bonito_init(qemu_irq *pic)
dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE);
phb = PCI_HOST_BRIDGE(dev);
pcihost = BONITO_PCI_HOST_BRIDGE(dev);
- pcihost->pic = pic;
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ qdev_connect_gpio_out(dev, 0, irq);
d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
s = PCI_BONITO(d);
--
2.47.1
next prev parent reply other threads:[~2025-01-21 16:18 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-21 16:18 [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
2025-01-21 16:18 ` Philippe Mathieu-Daudé [this message]
2025-01-21 16:18 ` [PATCH 2/6] target/mips: Create clock *after* accelerator vCPU is realized Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize Philippe Mathieu-Daudé
2025-01-21 23:07 ` Richard Henderson
2025-01-21 16:18 ` [PATCH 4/6] target/mips: Pass env to cpu_mips_clock_init() Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 5/6] target/mips: Move CPU timer from hw/mips/ to target/mips/system/ Philippe Mathieu-Daudé
2025-01-21 23:08 ` Richard Henderson
2025-01-21 16:18 ` [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState Philippe Mathieu-Daudé
2025-01-21 16:20 ` Philippe Mathieu-Daudé
2025-01-21 23:12 ` Richard Henderson
2025-01-21 16:42 ` [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
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