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From: "Cédric Le Goater" <clg@redhat.com>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Joel Stanley" <joel@jms.id.au>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Troy Lee" <troy_lee@aspeedtech.com>,
	"Jamin Lin" <jamin_lin@aspeedtech.com>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Kenneth Jia" <kenneth_jia@asus.com>,
	"Cédric Le Goater" <clg@redhat.com>
Subject: [PATCH 1/9] hw/arm/aspeed: fix connect_serial_hds_to_uarts
Date: Wed, 22 Jan 2025 08:09:01 +0100	[thread overview]
Message-ID: <20250122070909.1138598-2-clg@redhat.com> (raw)
In-Reply-To: <20250122070909.1138598-1-clg@redhat.com>

From: Kenneth Jia <kenneth_jia@asus.com>

In the loop, we need ignore the index increase when uart == uart_chosen
We should increase the index only after we allocate a serial.

Signed-off-by: Kenneth Jia <kenneth_jia@asus.com>
Fixes: d2b3eaefb4d7 ("aspeed: Refactor UART init for multi-SoC machines")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/5f9b0c53f1644922ba85522046e92f4c@asus.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 hw/arm/aspeed.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index a18d4ed1fb10..2662465ada4f 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -364,11 +364,11 @@ static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
 
     aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0));
-    for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
+    for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) {
         if (uart == uart_chosen) {
             continue;
         }
-        aspeed_soc_uart_set_chr(s, uart, serial_hd(i));
+        aspeed_soc_uart_set_chr(s, uart, serial_hd(i++));
     }
 }
 
-- 
2.48.1



  reply	other threads:[~2025-01-22  7:09 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-22  7:09 [PATCH 0/9] aspeed: pre-PR for QEMU 10.0 (RESEND) Cédric Le Goater
2025-01-22  7:09 ` Cédric Le Goater [this message]
2025-01-22  7:09 ` [PATCH 2/9] hw/sd/sdhci: Introduce a new Write Protected pin inverted property Cédric Le Goater
2025-01-22  7:09 ` [PATCH 3/9] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB Cédric Le Goater
2025-01-22  7:09 ` [PATCH 4/9] hw/timer/aspeed: Refactor Timer Callbacks for SoC-Specific Implementations Cédric Le Goater
2025-01-22  7:09 ` [PATCH 5/9] hw/timer/aspeed: Add AST2700 Support Cédric Le Goater
2025-01-22  7:09 ` [PATCH 6/9] aspeed/soc: Support Timer for AST2700 Cédric Le Goater
2025-01-22  7:09 ` [PATCH 7/9] test/functional: Update the Aspeed aarch64 test Cédric Le Goater
2025-01-22  7:28   ` Jamin Lin
2025-01-22  7:37     ` Cédric Le Goater
2025-01-22  7:09 ` [PATCH 8/9] test/functional: Update buildroot images to 2024.11 Cédric Le Goater
2025-01-22  7:35   ` Jamin Lin
2025-01-22  7:09 ` [PATCH 9/9] aspeed: Create sd devices only when defaults are enabled Cédric Le Goater
2025-01-22  7:38   ` Jamin Lin
2025-01-22  9:05   ` Philippe Mathieu-Daudé

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