* [PATCH v2 01/10] hw/core/generic-loader: Do not open-code cpu_set_pc()
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
@ 2025-01-22 9:30 ` Philippe Mathieu-Daudé
2025-01-24 19:25 ` Richard Henderson
2025-01-22 9:30 ` [PATCH v2 02/10] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Philippe Mathieu-Daudé
` (9 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:30 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Richard Henderson, Alex Bennée,
Philippe Mathieu-Daudé
Directly call cpu_set_pc() instead of open-coding it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/core/generic-loader.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
index fb354693aff..1b9ab600c9c 100644
--- a/hw/core/generic-loader.c
+++ b/hw/core/generic-loader.c
@@ -48,11 +48,8 @@ static void generic_loader_reset(void *opaque)
GenericLoaderState *s = GENERIC_LOADER(opaque);
if (s->set_pc) {
- CPUClass *cc = CPU_GET_CLASS(s->cpu);
cpu_reset(s->cpu);
- if (cc) {
- cc->set_pc(s->cpu, s->addr);
- }
+ cpu_set_pc(s->cpu, s->addr);
}
if (s->data_len) {
--
2.47.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 01/10] hw/core/generic-loader: Do not open-code cpu_set_pc()
2025-01-22 9:30 ` [PATCH v2 01/10] hw/core/generic-loader: Do not open-code cpu_set_pc() Philippe Mathieu-Daudé
@ 2025-01-24 19:25 ` Richard Henderson
0 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2025-01-24 19:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: qemu-arm, Alex Bennée
On 1/22/25 01:30, Philippe Mathieu-Daudé wrote:
> Directly call cpu_set_pc() instead of open-coding it.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/core/generic-loader.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
> index fb354693aff..1b9ab600c9c 100644
> --- a/hw/core/generic-loader.c
> +++ b/hw/core/generic-loader.c
> @@ -48,11 +48,8 @@ static void generic_loader_reset(void *opaque)
> GenericLoaderState *s = GENERIC_LOADER(opaque);
>
> if (s->set_pc) {
> - CPUClass *cc = CPU_GET_CLASS(s->cpu);
> cpu_reset(s->cpu);
> - if (cc) {
> - cc->set_pc(s->cpu, s->addr);
> - }
> + cpu_set_pc(s->cpu, s->addr);
> }
>
> if (s->data_len) {
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 02/10] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
2025-01-22 9:30 ` [PATCH v2 01/10] hw/core/generic-loader: Do not open-code cpu_set_pc() Philippe Mathieu-Daudé
@ 2025-01-22 9:30 ` Philippe Mathieu-Daudé
2025-01-22 9:32 ` Philippe Mathieu-Daudé
2025-01-22 20:55 ` Alex Bennée
2025-01-22 9:30 ` [PATCH v2 03/10] cpus: Cache CPUClass early in instance_init() handler Philippe Mathieu-Daudé
` (8 subsequent siblings)
10 siblings, 2 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:30 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Richard Henderson, Alex Bennée,
Philippe Mathieu-Daudé
Both CPUClass::gdb_read_register() and CPUClass::gdb_write_register()
handlers are called from common gdbstub code, and won't be called with
register index over CPUClass::gdb_num_core_regs:
int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (reg < cc->gdb_num_core_regs) {
return cc->gdb_read_register(cpu, buf, reg);
}
...
}
static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (reg < cc->gdb_num_core_regs) {
return cc->gdb_write_register(cpu, mem_buf, reg);
}
...
}
Clarify that in CPUClass docstring, and remove unreachable code on
the microblaze and tricore implementations.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/core/cpu.h | 2 ++
target/microblaze/gdbstub.c | 5 -----
target/openrisc/gdbstub.c | 5 -----
3 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index fb397cdfc53..7b6b22c431b 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -124,7 +124,9 @@ struct SysemuCPUOps;
* @get_pc: Callback for getting the Program Counter register.
* As above, with the semantics of the target architecture.
* @gdb_read_register: Callback for letting GDB read a register.
+ * No more than @gdb_num_core_regs registers can be read.
* @gdb_write_register: Callback for letting GDB write a register.
+ * No more than @gdb_num_core_regs registers can be written.
* @gdb_adjust_breakpoint: Callback for adjusting the address of a
* breakpoint. Used by AVR to handle a gdb mis-feature with
* its Harvard architecture split code and data.
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 09d74e164d0..d493681d38d 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -110,14 +110,9 @@ int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n)
int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- CPUClass *cc = CPU_GET_CLASS(cs);
CPUMBState *env = cpu_env(cs);
uint32_t tmp;
- if (n > cc->gdb_num_core_regs) {
- return 0;
- }
-
tmp = ldl_p(mem_buf);
switch (n) {
diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c
index c2a77d5d4d5..45bba80d878 100644
--- a/target/openrisc/gdbstub.c
+++ b/target/openrisc/gdbstub.c
@@ -47,14 +47,9 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- CPUClass *cc = CPU_GET_CLASS(cs);
CPUOpenRISCState *env = cpu_env(cs);
uint32_t tmp;
- if (n > cc->gdb_num_core_regs) {
- return 0;
- }
-
tmp = ldl_p(mem_buf);
if (n < 32) {
--
2.47.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 02/10] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed
2025-01-22 9:30 ` [PATCH v2 02/10] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Philippe Mathieu-Daudé
@ 2025-01-22 9:32 ` Philippe Mathieu-Daudé
2025-01-22 20:55 ` Alex Bennée
1 sibling, 0 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:32 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Richard Henderson, Alex Bennée
On 22/1/25 10:30, Philippe Mathieu-Daudé wrote:
> Both CPUClass::gdb_read_register() and CPUClass::gdb_write_register()
> handlers are called from common gdbstub code, and won't be called with
> register index over CPUClass::gdb_num_core_regs:
>
> int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
> {
> CPUClass *cc = CPU_GET_CLASS(cpu);
>
> if (reg < cc->gdb_num_core_regs) {
> return cc->gdb_read_register(cpu, buf, reg);
> }
> ...
> }
>
> static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
> {
> CPUClass *cc = CPU_GET_CLASS(cpu);
>
> if (reg < cc->gdb_num_core_regs) {
> return cc->gdb_write_register(cpu, mem_buf, reg);
> }
> ...
> }
>
> Clarify that in CPUClass docstring, and remove unreachable code on
> the microblaze and tricore implementations.
s/tricore/openrisc/ 🤦
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/hw/core/cpu.h | 2 ++
> target/microblaze/gdbstub.c | 5 -----
> target/openrisc/gdbstub.c | 5 -----
> 3 files changed, 2 insertions(+), 10 deletions(-)
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 02/10] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed
2025-01-22 9:30 ` [PATCH v2 02/10] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Philippe Mathieu-Daudé
2025-01-22 9:32 ` Philippe Mathieu-Daudé
@ 2025-01-22 20:55 ` Alex Bennée
1 sibling, 0 replies; 16+ messages in thread
From: Alex Bennée @ 2025-01-22 20:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel, qemu-arm, Richard Henderson
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> Both CPUClass::gdb_read_register() and CPUClass::gdb_write_register()
> handlers are called from common gdbstub code, and won't be called with
> register index over CPUClass::gdb_num_core_regs:
>
> int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
> {
> CPUClass *cc = CPU_GET_CLASS(cpu);
>
> if (reg < cc->gdb_num_core_regs) {
> return cc->gdb_read_register(cpu, buf, reg);
> }
> ...
> }
>
> static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
> {
> CPUClass *cc = CPU_GET_CLASS(cpu);
>
> if (reg < cc->gdb_num_core_regs) {
> return cc->gdb_write_register(cpu, mem_buf, reg);
> }
> ...
> }
>
> Clarify that in CPUClass docstring, and remove unreachable code on
> the microblaze and tricore implementations.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 03/10] cpus: Cache CPUClass early in instance_init() handler
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
2025-01-22 9:30 ` [PATCH v2 01/10] hw/core/generic-loader: Do not open-code cpu_set_pc() Philippe Mathieu-Daudé
2025-01-22 9:30 ` [PATCH v2 02/10] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Philippe Mathieu-Daudé
@ 2025-01-22 9:30 ` Philippe Mathieu-Daudé
2025-01-22 9:30 ` [PATCH v2 04/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
` (7 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:30 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Richard Henderson, Alex Bennée,
Philippe Mathieu-Daudé
Cache CPUClass as early as possible, when the instance
is initialized.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
cpu-target.c | 3 ---
hw/core/cpu-common.c | 3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/cpu-target.c b/cpu-target.c
index 667688332c9..89874496a41 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -134,9 +134,6 @@ const VMStateDescription vmstate_cpu_common = {
bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
- /* cache the cpu class for the hotpath */
- cpu->cc = CPU_GET_CLASS(cpu);
-
if (!accel_cpu_common_realize(cpu, errp)) {
return false;
}
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index cb79566cc51..ff605059c15 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -238,6 +238,9 @@ static void cpu_common_initfn(Object *obj)
{
CPUState *cpu = CPU(obj);
+ /* cache the cpu class for the hotpath */
+ cpu->cc = CPU_GET_CLASS(cpu);
+
gdb_init_cpu(cpu);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
--
2.47.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 04/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-01-22 9:30 ` [PATCH v2 03/10] cpus: Cache CPUClass early in instance_init() handler Philippe Mathieu-Daudé
@ 2025-01-22 9:30 ` Philippe Mathieu-Daudé
2025-01-22 9:30 ` [PATCH v2 05/10] accel: " Philippe Mathieu-Daudé
` (6 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:30 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Richard Henderson, Alex Bennée,
Philippe Mathieu-Daudé
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 10 +++-----
cpu-common.c | 10 ++++----
cpu-target.c | 6 ++---
hw/core/cpu-common.c | 13 ++++------
hw/core/cpu-system.c | 55 +++++++++++++++----------------------------
5 files changed, 32 insertions(+), 62 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 7b6b22c431b..d9e19d192e4 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -826,10 +826,8 @@ const char *parse_cpu_option(const char *cpu_option);
*/
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- g_assert(cc->has_work);
- return cc->has_work(cpu);
+ g_assert(cpu->cc->has_work);
+ return cpu->cc->has_work(cpu);
}
/**
@@ -968,9 +966,7 @@ void cpu_interrupt(CPUState *cpu, int mask);
*/
static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- cc->set_pc(cpu, addr);
+ cpu->cc->set_pc(cpu, addr);
}
/**
diff --git a/cpu-common.c b/cpu-common.c
index 4248b2d727e..3a409aacb2e 100644
--- a/cpu-common.c
+++ b/cpu-common.c
@@ -389,11 +389,10 @@ void process_queued_cpu_work(CPUState *cpu)
int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
CPUBreakpoint **breakpoint)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
CPUBreakpoint *bp;
- if (cc->gdb_adjust_breakpoint) {
- pc = cc->gdb_adjust_breakpoint(cpu, pc);
+ if (cpu->cc->gdb_adjust_breakpoint) {
+ pc = cpu->cc->gdb_adjust_breakpoint(cpu, pc);
}
bp = g_malloc(sizeof(*bp));
@@ -419,11 +418,10 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
/* Remove a specific breakpoint. */
int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
CPUBreakpoint *bp;
- if (cc->gdb_adjust_breakpoint) {
- pc = cc->gdb_adjust_breakpoint(cpu, pc);
+ if (cpu->cc->gdb_adjust_breakpoint) {
+ pc = cpu->cc->gdb_adjust_breakpoint(cpu, pc);
}
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
diff --git a/cpu-target.c b/cpu-target.c
index 89874496a41..98e9e7cc4a1 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -159,10 +159,8 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
void cpu_exec_unrealizefn(CPUState *cpu)
{
#ifndef CONFIG_USER_ONLY
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->sysemu_ops->legacy_vmsd != NULL) {
- vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
+ if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
+ vmstate_unregister(NULL, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index ff605059c15..886aa793c04 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -40,9 +40,7 @@ CPUState *cpu_by_arch_id(int64_t id)
CPUState *cpu;
CPU_FOREACH(cpu) {
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->get_arch_id(cpu) == id) {
+ if (cpu->cc->get_arch_id(cpu) == id) {
return cpu;
}
}
@@ -101,11 +99,9 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->dump_state) {
+ if (cpu->cc->dump_state) {
cpu_synchronize_state(cpu);
- cc->dump_state(cpu, f, flags);
+ cpu->cc->dump_state(cpu, f, flags);
}
}
@@ -119,11 +115,10 @@ void cpu_reset(CPUState *cpu)
static void cpu_common_reset_hold(Object *obj, ResetType type)
{
CPUState *cpu = CPU(obj);
- CPUClass *cc = CPU_GET_CLASS(cpu);
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
- log_cpu_state(cpu, cc->reset_dump_flags);
+ log_cpu_state(cpu, cpu->cc->reset_dump_flags);
}
cpu->interrupt_request = 0;
diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c
index 6aae28a349a..37d54d04bf8 100644
--- a/hw/core/cpu-system.c
+++ b/hw/core/cpu-system.c
@@ -25,10 +25,8 @@
bool cpu_paging_enabled(const CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->sysemu_ops->get_paging_enabled) {
- return cc->sysemu_ops->get_paging_enabled(cpu);
+ if (cpu->cc->sysemu_ops->get_paging_enabled) {
+ return cpu->cc->sysemu_ops->get_paging_enabled(cpu);
}
return false;
@@ -37,10 +35,8 @@ bool cpu_paging_enabled(const CPUState *cpu)
bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
Error **errp)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->sysemu_ops->get_memory_mapping) {
- return cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
+ if (cpu->cc->sysemu_ops->get_memory_mapping) {
+ return cpu->cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
}
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
@@ -50,14 +46,12 @@ bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->sysemu_ops->get_phys_page_attrs_debug) {
- return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
+ if (cpu->cc->sysemu_ops->get_phys_page_attrs_debug) {
+ return cpu->cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
}
/* Fallback for CPUs which don't implement the _attrs_ hook */
*attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->sysemu_ops->get_phys_page_debug(cpu, addr);
+ return cpu->cc->sysemu_ops->get_phys_page_debug(cpu, addr);
}
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
@@ -81,64 +75,53 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cc->sysemu_ops->write_elf32_qemunote) {
+ if (!cpu->cc->sysemu_ops->write_elf32_qemunote) {
return 0;
}
- return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
+ return (*cpu->cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
}
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cc->sysemu_ops->write_elf32_note) {
+ if (!cpu->cc->sysemu_ops->write_elf32_note) {
return -1;
}
- return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
+ return (*cpu->cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
}
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cc->sysemu_ops->write_elf64_qemunote) {
+ if (!cpu->cc->sysemu_ops->write_elf64_qemunote) {
return 0;
}
- return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
+ return (*cpu->cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
}
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (!cc->sysemu_ops->write_elf64_note) {
+ if (!cpu->cc->sysemu_ops->write_elf64_note) {
return -1;
}
- return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
+ return (*cpu->cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
}
bool cpu_virtio_is_big_endian(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->sysemu_ops->virtio_is_big_endian) {
- return cc->sysemu_ops->virtio_is_big_endian(cpu);
+ if (cpu->cc->sysemu_ops->virtio_is_big_endian) {
+ return cpu->cc->sysemu_ops->virtio_is_big_endian(cpu);
}
return target_words_bigendian();
}
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
GuestPanicInformation *res = NULL;
- if (cc->sysemu_ops->get_crash_info) {
- res = cc->sysemu_ops->get_crash_info(cpu);
+ if (cpu->cc->sysemu_ops->get_crash_info) {
+ res = cpu->cc->sysemu_ops->get_crash_info(cpu);
}
return res;
}
--
2.47.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 05/10] accel: Prefer cached CpuClass over CPU_GET_CLASS() macro
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2025-01-22 9:30 ` [PATCH v2 04/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
@ 2025-01-22 9:30 ` Philippe Mathieu-Daudé
2025-01-22 9:30 ` [PATCH v2 06/10] user: " Philippe Mathieu-Daudé
` (5 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:30 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Richard Henderson, Alex Bennée,
Philippe Mathieu-Daudé
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/accel-target.c | 12 +++++-------
accel/tcg/tcg-accel-ops.c | 3 +--
accel/tcg/translate-all.c | 2 +-
accel/tcg/watchpoint.c | 9 ++++-----
4 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/accel/accel-target.c b/accel/accel-target.c
index 08626c00c2d..8a16c0c3ae0 100644
--- a/accel/accel-target.c
+++ b/accel/accel-target.c
@@ -112,22 +112,20 @@ void accel_init_interfaces(AccelClass *ac)
void accel_cpu_instance_init(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->accel_cpu && cc->accel_cpu->cpu_instance_init) {
- cc->accel_cpu->cpu_instance_init(cpu);
+ if (cpu->cc->accel_cpu && cpu->cc->accel_cpu->cpu_instance_init) {
+ cpu->cc->accel_cpu->cpu_instance_init(cpu);
}
}
bool accel_cpu_common_realize(CPUState *cpu, Error **errp)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
AccelState *accel = current_accel();
AccelClass *acc = ACCEL_GET_CLASS(accel);
/* target specific realization */
- if (cc->accel_cpu && cc->accel_cpu->cpu_target_realize
- && !cc->accel_cpu->cpu_target_realize(cpu, errp)) {
+ if (cpu->cc->accel_cpu
+ && cpu->cc->accel_cpu->cpu_target_realize
+ && !cpu->cc->accel_cpu->cpu_target_realize(cpu, errp)) {
return false;
}
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 6e3f1fa92b2..299d6176cfb 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -120,10 +120,9 @@ static inline int xlat_gdb_type(CPUState *cpu, int gdbtype)
[GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
};
- CPUClass *cc = CPU_GET_CLASS(cpu);
int cputype = xlat[gdbtype];
- if (cc->gdb_stop_before_watchpoint) {
+ if (cpu->cc->gdb_stop_before_watchpoint) {
cputype |= BP_STOP_BEFORE_ACCESS;
}
return cputype;
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index d56ca13cddf..5a378cb0281 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -622,7 +622,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
* to account for the re-execution of the branch.
*/
n = 1;
- cc = CPU_GET_CLASS(cpu);
+ cc = cpu->cc;
if (cc->tcg_ops->io_recompile_replay_branch &&
cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) {
cpu->neg.icount_decr.u16.low++;
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
index af57d182d5b..52e550dec6b 100644
--- a/accel/tcg/watchpoint.c
+++ b/accel/tcg/watchpoint.c
@@ -69,7 +69,6 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
MemTxAttrs attrs, int flags, uintptr_t ra)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
CPUWatchpoint *wp;
assert(tcg_enabled());
@@ -85,9 +84,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
return;
}
- if (cc->tcg_ops->adjust_watchpoint_address) {
+ if (cpu->cc->tcg_ops->adjust_watchpoint_address) {
/* this is currently used only by ARM BE32 */
- addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
+ addr = cpu->cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
}
assert((flags & ~BP_MEM_ACCESS) == 0);
@@ -119,8 +118,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
wp->hitattrs = attrs;
if (wp->flags & BP_CPU
- && cc->tcg_ops->debug_check_watchpoint
- && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
+ && cpu->cc->tcg_ops->debug_check_watchpoint
+ && !cpu->cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
wp->flags &= ~BP_WATCHPOINT_HIT;
continue;
}
--
2.47.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 06/10] user: Prefer cached CpuClass over CPU_GET_CLASS() macro
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2025-01-22 9:30 ` [PATCH v2 05/10] accel: " Philippe Mathieu-Daudé
@ 2025-01-22 9:30 ` Philippe Mathieu-Daudé
2025-01-22 9:30 ` [PATCH v2 07/10] disas: " Philippe Mathieu-Daudé
` (4 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:30 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Richard Henderson, Alex Bennée,
Philippe Mathieu-Daudé
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/alpha/target_proc.h | 2 +-
bsd-user/signal.c | 4 ++--
linux-user/signal.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/linux-user/alpha/target_proc.h b/linux-user/alpha/target_proc.h
index dac37dffc9d..da437ee0e56 100644
--- a/linux-user/alpha/target_proc.h
+++ b/linux-user/alpha/target_proc.h
@@ -15,7 +15,7 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
const char *p, *q;
int t;
- p = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(env_cpu(cpu_env))));
+ p = object_class_get_name(OBJECT_CLASS(env_cpu(cpu_env)->cc));
q = strchr(p, '-');
t = q - p;
assert(t < sizeof(model));
diff --git a/bsd-user/signal.c b/bsd-user/signal.c
index b4e1458237a..4e32cd64f18 100644
--- a/bsd-user/signal.c
+++ b/bsd-user/signal.c
@@ -1021,7 +1021,7 @@ void process_pending_signals(CPUArchState *env)
void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, bool maperr, uintptr_t ra)
{
- const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
if (tcg_ops->record_sigsegv) {
tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
@@ -1037,7 +1037,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, uintptr_t ra)
{
- const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
if (tcg_ops->record_sigbus) {
tcg_ops->record_sigbus(cpu, addr, access_type, ra);
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 087c4d270e4..53b40e82261 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -743,7 +743,7 @@ void force_sigsegv(int oldsig)
void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, bool maperr, uintptr_t ra)
{
- const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
if (tcg_ops->record_sigsegv) {
tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
@@ -759,7 +759,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
MMUAccessType access_type, uintptr_t ra)
{
- const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
if (tcg_ops->record_sigbus) {
tcg_ops->record_sigbus(cpu, addr, access_type, ra);
--
2.47.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 07/10] disas: Prefer cached CpuClass over CPU_GET_CLASS() macro
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2025-01-22 9:30 ` [PATCH v2 06/10] user: " Philippe Mathieu-Daudé
@ 2025-01-22 9:30 ` Philippe Mathieu-Daudé
2025-01-22 9:30 ` [PATCH v2 08/10] gdbstub: " Philippe Mathieu-Daudé
` (3 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:30 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Richard Henderson, Alex Bennée,
Philippe Mathieu-Daudé
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
disas/disas-common.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/disas/disas-common.c b/disas/disas-common.c
index de61f6d8a12..57505823cb7 100644
--- a/disas/disas-common.c
+++ b/disas/disas-common.c
@@ -67,9 +67,8 @@ void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu)
s->info.endian = BFD_ENDIAN_LITTLE;
}
- CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->disas_set_info) {
- cc->disas_set_info(cpu, &s->info);
+ if (cpu->cc->disas_set_info) {
+ cpu->cc->disas_set_info(cpu, &s->info);
}
}
--
2.47.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 08/10] gdbstub: Prefer cached CpuClass over CPU_GET_CLASS() macro
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2025-01-22 9:30 ` [PATCH v2 07/10] disas: " Philippe Mathieu-Daudé
@ 2025-01-22 9:30 ` Philippe Mathieu-Daudé
2025-01-22 21:34 ` Alex Bennée
2025-01-22 9:30 ` [PATCH v2 09/10] hw/acpi: " Philippe Mathieu-Daudé
` (2 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:30 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Richard Henderson, Alex Bennée,
Philippe Mathieu-Daudé
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
gdbstub/gdbstub.c | 26 +++++++++-----------------
gdbstub/system.c | 7 ++-----
gdbstub/user-target.c | 6 ++----
gdbstub/user.c | 7 ++-----
4 files changed, 15 insertions(+), 31 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c
index e366df12d4a..282e13e163f 100644
--- a/gdbstub/gdbstub.c
+++ b/gdbstub/gdbstub.c
@@ -354,7 +354,6 @@ static const char *get_feature_xml(const char *p, const char **newp,
GDBProcess *process)
{
CPUState *cpu = gdb_get_first_cpu_in_process(process);
- CPUClass *cc = CPU_GET_CLASS(cpu);
GDBRegisterState *r;
size_t len;
@@ -377,11 +376,11 @@ static const char *get_feature_xml(const char *p, const char **newp,
"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
"<target>"));
- if (cc->gdb_arch_name) {
+ if (cpu->cc->gdb_arch_name) {
g_ptr_array_add(
xml,
g_markup_printf_escaped("<architecture>%s</architecture>",
- cc->gdb_arch_name(cpu)));
+ cpu->cc->gdb_arch_name(cpu)));
}
for (guint i = 0; i < cpu->gdb_regs->len; i++) {
r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);
@@ -520,11 +519,10 @@ GArray *gdb_get_register_list(CPUState *cpu)
int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
GDBRegisterState *r;
- if (reg < cc->gdb_num_core_regs) {
- return cc->gdb_read_register(cpu, buf, reg);
+ if (reg < cpu->cc->gdb_num_core_regs) {
+ return cpu->cc->gdb_read_register(cpu, buf, reg);
}
for (guint i = 0; i < cpu->gdb_regs->len; i++) {
@@ -538,11 +536,10 @@ int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
GDBRegisterState *r;
- if (reg < cc->gdb_num_core_regs) {
- return cc->gdb_write_register(cpu, mem_buf, reg);
+ if (reg < cpu->cc->gdb_num_core_regs) {
+ return cpu->cc->gdb_write_register(cpu, mem_buf, reg);
}
for (guint i = 0; i < cpu->gdb_regs->len; i++) {
@@ -570,7 +567,7 @@ static void gdb_register_feature(CPUState *cpu, int base_reg,
void gdb_init_cpu(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
+ CPUClass *cc = cpu->cc;
const GDBFeature *feature;
cpu->gdb_regs = g_array_new(false, false, sizeof(GDBRegisterState));
@@ -1646,11 +1643,8 @@ void gdb_extend_qsupported_features(char *qflags)
static void handle_query_supported(GArray *params, void *user_ctx)
{
- CPUClass *cc;
-
g_string_printf(gdbserver_state.str_buf, "PacketSize=%x", MAX_PACKET_LENGTH);
- cc = CPU_GET_CLASS(first_cpu);
- if (cc->gdb_core_xml_file) {
+ if (first_cpu->cc->gdb_core_xml_file) {
g_string_append(gdbserver_state.str_buf, ";qXfer:features:read+");
}
@@ -1697,7 +1691,6 @@ static void handle_query_supported(GArray *params, void *user_ctx)
static void handle_query_xfer_features(GArray *params, void *user_ctx)
{
GDBProcess *process;
- CPUClass *cc;
unsigned long len, total_len, addr;
const char *xml;
const char *p;
@@ -1708,8 +1701,7 @@ static void handle_query_xfer_features(GArray *params, void *user_ctx)
}
process = gdb_get_cpu_process(gdbserver_state.g_cpu);
- cc = CPU_GET_CLASS(gdbserver_state.g_cpu);
- if (!cc->gdb_core_xml_file) {
+ if (!gdbserver_state.g_cpu->cc->gdb_core_xml_file) {
gdb_put_packet("");
return;
}
diff --git a/gdbstub/system.c b/gdbstub/system.c
index 8ce79fa88cf..215a2c5dcad 100644
--- a/gdbstub/system.c
+++ b/gdbstub/system.c
@@ -452,8 +452,6 @@ static int phy_memory_mode;
int gdb_target_memory_rw_debug(CPUState *cpu, hwaddr addr,
uint8_t *buf, int len, bool is_write)
{
- CPUClass *cc;
-
if (phy_memory_mode) {
if (is_write) {
cpu_physical_memory_write(addr, buf, len);
@@ -463,9 +461,8 @@ int gdb_target_memory_rw_debug(CPUState *cpu, hwaddr addr,
return 0;
}
- cc = CPU_GET_CLASS(cpu);
- if (cc->memory_rw_debug) {
- return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
+ if (cpu->cc->memory_rw_debug) {
+ return cpu->cc->memory_rw_debug(cpu, addr, buf, len, is_write);
}
return cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
diff --git a/gdbstub/user-target.c b/gdbstub/user-target.c
index 22bf4008c0f..355b1901b4f 100644
--- a/gdbstub/user-target.c
+++ b/gdbstub/user-target.c
@@ -233,10 +233,8 @@ void gdb_handle_query_offsets(GArray *params, void *user_ctx)
static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, bool is_write)
{
- CPUClass *cc;
- cc = CPU_GET_CLASS(cpu);
- if (cc->memory_rw_debug) {
- return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
+ if (cpu->cc->memory_rw_debug) {
+ return cpu->cc->memory_rw_debug(cpu, addr, buf, len, is_write);
}
return cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
}
diff --git a/gdbstub/user.c b/gdbstub/user.c
index c2bdfc3d491..375f7f80653 100644
--- a/gdbstub/user.c
+++ b/gdbstub/user.c
@@ -665,11 +665,8 @@ int gdb_continue_partial(char *newstates)
int gdb_target_memory_rw_debug(CPUState *cpu, hwaddr addr,
uint8_t *buf, int len, bool is_write)
{
- CPUClass *cc;
-
- cc = CPU_GET_CLASS(cpu);
- if (cc->memory_rw_debug) {
- return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
+ if (cpu->cc->memory_rw_debug) {
+ return cpu->cc->memory_rw_debug(cpu, addr, buf, len, is_write);
}
return cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
}
--
2.47.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 08/10] gdbstub: Prefer cached CpuClass over CPU_GET_CLASS() macro
2025-01-22 9:30 ` [PATCH v2 08/10] gdbstub: " Philippe Mathieu-Daudé
@ 2025-01-22 21:34 ` Alex Bennée
0 siblings, 0 replies; 16+ messages in thread
From: Alex Bennée @ 2025-01-22 21:34 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel, qemu-arm, Richard Henderson
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> CpuState caches its CPUClass since commit 6fbdff87062
> ("cpu: cache CPUClass in CPUState for hot code paths"),
> use it.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 09/10] hw/acpi: Prefer cached CpuClass over CPU_GET_CLASS() macro
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2025-01-22 9:30 ` [PATCH v2 08/10] gdbstub: " Philippe Mathieu-Daudé
@ 2025-01-22 9:30 ` Philippe Mathieu-Daudé
2025-01-22 9:30 ` [PATCH v2 10/10] target/arm: " Philippe Mathieu-Daudé
2025-02-10 21:56 ` [PATCH v2 00/10] cpus: " Philippe Mathieu-Daudé
10 siblings, 0 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:30 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Richard Henderson, Alex Bennée,
Philippe Mathieu-Daudé
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/acpi/cpu.c | 4 ++--
hw/acpi/cpu_hotplug.c | 3 +--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
index f70a2c045e1..6f1ae79edbf 100644
--- a/hw/acpi/cpu.c
+++ b/hw/acpi/cpu.c
@@ -235,8 +235,8 @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner,
static AcpiCpuStatus *get_cpu_status(CPUHotplugState *cpu_st, DeviceState *dev)
{
- CPUClass *k = CPU_GET_CLASS(dev);
- uint64_t cpu_arch_id = k->get_arch_id(CPU(dev));
+ CPUState *cpu = CPU(dev);
+ uint64_t cpu_arch_id = cpu->cc->get_arch_id(cpu);
int i;
for (i = 0; i < cpu_st->dev_count; i++) {
diff --git a/hw/acpi/cpu_hotplug.c b/hw/acpi/cpu_hotplug.c
index 83b8bc5deb8..aa0e1e3efa5 100644
--- a/hw/acpi/cpu_hotplug.c
+++ b/hw/acpi/cpu_hotplug.c
@@ -62,10 +62,9 @@ static const MemoryRegionOps AcpiCpuHotplug_ops = {
static void acpi_set_cpu_present_bit(AcpiCpuHotplug *g, CPUState *cpu,
bool *swtchd_to_modern)
{
- CPUClass *k = CPU_GET_CLASS(cpu);
int64_t cpu_id;
- cpu_id = k->get_arch_id(cpu);
+ cpu_id = cpu->cc->get_arch_id(cpu);
if ((cpu_id / 8) >= ACPI_GPE_PROC_LEN) {
object_property_set_bool(g->device, "cpu-hotplug-legacy", false,
&error_abort);
--
2.47.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 10/10] target/arm: Prefer cached CpuClass over CPU_GET_CLASS() macro
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2025-01-22 9:30 ` [PATCH v2 09/10] hw/acpi: " Philippe Mathieu-Daudé
@ 2025-01-22 9:30 ` Philippe Mathieu-Daudé
2025-02-10 21:56 ` [PATCH v2 00/10] cpus: " Philippe Mathieu-Daudé
10 siblings, 0 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-22 9:30 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Richard Henderson, Alex Bennée,
Philippe Mathieu-Daudé
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 3 +--
target/arm/tcg/cpu-v7m.c | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index dc0231233a6..048b825a006 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -846,7 +846,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- CPUClass *cc = CPU_GET_CLASS(cs);
CPUARMState *env = cpu_env(cs);
uint32_t cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
@@ -946,7 +945,7 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
found:
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
- cc->tcg_ops->do_interrupt(cs);
+ cs->cc->tcg_ops->do_interrupt(cs);
return true;
}
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 03acdf83e00..d2d0b94b630 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -19,7 +19,6 @@
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- CPUClass *cc = CPU_GET_CLASS(cs);
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
bool ret = false;
@@ -35,7 +34,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD
&& (armv7m_nvic_can_take_pending_exception(env->nvic))) {
cs->exception_index = EXCP_IRQ;
- cc->tcg_ops->do_interrupt(cs);
+ cs->cc->tcg_ops->do_interrupt(cs);
ret = true;
}
return ret;
--
2.47.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro
2025-01-22 9:30 [PATCH v2 00/10] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2025-01-22 9:30 ` [PATCH v2 10/10] target/arm: " Philippe Mathieu-Daudé
@ 2025-02-10 21:56 ` Philippe Mathieu-Daudé
10 siblings, 0 replies; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-02-10 21:56 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, Richard Henderson, Alex Bennée
On 22/1/25 10:30, Philippe Mathieu-Daudé wrote:
> Philippe Mathieu-Daudé (10):
> hw/core/generic-loader: Do not open-code cpu_set_pc()
> gdbstub: Clarify no more than @gdb_num_core_regs can be accessed
> cpus: Cache CPUClass early in instance_init() handler
> cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro
> accel: Prefer cached CpuClass over CPU_GET_CLASS() macro
> user: Prefer cached CpuClass over CPU_GET_CLASS() macro
> disas: Prefer cached CpuClass over CPU_GET_CLASS() macro
> gdbstub: Prefer cached CpuClass over CPU_GET_CLASS() macro
> hw/acpi: Prefer cached CpuClass over CPU_GET_CLASS() macro
> target/arm: Prefer cached CpuClass over CPU_GET_CLASS() macro
Series queued, thanks.
^ permalink raw reply [flat|nested] 16+ messages in thread