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From: "Cédric Le Goater" <clg@redhat.com>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Jamin Lin" <jamin_lin@aspeedtech.com>,
	"Cédric Le Goater" <clg@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 02/12] hw/sd/sdhci: Introduce a new Write Protected pin inverted property
Date: Mon, 27 Jan 2025 10:42:29 +0100	[thread overview]
Message-ID: <20250127094239.636526-3-clg@redhat.com> (raw)
In-Reply-To: <20250127094239.636526-1-clg@redhat.com>

From: Jamin Lin <jamin_lin@aspeedtech.com>

The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24). However, some boards are
design Write Protected pin active high. In other words, write enable the bit 19
should be 0 and write protected the bit 19 should be 1 at the
Present State Register (0x24). To support it, introduces a new "wp-inverted"
property and set it false by default.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20241114094839.4128404-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 include/hw/sd/sdhci.h | 5 +++++
 hw/sd/sdhci.c         | 6 ++++++
 2 files changed, 11 insertions(+)

diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 6cd2822f1d13..38c08e285980 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -100,6 +100,11 @@ struct SDHCIState {
     uint8_t sd_spec_version;
     uint8_t uhs_mode;
     uint8_t vendor;        /* For vendor specific functionality */
+    /*
+     * Write Protect pin default active low for detecting SD card
+     * to be protected. Set wp_inverted to invert the signal.
+     */
+    bool wp_inverted;
 };
 typedef struct SDHCIState SDHCIState;
 
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 318587ff57ca..99dd4a4e9528 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -274,6 +274,10 @@ static void sdhci_set_readonly(DeviceState *dev, bool level)
 {
     SDHCIState *s = (SDHCIState *)dev;
 
+    if (s->wp_inverted) {
+        level = !level;
+    }
+
     if (level) {
         s->prnsts &= ~SDHC_WRITE_PROTECT;
     } else {
@@ -1555,6 +1559,8 @@ static const Property sdhci_sysbus_properties[] = {
                      false),
     DEFINE_PROP_LINK("dma", SDHCIState,
                      dma_mr, TYPE_MEMORY_REGION, MemoryRegion *),
+    DEFINE_PROP_BOOL("wp-inverted", SDHCIState,
+                     wp_inverted, false),
 };
 
 static void sdhci_sysbus_init(Object *obj)
-- 
2.48.1



  parent reply	other threads:[~2025-01-27  9:44 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-27  9:42 [PULL 00/12] aspeed queue Cédric Le Goater
2025-01-27  9:42 ` [PULL 01/12] hw/arm/aspeed: fix connect_serial_hds_to_uarts Cédric Le Goater
2025-01-27  9:42 ` Cédric Le Goater [this message]
2025-01-27  9:42 ` [PULL 03/12] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB Cédric Le Goater
2025-01-27  9:42 ` [PULL 04/12] hw/timer/aspeed: Refactor Timer Callbacks for SoC-Specific Implementations Cédric Le Goater
2025-01-27  9:42 ` [PULL 05/12] hw/timer/aspeed: Add AST2700 Support Cédric Le Goater
2025-01-27  9:42 ` [PULL 06/12] aspeed/soc: Support Timer for AST2700 Cédric Le Goater
2025-01-27  9:42 ` [PULL 07/12] test/functional: Update the Aspeed aarch64 test Cédric Le Goater
2025-01-27  9:42 ` [PULL 08/12] test/functional: Update buildroot images to 2024.11 Cédric Le Goater
2025-01-27  9:42 ` [PULL 09/12] aspeed: Create sd devices only when defaults are enabled Cédric Le Goater
2025-01-27  9:42 ` [PULL 10/12] aspeed/wdt: Fix coding style Cédric Le Goater
2025-01-27  9:42 ` [PULL 11/12] aspeed/wdt: Support software reset mode for AST2600 Cédric Le Goater
2025-01-27  9:42 ` [PULL 12/12] docs/system/arm/aspeed: Remove tacoma-bmc from the documentation Cédric Le Goater
2025-01-27 19:42 ` [PULL 00/12] aspeed queue Stefan Hajnoczi

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