Re: [PATCH 3/3] hw/cxl: introduce CXL type-2 device emulation

[Jonathan Cameron via <qemu-devel@nongnu.org>]

> >> +static void cxl_accel_class_init(ObjectClass *oc, void *data)
> >> +{
> >> +    DeviceClass *dc = DEVICE_CLASS(oc);
> >> +    PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
> >> +
> >> +    pc->realize = cxl_accel_realize;
> >> +    pc->exit = cxl_accel_exit;
> >> +
> >> +    pc->class_id = PCI_CLASS_CXL_QEMU_ACCEL;
> >> +    pc->vendor_id = PCI_VENDOR_ID_INTEL;
> >> +    pc->device_id = 0xd94;  
> >  
> 
> The IDs are mostly from Ira's original T2 emulated device patches.
> I will take a look to see if there is a better option for this.

I pinged Ira and you on the CXL discord.  May be fine to use this
and save you figuring out who in holds the magic list at NVidia
and persuading them to let you have one ;)

> 
> > If you are posting these I hope you have those IDs reserved
> > (which seems unlikely ;)
> > We need to be absolutely sure we never hit an existing ID which generally
> > means you need to find whoever controls those allocations in your company
> > and get them to give you an ID for this.
> >  
> >> +    pc->revision = 1;
> >> +
> >> +    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
> >> +    dc->desc = "CXL Accelerator Device (Type 2)";
> >> +    device_class_set_legacy_reset(dc, cxl_accel_reset);
> >> +    device_class_set_props(dc, cxl_accel_props);
> >> +}  
> >  
> >>   void cxl_event_init(CXLDeviceState *cxlds, int start_msg_num);
> >> diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
> >> index f1a53fea8d..08bc469316 100644
> >> --- a/include/hw/pci/pci_ids.h
> >> +++ b/include/hw/pci/pci_ids.h
> >> @@ -55,6 +55,7 @@
> >>   #define PCI_CLASS_MEMORY_RAM             0x0500
> >>   #define PCI_CLASS_MEMORY_FLASH           0x0501
> >>   #define PCI_CLASS_MEMORY_CXL             0x0502
> >> +#define PCI_CLASS_CXL_QEMU_ACCEL         0x0503  
> >
> > Either this is a real device class (which seems unlikely given the name)
> > or you need to choose something else.  PCI maintains a big list of
> > class codes and currently 0x0502 is the highest one define in baseclass 05h
> > (memory controllers)
> >
> > https://members.pcisig.com/wg/PCI-SIG/document/20113
> > (behind a pcisig login)
> >  
> >>   #define PCI_CLASS_MEMORY_OTHER           0x0580
> >>
> >>   #define PCI_BASE_CLASS_BRIDGE            0x06  
> >  
>