[PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.

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* [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.
@ 2025-02-05 11:18 Rajnesh Kanwal
  2025-02-05 11:18 ` [PATCH v6 1/7] target/riscv: Remove obsolete sfence.vm instruction Rajnesh Kanwal
                   ` (7 more replies)
  0 siblings, 8 replies; 12+ messages in thread
From: Rajnesh Kanwal @ 2025-02-05 11:18 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: alistair.francis, bin.meng, liweiwei, dbarboza, zhiwei_liu,
	atishp, apatel, rkanwal, beeman, jason.chien, frank.chang,
	richard.henderson, bmeng.cn

This series enables Control Transfer Records extension support on riscv
platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been ratified and this series is based on v1.0 [0]

CTR extension depends on both the implementation of S-mode and Sscsrind
extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs using
sscsrind extension.

The series is based on Smcdeleg/Ssccfg counter delegation extension [2]
patches [3]. CTR itself doesn't depend on counter delegation support. This
rebase is basically to include the Smcsrind patches.

Here is the link to a quick start guide [4] to setup and run a basic perf demo
on Linux to use CTR Ext.

Qemu patches can be found here:
https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v6

Opensbi patch can be found here:
https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2

Linux kernel patches can be found here:
https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v2

[0]: https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0
[1]: https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0
[2]: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0
[3]: https://lore.kernel.org/qemu-riscv/20241203-counter_delegation-v4-0-c12a89baed86@rivosinc.com/
[4]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
Changelog:
v6: Rebased on latest riscv-to-apply.for-upstream.

v5: Improvements based on Richard Henderson's feedback.
  - Fixed code gen logic to use gen_update_pc() instead of
    tcg_constant_tl().
  - Some function renaming.
  - Rebased onto v4 of counter delegation series.
  - https://lore.kernel.org/qemu-riscv/20241205-b4-ctr_upstream_v3-v5-0-60b993aa567d@rivosinc.com/

v4: Improvements based on Richard Henderson's feedback.
  - Refactored CTR related code generation to move more code into
    translation side and avoid unnecessary code execution in generated
    code.
  - Added missing code in machine.c to migrate the new state.
  - https://lore.kernel.org/r/20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com

v3: Improvements based on Jason Chien and Frank Chang's feedback.
  - Created single set of MACROs for CTR CSRs in cpu_bit.h
  - Some fixes in riscv_ctr_add_entry.
  - Return zero for vs/sireg4-6 for CTR 0x200 to 0x2ff range.
  - Improved extension dependency check.
  - Fixed invalid ctrctl csr selection bug in riscv_ctr_freeze.
  - Added implied rules for Smctr and Ssctr.
  - Added missing SMSTATEEN0_CTR bit in mstateen0 and hstateen0 write ops.
  - Some more cosmetic changes.
  - https://lore.kernel.org/qemu-riscv/20241104-b4-ctr_upstream_v3-v3-0-32fd3c48205f@rivosinc.com/

v2: Lots of improvements based on Jason Chien's feedback including:
  - Added CTR recording for cm.jalt, cm.jt, cm.popret, cm.popretz.
  - Fixed and added more CTR extension enable checks.
  - Fixed CTR CSR predicate functions.
  - Fixed external trap xTE bit checks.
  - One fix in freeze function for VS-mode.
  - Lots of minor code improvements.
  - Added checks in sctrclr instruction helper.
  - https://lore.kernel.org/qemu-riscv/20240619152708.135991-1-rkanwal@rivosinc.com/

v1:
  - https://lore.kernel.org/qemu-riscv/20240529160950.132754-1-rkanwal@rivosinc.com/

---
Rajnesh Kanwal (7):
      target/riscv: Remove obsolete sfence.vm instruction
      target/riscv: Add Control Transfer Records CSR definitions.
      target/riscv: Add support for Control Transfer Records extension CSRs.
      target/riscv: Add support to record CTR entries.
      target/riscv: Add CTR sctrclr instruction.
      target/riscv: machine: Add Control Transfer Record state description
      target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.

 target/riscv/cpu.c                             |  26 ++-
 target/riscv/cpu.h                             |  13 ++
 target/riscv/cpu_bits.h                        | 145 ++++++++++++
 target/riscv/cpu_cfg.h                         |   2 +
 target/riscv/cpu_helper.c                      | 266 ++++++++++++++++++++++
 target/riscv/csr.c                             | 294 ++++++++++++++++++++++++-
 target/riscv/helper.h                          |   2 +
 target/riscv/insn32.decode                     |   2 +-
 target/riscv/insn_trans/trans_privileged.c.inc |  18 +-
 target/riscv/insn_trans/trans_rvi.c.inc        |  75 +++++++
 target/riscv/insn_trans/trans_rvzce.c.inc      |  21 ++
 target/riscv/machine.c                         |  25 +++
 target/riscv/op_helper.c                       |  48 ++++
 target/riscv/tcg/tcg-cpu.c                     |  11 +
 target/riscv/translate.c                       |  46 ++++
 15 files changed, 986 insertions(+), 8 deletions(-)
---
base-commit: 699291ba7774f1580584cd96f84ceda8cc4edb7e
change-id: 20250205-b4-ctr_upstream_v6-71418cd245ee
-- 
Best Regards,
Rajnesh Kanwal



^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH v6 1/7] target/riscv: Remove obsolete sfence.vm instruction
  2025-02-05 11:18 [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
@ 2025-02-05 11:18 ` Rajnesh Kanwal
  2025-02-05 11:18 ` [PATCH v6 2/7] target/riscv: Add Control Transfer Records CSR definitions Rajnesh Kanwal
                   ` (6 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Rajnesh Kanwal @ 2025-02-05 11:18 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: alistair.francis, bin.meng, liweiwei, dbarboza, zhiwei_liu,
	atishp, apatel, rkanwal, beeman, jason.chien, frank.chang,
	richard.henderson, bmeng.cn

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jason Chien <jason.chien@sifive.com>
---
 target/riscv/insn32.decode                     | 1 -
 target/riscv/insn_trans/trans_privileged.c.inc | 5 -----
 2 files changed, 6 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 942c434c6e8c0596d686263f5eba064feba28022..a98dab02057648d9dae28eaf9f9ddb00079211e2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -119,7 +119,6 @@ sret        0001000    00010 00000 000 00000 1110011
 mret        0011000    00010 00000 000 00000 1110011
 wfi         0001000    00101 00000 000 00000 1110011
 sfence_vma  0001001    ..... ..... 000 00000 1110011 @sfence_vma
-sfence_vm   0001000    00100 ..... 000 00000 1110011 @sfence_vm
 
 # *** NMI ***
 mnret       0111000    00010 00000 000 00000 1110011
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 73f940d406135a9b346d66120321e35cf424ec40..27d5558d63edf10a516c068a69023ad9035414fd 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -147,8 +147,3 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
 #endif
     return false;
 }
-
-static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
-{
-    return false;
-}

-- 
2.34.1



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v6 2/7] target/riscv: Add Control Transfer Records CSR definitions.
  2025-02-05 11:18 [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
  2025-02-05 11:18 ` [PATCH v6 1/7] target/riscv: Remove obsolete sfence.vm instruction Rajnesh Kanwal
@ 2025-02-05 11:18 ` Rajnesh Kanwal
  2025-02-05 11:18 ` [PATCH v6 3/7] target/riscv: Add support for Control Transfer Records extension CSRs Rajnesh Kanwal
                   ` (5 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Rajnesh Kanwal @ 2025-02-05 11:18 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: alistair.francis, bin.meng, liweiwei, dbarboza, zhiwei_liu,
	atishp, apatel, rkanwal, beeman, jason.chien, frank.chang,
	richard.henderson, bmeng.cn

The Control Transfer Records (CTR) extension provides a method to
record a limited branch history in register-accessible internal chip
storage.

This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc5

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 145 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 145 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index f97c48a3943fb17b8cbe2d5e45db8126726e9956..70ef443c9947755cc4e7c0c1d03f3cc225d4781b 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -247,6 +247,17 @@
 #define CSR_SIEH            0x114
 #define CSR_SIPH            0x154
 
+/* Machine-Level Control transfer records CSRs */
+#define CSR_MCTRCTL         0x34e
+
+/* Supervisor-Level Control transfer records CSRs */
+#define CSR_SCTRCTL         0x14e
+#define CSR_SCTRSTATUS      0x14f
+#define CSR_SCTRDEPTH       0x15f
+
+/* VS-Level Control transfer records CSRs */
+#define CSR_VSCTRCTL        0x24e
+
 /* Hpervisor CSRs */
 #define CSR_HSTATUS         0x600
 #define CSR_HEDELEG         0x602
@@ -344,6 +355,7 @@
 #define SMSTATEEN0_CS       (1ULL << 0)
 #define SMSTATEEN0_FCSR     (1ULL << 1)
 #define SMSTATEEN0_JVT      (1ULL << 2)
+#define SMSTATEEN0_CTR      (1ULL << 54)
 #define SMSTATEEN0_P1P13    (1ULL << 56)
 #define SMSTATEEN0_HSCONTXT (1ULL << 57)
 #define SMSTATEEN0_IMSIC    (1ULL << 58)
@@ -825,6 +837,139 @@ typedef enum RISCVException {
 #define HENVCFGH_PBMTE                      MENVCFGH_PBMTE
 #define HENVCFGH_STCE                       MENVCFGH_STCE
 
+/* Offsets for every pair of control bits per each priv level */
+#define XS_OFFSET    0ULL
+#define U_OFFSET     2ULL
+#define S_OFFSET     5ULL
+#define M_OFFSET     8ULL
+
+#define PM_XS_BITS   (EXT_STATUS_MASK << XS_OFFSET)
+#define U_PM_ENABLE  (PM_ENABLE  << U_OFFSET)
+#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
+#define U_PM_INSN    (PM_INSN    << U_OFFSET)
+#define S_PM_ENABLE  (PM_ENABLE  << S_OFFSET)
+#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
+#define S_PM_INSN    (PM_INSN    << S_OFFSET)
+#define M_PM_ENABLE  (PM_ENABLE  << M_OFFSET)
+#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
+#define M_PM_INSN    (PM_INSN    << M_OFFSET)
+
+/* mmte CSR bits */
+#define MMTE_PM_XS_BITS     PM_XS_BITS
+#define MMTE_U_PM_ENABLE    U_PM_ENABLE
+#define MMTE_U_PM_CURRENT   U_PM_CURRENT
+#define MMTE_U_PM_INSN      U_PM_INSN
+#define MMTE_S_PM_ENABLE    S_PM_ENABLE
+#define MMTE_S_PM_CURRENT   S_PM_CURRENT
+#define MMTE_S_PM_INSN      S_PM_INSN
+#define MMTE_M_PM_ENABLE    M_PM_ENABLE
+#define MMTE_M_PM_CURRENT   M_PM_CURRENT
+#define MMTE_M_PM_INSN      M_PM_INSN
+#define MMTE_MASK    (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
+                      MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
+                      MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
+                      MMTE_PM_XS_BITS)
+
+/* (v)smte CSR bits */
+#define SMTE_PM_XS_BITS     PM_XS_BITS
+#define SMTE_U_PM_ENABLE    U_PM_ENABLE
+#define SMTE_U_PM_CURRENT   U_PM_CURRENT
+#define SMTE_U_PM_INSN      U_PM_INSN
+#define SMTE_S_PM_ENABLE    S_PM_ENABLE
+#define SMTE_S_PM_CURRENT   S_PM_CURRENT
+#define SMTE_S_PM_INSN      S_PM_INSN
+#define SMTE_MASK    (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
+                      SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
+                      SMTE_PM_XS_BITS)
+
+/* umte CSR bits */
+#define UMTE_U_PM_ENABLE    U_PM_ENABLE
+#define UMTE_U_PM_CURRENT   U_PM_CURRENT
+#define UMTE_U_PM_INSN      U_PM_INSN
+#define UMTE_MASK     (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
+
+/* CTR control register commom fields */
+#define XCTRCTL_U              BIT_ULL(0)
+#define XCTRCTL_S              BIT_ULL(1)
+#define XCTRCTL_RASEMU         BIT_ULL(7)
+#define XCTRCTL_STE            BIT_ULL(8)
+#define XCTRCTL_BPFRZ          BIT_ULL(11)
+#define XCTRCTL_LCOFIFRZ       BIT_ULL(12)
+#define XCTRCTL_EXCINH         BIT_ULL(33)
+#define XCTRCTL_INTRINH        BIT_ULL(34)
+#define XCTRCTL_TRETINH        BIT_ULL(35)
+#define XCTRCTL_NTBREN         BIT_ULL(36)
+#define XCTRCTL_TKBRINH        BIT_ULL(37)
+#define XCTRCTL_INDCALLINH     BIT_ULL(40)
+#define XCTRCTL_DIRCALLINH     BIT_ULL(41)
+#define XCTRCTL_INDJMPINH      BIT_ULL(42)
+#define XCTRCTL_DIRJMPINH      BIT_ULL(43)
+#define XCTRCTL_CORSWAPINH     BIT_ULL(44)
+#define XCTRCTL_RETINH         BIT_ULL(45)
+#define XCTRCTL_INDLJMPINH     BIT_ULL(46)
+#define XCTRCTL_DIRLJMPINH     BIT_ULL(47)
+
+#define XCTRCTL_MASK (XCTRCTL_U | XCTRCTL_S | XCTRCTL_RASEMU |                \
+                      XCTRCTL_STE | XCTRCTL_BPFRZ | XCTRCTL_LCOFIFRZ |        \
+                      XCTRCTL_EXCINH | XCTRCTL_INTRINH | XCTRCTL_TRETINH |    \
+                      XCTRCTL_NTBREN | XCTRCTL_TKBRINH | XCTRCTL_INDCALLINH | \
+                      XCTRCTL_DIRCALLINH | XCTRCTL_INDJMPINH |                \
+                      XCTRCTL_DIRJMPINH | XCTRCTL_CORSWAPINH |                \
+                      XCTRCTL_RETINH | XCTRCTL_INDLJMPINH | XCTRCTL_DIRLJMPINH)
+
+#define XCTRCTL_INH_START         32U
+
+/* CTR mctrctl bits */
+#define MCTRCTL_M                 BIT_ULL(2)
+#define MCTRCTL_MTE               BIT_ULL(9)
+
+#define MCTRCTL_MASK              (XCTRCTL_MASK | MCTRCTL_M | MCTRCTL_MTE)
+#define SCTRCTL_MASK              XCTRCTL_MASK
+#define VSCTRCTL_MASK             XCTRCTL_MASK
+
+/* sctrstatus CSR bits. */
+#define SCTRSTATUS_WRPTR_MASK       0xFF
+#define SCTRSTATUS_FROZEN           BIT(31)
+#define SCTRSTATUS_MASK             (SCTRSTATUS_WRPTR_MASK | SCTRSTATUS_FROZEN)
+
+/* sctrdepth CSR bits. */
+#define SCTRDEPTH_MASK              0x7
+#define SCTRDEPTH_MIN               0U  /* 16 Entries. */
+#define SCTRDEPTH_MAX               4U  /* 256 Entries. */
+
+#define CTR_ENTRIES_FIRST           0x200
+#define CTR_ENTRIES_LAST            0x2ff
+
+#define CTRSOURCE_VALID             BIT(0)
+#define CTRTARGET_MISP              BIT(0)
+
+#define CTRDATA_TYPE_MASK           0xF
+#define CTRDATA_CCV                 BIT(15)
+#define CTRDATA_CCM_MASK            0xFFF0000
+#define CTRDATA_CCE_MASK            0xF0000000
+
+#define CTRDATA_MASK            (CTRDATA_TYPE_MASK | CTRDATA_CCV |  \
+                                 CTRDATA_CCM_MASK | CTRDATA_CCE_MASK)
+
+typedef enum CTRType {
+    CTRDATA_TYPE_NONE                   = 0,
+    CTRDATA_TYPE_EXCEPTION              = 1,
+    CTRDATA_TYPE_INTERRUPT              = 2,
+    CTRDATA_TYPE_EXCEP_INT_RET          = 3,
+    CTRDATA_TYPE_NONTAKEN_BRANCH        = 4,
+    CTRDATA_TYPE_TAKEN_BRANCH           = 5,
+    CTRDATA_TYPE_RESERVED_0             = 6,
+    CTRDATA_TYPE_RESERVED_1             = 7,
+    CTRDATA_TYPE_INDIRECT_CALL          = 8,
+    CTRDATA_TYPE_DIRECT_CALL            = 9,
+    CTRDATA_TYPE_INDIRECT_JUMP          = 10,
+    CTRDATA_TYPE_DIRECT_JUMP            = 11,
+    CTRDATA_TYPE_CO_ROUTINE_SWAP        = 12,
+    CTRDATA_TYPE_RETURN                 = 13,
+    CTRDATA_TYPE_OTHER_INDIRECT_JUMP    = 14,
+    CTRDATA_TYPE_OTHER_DIRECT_JUMP      = 15,
+} CTRType;
+
 /* MISELECT, SISELECT, and VSISELECT bits (AIA) */
 #define ISELECT_IPRIO0                     0x30
 #define ISELECT_IPRIO15                    0x3f

-- 
2.34.1



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v6 3/7] target/riscv: Add support for Control Transfer Records extension CSRs.
  2025-02-05 11:18 [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
  2025-02-05 11:18 ` [PATCH v6 1/7] target/riscv: Remove obsolete sfence.vm instruction Rajnesh Kanwal
  2025-02-05 11:18 ` [PATCH v6 2/7] target/riscv: Add Control Transfer Records CSR definitions Rajnesh Kanwal
@ 2025-02-05 11:18 ` Rajnesh Kanwal
  2025-02-05 11:18 ` [PATCH v6 4/7] target/riscv: Add support to record CTR entries Rajnesh Kanwal
                   ` (4 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Rajnesh Kanwal @ 2025-02-05 11:18 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: alistair.francis, bin.meng, liweiwei, dbarboza, zhiwei_liu,
	atishp, apatel, rkanwal, beeman, jason.chien, frank.chang,
	richard.henderson, bmeng.cn

This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and
sctrdepth CSRs handling.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h     |   5 ++
 target/riscv/cpu_cfg.h |   2 +
 target/riscv/csr.c     | 144 +++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 151 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 97713681cbea79745ec1fabc625ebc707fee7eff..e51a4bc4a535276d1b348f9ed50443be898d538f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -312,6 +312,11 @@ struct CPUArchState {
     target_ulong mcause;
     target_ulong mtval;  /* since: priv-1.10.0 */
 
+    uint64_t mctrctl;
+    uint32_t sctrdepth;
+    uint32_t sctrstatus;
+    uint64_t vsctrctl;
+
     /* Machine and Supervisor interrupt priorities */
     uint8_t miprio[64];
     uint8_t siprio[64];
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index b410b1e603839dcb4091c8167a93473fba4191c1..3f3c1118c08ff66fb9cf1bf77575a4d7257819bf 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -133,6 +133,8 @@ struct RISCVCPUConfig {
     bool ext_zvfhmin;
     bool ext_smaia;
     bool ext_ssaia;
+    bool ext_smctr;
+    bool ext_ssctr;
     bool ext_sscofpmf;
     bool ext_smepmp;
     bool ext_smrnmi;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index afb7544f0780be4f1e9c94f26dc10e2be1060c85..07a591fc90a8a516888dd465292f4e4b4178524d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -639,6 +639,48 @@ static RISCVException hgatp(CPURISCVState *env, int csrno)
     return hmode(env, csrno);
 }
 
+/*
+ * M-mode:
+ * Without ext_smctr raise illegal inst excep.
+ * Otherwise everything is accessible to m-mode.
+ *
+ * S-mode:
+ * Without ext_ssctr or mstateen.ctr raise illegal inst excep.
+ * Otherwise everything other than mctrctl is accessible.
+ *
+ * VS-mode:
+ * Without ext_ssctr or mstateen.ctr raise illegal inst excep.
+ * Without hstateen.ctr raise virtual illegal inst excep.
+ * Otherwise allow sctrctl (vsctrctl), sctrstatus, 0x200-0x2ff entry range.
+ * Always raise illegal instruction exception for sctrdepth.
+ */
+static RISCVException ctr_mmode(CPURISCVState *env, int csrno)
+{
+    /* Check if smctr-ext is present */
+    if (riscv_cpu_cfg(env)->ext_smctr) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static RISCVException ctr_smode(CPURISCVState *env, int csrno)
+{
+    const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
+
+    if (!cfg->ext_smctr && !cfg->ext_ssctr) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_CTR);
+    if (ret == RISCV_EXCP_NONE && csrno == CSR_SCTRDEPTH &&
+        env->virt_enabled) {
+        return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+    }
+
+    return ret;
+}
+
 static RISCVException aia_hmode(CPURISCVState *env, int csrno)
 {
     int ret;
@@ -3234,6 +3276,10 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
         wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);
     }
 
+    if (riscv_cpu_cfg(env)->ext_ssctr) {
+        wr_mask |= SMSTATEEN0_CTR;
+    }
+
     return write_mstateen(env, csrno, wr_mask, new_val);
 }
 
@@ -3273,6 +3319,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
         wr_mask |= SMSTATEEN0_P1P13;
     }
 
+    if (riscv_cpu_cfg(env)->ext_ssctr) {
+        wr_mask |= SMSTATEEN0_CTR;
+    }
+
     return write_mstateenh(env, csrno, wr_mask, new_val);
 }
 
@@ -3327,6 +3377,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
         wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);
     }
 
+    if (riscv_cpu_cfg(env)->ext_ssctr) {
+        wr_mask |= SMSTATEEN0_CTR;
+    }
+
     return write_hstateen(env, csrno, wr_mask, new_val);
 }
 
@@ -3366,6 +3420,10 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
 {
     uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
 
+    if (riscv_cpu_cfg(env)->ext_ssctr) {
+        wr_mask |= SMSTATEEN0_CTR;
+    }
+
     return write_hstateenh(env, csrno, wr_mask, new_val);
 }
 
@@ -4086,6 +4144,86 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException rmw_sctrdepth(CPURISCVState *env, int csrno,
+                                    target_ulong *ret_val,
+                                    target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t mask = wr_mask & SCTRDEPTH_MASK;
+
+    if (ret_val) {
+        *ret_val = env->sctrdepth;
+    }
+
+    env->sctrdepth = (env->sctrdepth & ~mask) | (new_val & mask);
+
+    /* Correct depth. */
+    if (mask) {
+        uint64_t depth = get_field(env->sctrdepth, SCTRDEPTH_MASK);
+
+        if (depth > SCTRDEPTH_MAX) {
+            depth = SCTRDEPTH_MAX;
+            env->sctrdepth = set_field(env->sctrdepth, SCTRDEPTH_MASK, depth);
+        }
+
+        /* Update sctrstatus.WRPTR with a legal value */
+        depth = 16 << depth;
+        env->sctrstatus =
+            env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth - 1));
+    }
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException rmw_sctrstatus(CPURISCVState *env, int csrno,
+                                     target_ulong *ret_val,
+                                     target_ulong new_val, target_ulong wr_mask)
+{
+    uint32_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
+    uint32_t mask = wr_mask & SCTRSTATUS_MASK;
+
+    if (ret_val) {
+        *ret_val = env->sctrstatus;
+    }
+
+    env->sctrstatus = (env->sctrstatus & ~mask) | (new_val & mask);
+
+    /* Update sctrstatus.WRPTR with a legal value */
+    env->sctrstatus = env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth - 1));
+
+    return RISCV_EXCP_NONE;
+}
+
+static RISCVException rmw_xctrctl(CPURISCVState *env, int csrno,
+                                    target_ulong *ret_val,
+                                    target_ulong new_val, target_ulong wr_mask)
+{
+    uint64_t csr_mask, mask = wr_mask;
+    uint64_t *ctl_ptr = &env->mctrctl;
+
+    if (csrno == CSR_MCTRCTL) {
+        csr_mask = MCTRCTL_MASK;
+    } else if (csrno == CSR_SCTRCTL && !env->virt_enabled) {
+        csr_mask = SCTRCTL_MASK;
+    } else {
+        /*
+         * This is for csrno == CSR_SCTRCTL and env->virt_enabled == true
+         * or csrno == CSR_VSCTRCTL.
+         */
+        csr_mask = VSCTRCTL_MASK;
+        ctl_ptr = &env->vsctrctl;
+    }
+
+    mask &= csr_mask;
+
+    if (ret_val) {
+        *ret_val = *ctl_ptr & csr_mask;
+    }
+
+    *ctl_ptr = (*ctl_ptr & ~mask) | (new_val & mask);
+
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_vstopi(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
@@ -5839,6 +5977,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_TINFO]     =  { "tinfo",    debug, read_tinfo,    write_ignore   },
     [CSR_MCONTEXT]  =  { "mcontext", debug, read_mcontext, write_mcontext },
 
+    [CSR_MCTRCTL]    = { "mctrctl",    ctr_mmode,  NULL, NULL, rmw_xctrctl    },
+    [CSR_SCTRCTL]    = { "sctrctl",    ctr_smode,  NULL, NULL, rmw_xctrctl    },
+    [CSR_VSCTRCTL]   = { "vsctrctl",   ctr_smode,  NULL, NULL, rmw_xctrctl    },
+    [CSR_SCTRDEPTH]  = { "sctrdepth",  ctr_smode,  NULL, NULL, rmw_sctrdepth  },
+    [CSR_SCTRSTATUS] = { "sctrstatus", ctr_smode,  NULL, NULL, rmw_sctrstatus },
+
     /* Performance Counters */
     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_hpmcounter },
     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_hpmcounter },

-- 
2.34.1



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v6 4/7] target/riscv: Add support to record CTR entries.
  2025-02-05 11:18 [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
                   ` (2 preceding siblings ...)
  2025-02-05 11:18 ` [PATCH v6 3/7] target/riscv: Add support for Control Transfer Records extension CSRs Rajnesh Kanwal
@ 2025-02-05 11:18 ` Rajnesh Kanwal
  2025-02-05 11:18 ` [PATCH v6 5/7] target/riscv: Add CTR sctrclr instruction Rajnesh Kanwal
                   ` (3 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Rajnesh Kanwal @ 2025-02-05 11:18 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: alistair.francis, bin.meng, liweiwei, dbarboza, zhiwei_liu,
	atishp, apatel, rkanwal, beeman, jason.chien, frank.chang,
	richard.henderson, bmeng.cn

This commit adds logic to records CTR entries of different types
and adds required hooks in TCG and interrupt/Exception logic to
record events.

This commit also adds support to invoke freeze CTR logic for breakpoint
exceptions and counter overflow interrupts.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                             |   7 +
 target/riscv/cpu_helper.c                      | 259 +++++++++++++++++++++++++
 target/riscv/helper.h                          |   1 +
 target/riscv/insn_trans/trans_privileged.c.inc |   2 +
 target/riscv/insn_trans/trans_rvi.c.inc        |  75 +++++++
 target/riscv/insn_trans/trans_rvzce.c.inc      |  21 ++
 target/riscv/op_helper.c                       |  19 ++
 target/riscv/translate.c                       |  46 +++++
 8 files changed, 430 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index e51a4bc4a535276d1b348f9ed50443be898d538f..2d8212e2fefe21defb4ca007d894f02592ed3c89 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -317,6 +317,10 @@ struct CPUArchState {
     uint32_t sctrstatus;
     uint64_t vsctrctl;
 
+    uint64_t ctr_src[16 << SCTRDEPTH_MAX];
+    uint64_t ctr_dst[16 << SCTRDEPTH_MAX];
+    uint64_t ctr_data[16 << SCTRDEPTH_MAX];
+
     /* Machine and Supervisor interrupt priorities */
     uint8_t miprio[64];
     uint8_t siprio[64];
@@ -612,6 +616,9 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
 
 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en);
 
+void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
+    enum CTRType type, target_ulong prev_priv, bool prev_virt);
+
 void riscv_translate_init(void);
 void riscv_translate_code(CPUState *cs, TranslationBlock *tb,
                           int *max_insns, vaddr pc, void *host_pc);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e1dfc4ecbfc5da5204b261cb24d1afa312dba323..afecc822ae7d07a0904f1ec8c223845bbac92523 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -875,6 +875,247 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
     }
 }
 
+static void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask,
+                             bool virt)
+{
+    uint64_t ctl = virt ? env->vsctrctl : env->mctrctl;
+
+    assert((freeze_mask & (~(XCTRCTL_BPFRZ | XCTRCTL_LCOFIFRZ))) == 0);
+
+    if (ctl & freeze_mask) {
+        env->sctrstatus |= SCTRSTATUS_FROZEN;
+    }
+}
+
+static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt)
+{
+    switch (priv) {
+    case PRV_M:
+        return MCTRCTL_M;
+    case PRV_S:
+        if (virt) {
+            return XCTRCTL_S;
+        }
+        return XCTRCTL_S;
+    case PRV_U:
+        if (virt) {
+            return XCTRCTL_U;
+        }
+        return XCTRCTL_U;
+    }
+
+    g_assert_not_reached();
+}
+
+static uint64_t riscv_ctr_get_control(CPURISCVState *env, target_long priv,
+                                      bool virt)
+{
+    switch (priv) {
+    case PRV_M:
+        return env->mctrctl;
+    case PRV_S:
+    case PRV_U:
+        if (virt) {
+            return env->vsctrctl;
+        }
+        return env->mctrctl;
+    }
+
+    g_assert_not_reached();
+}
+
+/*
+ * This function assumes that src privilege and target privilege are not same
+ * and src privilege is less than target privilege. This includes the virtual
+ * state as well.
+ */
+static bool riscv_ctr_check_xte(CPURISCVState *env, target_long src_prv,
+                                bool src_virt)
+{
+    target_long tgt_prv = env->priv;
+    bool res = true;
+
+    /*
+     * VS and U mode are same in terms of xTE bits required to record an
+     * external trap. See 6.1.2. External Traps, table 8 External Trap Enable
+     * Requirements. This changes VS to U to simplify the logic a bit.
+     */
+    if (src_virt && src_prv == PRV_S) {
+        src_prv = PRV_U;
+    } else if (env->virt_enabled && tgt_prv == PRV_S) {
+        tgt_prv = PRV_U;
+    }
+
+    /* VU mode is an outlier here. */
+    if (src_virt && src_prv == PRV_U) {
+        res &= !!(env->vsctrctl & XCTRCTL_STE);
+    }
+
+    switch (src_prv) {
+    case PRV_U:
+        if (tgt_prv == PRV_U) {
+            break;
+        }
+        res &= !!(env->mctrctl & XCTRCTL_STE);
+        /* fall-through */
+    case PRV_S:
+        if (tgt_prv == PRV_S) {
+            break;
+        }
+        res &= !!(env->mctrctl & MCTRCTL_MTE);
+        /* fall-through */
+    case PRV_M:
+        break;
+    }
+
+    return res;
+}
+
+/*
+ * Special cases for traps and trap returns:
+ *
+ * 1- Traps, and trap returns, between enabled modes are recorded as normal.
+ * 2- Traps from an inhibited mode to an enabled mode, and trap returns from an
+ * enabled mode back to an inhibited mode, are partially recorded.  In such
+ * cases, the PC from the inhibited mode (source PC for traps, and target PC
+ * for trap returns) is 0.
+ *
+ * 3- Trap returns from an inhibited mode to an enabled mode are not recorded.
+ * Traps from an enabled mode to an inhibited mode, known as external traps,
+ * receive special handling.
+ * By default external traps are not recorded, but a handshake mechanism exists
+ * to allow partial recording.  Software running in the target mode of the trap
+ * can opt-in to allowing CTR to record traps into that mode even when the mode
+ * is inhibited.  The MTE, STE, and VSTE bits allow M-mode, S-mode, and VS-mode,
+ * respectively, to opt-in. When an External Trap occurs, and xTE=1, such that
+ * x is the target privilege mode of the trap, will CTR record the trap. In such
+ * cases, the target PC is 0.
+ */
+/*
+ * CTR arrays are implemented as circular buffers and new entry is stored at
+ * sctrstatus.WRPTR, but they are presented to software as moving circular
+ * buffers. Which means, software get's the illusion that whenever a new entry
+ * is added the whole buffer is moved by one place and the new entry is added at
+ * the start keeping new entry at idx 0 and older ones follow.
+ *
+ * Depth = 16.
+ *
+ * buffer [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
+ * WRPTR                                   W
+ * entry   7   6   5   4   3   2   1   0   F   E   D   C   B   A   9   8
+ *
+ * When a new entry is added:
+ * buffer [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
+ * WRPTR                                       W
+ * entry   8   7   6   5   4   3   2   1   0   F   E   D   C   B   A   9
+ *
+ * entry here denotes the logical entry number that software can access
+ * using ctrsource, ctrtarget and ctrdata registers. So xiselect 0x200
+ * will return entry 0 i-e buffer[8] and 0x201 will return entry 1 i-e
+ * buffer[7]. Here is how we convert entry to buffer idx.
+ *
+ *    entry = isel - CTR_ENTRIES_FIRST;
+ *    idx = (sctrstatus.WRPTR - entry - 1) & (depth - 1);
+ */
+void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
+    enum CTRType type, target_ulong src_priv, bool src_virt)
+{
+    bool tgt_virt = env->virt_enabled;
+    uint64_t src_mask = riscv_ctr_priv_to_mask(src_priv, src_virt);
+    uint64_t tgt_mask = riscv_ctr_priv_to_mask(env->priv, tgt_virt);
+    uint64_t src_ctrl = riscv_ctr_get_control(env, src_priv, src_virt);
+    uint64_t tgt_ctrl = riscv_ctr_get_control(env, env->priv, tgt_virt);
+    uint64_t depth, head;
+    bool ext_trap = false;
+
+    /*
+     * Return immediately if both target and src recording is disabled or if
+     * CTR is in frozen state.
+     */
+    if ((!(src_ctrl & src_mask) && !(tgt_ctrl & tgt_mask)) ||
+        env->sctrstatus & SCTRSTATUS_FROZEN) {
+        return;
+    }
+
+    /*
+     * With RAS Emul enabled, only allow Indirect, direct calls, Function
+     * returns and Co-routine swap types.
+     */
+    if (tgt_ctrl & XCTRCTL_RASEMU &&
+        type != CTRDATA_TYPE_INDIRECT_CALL &&
+        type != CTRDATA_TYPE_DIRECT_CALL &&
+        type != CTRDATA_TYPE_RETURN &&
+        type != CTRDATA_TYPE_CO_ROUTINE_SWAP) {
+        return;
+    }
+
+    if (type == CTRDATA_TYPE_EXCEPTION || type == CTRDATA_TYPE_INTERRUPT) {
+        /* Case 2 for traps. */
+        if (!(src_ctrl & src_mask)) {
+            src = 0;
+        } else if (!(tgt_ctrl & tgt_mask)) {
+            /* Check if target priv-mode has allowed external trap recording. */
+            if (!riscv_ctr_check_xte(env, src_priv, src_virt)) {
+                return;
+            }
+
+            ext_trap = true;
+            dst = 0;
+        }
+    } else if (type == CTRDATA_TYPE_EXCEP_INT_RET) {
+        /*
+         * Case 3 for trap returns.  Trap returns from inhibited mode are not
+         * recorded.
+         */
+        if (!(src_ctrl & src_mask)) {
+            return;
+        }
+
+        /* Case 2 for trap returns. */
+        if (!(tgt_ctrl & tgt_mask)) {
+            dst = 0;
+        }
+    }
+
+    /* Ignore filters in case of RASEMU mode or External trap. */
+    if (!(tgt_ctrl & XCTRCTL_RASEMU) && !ext_trap) {
+        /*
+         * Check if the specific type is inhibited. Not taken branch filter is
+         * an enable bit and needs to be checked separatly.
+         */
+        bool check = tgt_ctrl & BIT_ULL(type + XCTRCTL_INH_START);
+        if ((type == CTRDATA_TYPE_NONTAKEN_BRANCH && !check) ||
+            (type != CTRDATA_TYPE_NONTAKEN_BRANCH && check)) {
+            return;
+        }
+    }
+
+    head = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
+
+    depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
+    if (tgt_ctrl & XCTRCTL_RASEMU && type == CTRDATA_TYPE_RETURN) {
+        head = (head - 1) & (depth - 1);
+
+        env->ctr_src[head] &= ~CTRSOURCE_VALID;
+        env->sctrstatus =
+            set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, head);
+        return;
+    }
+
+    /* In case of Co-routine SWAP we overwrite latest entry. */
+    if (tgt_ctrl & XCTRCTL_RASEMU && type == CTRDATA_TYPE_CO_ROUTINE_SWAP) {
+        head = (head - 1) & (depth - 1);
+    }
+
+    env->ctr_src[head] = src | CTRSOURCE_VALID;
+    env->ctr_dst[head] = dst & ~CTRTARGET_MISP;
+    env->ctr_data[head] = set_field(0, CTRDATA_TYPE_MASK, type);
+
+    head = (head + 1) & (depth - 1);
+
+    env->sctrstatus = set_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK, head);
+}
+
 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en)
 {
     g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED);
@@ -1986,10 +2227,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
         !(env->mip & (1ULL << cause));
     bool smode_double_trap = false;
     uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
+    const bool prev_virt = env->virt_enabled;
+    const target_ulong prev_priv = env->priv;
     target_ulong tval = 0;
     target_ulong tinst = 0;
     target_ulong htval = 0;
     target_ulong mtval2 = 0;
+    target_ulong src;
     int sxlen = 0;
     int mxlen = 16 << riscv_cpu_mxl(env);
     bool nnmi_excep = false;
@@ -2173,6 +2417,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
         env->pc = (env->stvec >> 2 << 2) +
                   ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);
         riscv_cpu_set_mode(env, PRV_S, virt);
+
+        src = env->sepc;
     } else {
         /*
          * If the hart encounters an exception while executing in M-mode
@@ -2257,6 +2503,19 @@ void riscv_cpu_do_interrupt(CPUState *cs)
                       ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
         }
         riscv_cpu_set_mode(env, PRV_M, virt);
+        src = env->mepc;
+    }
+
+    if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) {
+        if (async && cause == IRQ_PMU_OVF) {
+            riscv_ctr_freeze(env, XCTRCTL_LCOFIFRZ, virt);
+        } else if (!async && cause == RISCV_EXCP_BREAKPOINT) {
+            riscv_ctr_freeze(env, XCTRCTL_BPFRZ, virt);
+        }
+
+        riscv_ctr_add_entry(env, src, env->pc,
+                        async ? CTRDATA_TYPE_INTERRUPT : CTRDATA_TYPE_EXCEPTION,
+                        prev_priv, prev_virt);
     }
 
     /*
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 16ea240d26d31b103dd5da0ac4c7f7d67869af71..163121ade599f5ec2682ecea25a59b664593fba3 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -136,6 +136,7 @@ DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
+DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl)
 /* Native Debug */
 DEF_HELPER_1(itrigger_match, void, env)
 #endif
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 27d5558d63edf10a516c068a69023ad9035414fd..ca52405d7da411907f1d52234df955940efdc25d 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -86,6 +86,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
     if (has_ext(ctx, RVS)) {
         decode_save_opc(ctx, 0);
         translator_io_start(&ctx->base);
+        gen_update_pc(ctx, 0);
         gen_helper_sret(cpu_pc, tcg_env);
         exit_tb(ctx); /* no chaining */
         ctx->base.is_jmp = DISAS_NORETURN;
@@ -103,6 +104,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
 #ifndef CONFIG_USER_ONLY
     decode_save_opc(ctx, 0);
     translator_io_start(&ctx->base);
+    gen_update_pc(ctx, 0);
     gen_helper_mret(cpu_pc, tcg_env);
     exit_tb(ctx); /* no chaining */
     ctx->base.is_jmp = DISAS_NORETURN;
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 96c218a9d7875c6419287ac3aa9746251be3f442..b55f56a5eb2c72eee004e16817a6df13c60446de 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -93,6 +93,51 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
     return true;
 }
 
+#ifndef CONFIG_USER_ONLY
+/*
+ * Indirect calls
+ * - jalr x1, rs where rs != x5;
+ * - jalr x5, rs where rs != x1;
+ * - c.jalr rs1 where rs1 != x5;
+ *
+ * Indirect jumps
+ * - jalr x0, rs where rs != x1 and rs != x5;
+ * - c.jr rs1 where rs1 != x1 and rs1 != x5.
+ *
+ * Returns
+ * - jalr rd, rs where (rs == x1 or rs == x5) and rd != x1 and rd != x5;
+ * - c.jr rs1 where rs1 == x1 or rs1 == x5.
+ *
+ * Co-routine swap
+ * - jalr x1, x5;
+ * - jalr x5, x1;
+ * - c.jalr x5.
+ *
+ * Other indirect jumps
+ * - jalr rd, rs where rs != x1, rs != x5, rd != x0, rd != x1 and rd != x5.
+ */
+static void gen_ctr_jalr(DisasContext *ctx, arg_jalr *a, TCGv dest)
+{
+    TCGv src = tcg_temp_new();
+    TCGv type;
+
+    if ((a->rd == 1 && a->rs1 != 5) || (a->rd == 5 && a->rs1 != 1)) {
+        type = tcg_constant_tl(CTRDATA_TYPE_INDIRECT_CALL);
+    } else if (a->rd == 0 && a->rs1 != 1 && a->rs1 != 5) {
+        type = tcg_constant_tl(CTRDATA_TYPE_INDIRECT_JUMP);
+    } else if ((a->rs1 == 1 || a->rs1 == 5) && (a->rd != 1 && a->rd != 5)) {
+        type = tcg_constant_tl(CTRDATA_TYPE_RETURN);
+    } else if ((a->rs1 == 1 && a->rd == 5) || (a->rs1 == 5 && a->rd == 1)) {
+        type = tcg_constant_tl(CTRDATA_TYPE_CO_ROUTINE_SWAP);
+    } else {
+        type = tcg_constant_tl(CTRDATA_TYPE_OTHER_INDIRECT_JUMP);
+    }
+
+    gen_pc_plus_diff(src, ctx, 0);
+    gen_helper_ctr_add_entry(tcg_env, src, dest, type);
+}
+#endif
+
 static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
 {
     TCGLabel *misaligned = NULL;
@@ -117,6 +162,12 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
     gen_set_gpr(ctx, a->rd, succ_pc);
 
+#ifndef CONFIG_USER_ONLY
+    if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
+        gen_ctr_jalr(ctx, a, target_pc);
+    }
+#endif
+
     tcg_gen_mov_tl(cpu_pc, target_pc);
     if (ctx->fcfi_enabled) {
         /*
@@ -231,6 +282,19 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
     } else {
         tcg_gen_brcond_tl(cond, src1, src2, l);
     }
+
+#ifndef CONFIG_USER_ONLY
+    if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
+        TCGv type = tcg_constant_tl(CTRDATA_TYPE_NONTAKEN_BRANCH);
+        TCGv dest = tcg_temp_new();
+        TCGv src = tcg_temp_new();
+
+        gen_pc_plus_diff(src, ctx, 0);
+        gen_pc_plus_diff(dest, ctx, ctx->cur_insn_len);
+        gen_helper_ctr_add_entry(tcg_env, src, dest, type);
+    }
+#endif
+
     gen_goto_tb(ctx, 1, ctx->cur_insn_len);
     ctx->pc_save = orig_pc_save;
 
@@ -243,6 +307,17 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
         gen_pc_plus_diff(target_pc, ctx, a->imm);
         gen_exception_inst_addr_mis(ctx, target_pc);
     } else {
+#ifndef CONFIG_USER_ONLY
+        if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
+            TCGv type = tcg_constant_tl(CTRDATA_TYPE_TAKEN_BRANCH);
+            TCGv dest = tcg_temp_new();
+            TCGv src = tcg_temp_new();
+
+            gen_pc_plus_diff(src, ctx, 0);
+            gen_pc_plus_diff(dest, ctx, a->imm);
+            gen_helper_ctr_add_entry(tcg_env, src, dest, type);
+        }
+#endif
         gen_goto_tb(ctx, 0, a->imm);
     }
     ctx->pc_save = -1;
diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc
index cd234ad960724c936b92afb6fd1f3c7c2a37cb80..c77c2b927b0cfdf7d21dca7657712015494e1b46 100644
--- a/target/riscv/insn_trans/trans_rvzce.c.inc
+++ b/target/riscv/insn_trans/trans_rvzce.c.inc
@@ -203,6 +203,14 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val)
 
     if (ret) {
         TCGv ret_addr = get_gpr(ctx, xRA, EXT_SIGN);
+#ifndef CONFIG_USER_ONLY
+        if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
+            TCGv type = tcg_constant_tl(CTRDATA_TYPE_RETURN);
+            TCGv src = tcg_temp_new();
+            gen_pc_plus_diff(src, ctx, 0);
+            gen_helper_ctr_add_entry(tcg_env, src, ret_addr, type);
+        }
+#endif
         tcg_gen_mov_tl(cpu_pc, ret_addr);
         tcg_gen_lookup_and_goto_ptr();
         ctx->base.is_jmp = DISAS_NORETURN;
@@ -309,6 +317,19 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
         gen_set_gpr(ctx, xRA, succ_pc);
     }
 
+#ifndef CONFIG_USER_ONLY
+    if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
+        if (a->index >= 32) {
+            TCGv type = tcg_constant_tl(CTRDATA_TYPE_DIRECT_CALL);
+            gen_helper_ctr_add_entry(tcg_env, cpu_pc, addr, type);
+        } else {
+            TCGv type = tcg_constant_tl(CTRDATA_TYPE_DIRECT_JUMP);
+            gen_helper_ctr_add_entry(tcg_env, cpu_pc, addr, type);
+        }
+    }
+#endif
+
+
     tcg_gen_mov_tl(cpu_pc, addr);
 
     tcg_gen_lookup_and_goto_ptr();
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ce1256f439c69c32335193dcdcb98f0c38b10b39..5a99c47b128caf847df76cd1b534f9fdf15a28a8 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -270,6 +270,8 @@ target_ulong helper_sret(CPURISCVState *env)
 {
     uint64_t mstatus;
     target_ulong prev_priv, prev_virt = env->virt_enabled;
+    const target_ulong src_priv = env->priv;
+    const bool src_virt = env->virt_enabled;
 
     if (!(env->priv >= PRV_S)) {
         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
@@ -339,6 +341,11 @@ target_ulong helper_sret(CPURISCVState *env)
     }
     env->mstatus = set_field(env->mstatus, MSTATUS_SPELP, 0);
 
+    if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) {
+        riscv_ctr_add_entry(env, env->pc, retpc, CTRDATA_TYPE_EXCEP_INT_RET,
+                            src_priv, src_virt);
+    }
+
     return retpc;
 }
 
@@ -416,6 +423,11 @@ target_ulong helper_mret(CPURISCVState *env)
     }
     env->mstatus = set_field(env->mstatus, MSTATUS_MPELP, 0);
 
+    if (riscv_cpu_cfg(env)->ext_smctr || riscv_cpu_cfg(env)->ext_ssctr) {
+        riscv_ctr_add_entry(env, env->pc, retpc, CTRDATA_TYPE_EXCEP_INT_RET,
+                            PRV_M, false);
+    }
+
     return retpc;
 }
 
@@ -466,6 +478,13 @@ target_ulong helper_mnret(CPURISCVState *env)
     return retpc;
 }
 
+void helper_ctr_add_entry(CPURISCVState *env, target_ulong src,
+                          target_ulong dest, target_ulong type)
+{
+    riscv_ctr_add_entry(env, src, dest, (enum CTRType)type,
+                        env->priv, env->virt_enabled);
+}
+
 void helper_wfi(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 698b74f7a8fab0b55616dedb06e46805b34a3743..eaa5d86eaeedd53b2bc27142124129b0fb23674f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -561,6 +561,46 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
     }
 }
 
+#ifndef CONFIG_USER_ONLY
+/*
+ * Direct calls
+ * - jal x1;
+ * - jal x5;
+ * - c.jal.
+ * - cm.jalt.
+ *
+ * Direct jumps
+ * - jal x0;
+ * - c.j;
+ * - cm.jt.
+ *
+ * Other direct jumps
+ * - jal rd where rd != x1 and rd != x5 and rd != x0;
+ */
+static void gen_ctr_jal(DisasContext *ctx, int rd, target_ulong imm)
+{
+    TCGv dest = tcg_temp_new();
+    TCGv src = tcg_temp_new();
+    TCGv type;
+
+    /*
+     * If rd is x1 or x5 link registers, treat this as direct call otherwise
+     * its a direct jump.
+     */
+    if (rd == 1 || rd == 5) {
+        type = tcg_constant_tl(CTRDATA_TYPE_DIRECT_CALL);
+    } else if (rd == 0) {
+        type = tcg_constant_tl(CTRDATA_TYPE_DIRECT_JUMP);
+    } else {
+        type = tcg_constant_tl(CTRDATA_TYPE_OTHER_DIRECT_JUMP);
+    }
+
+    gen_pc_plus_diff(dest, ctx, imm);
+    gen_pc_plus_diff(src, ctx, 0);
+    gen_helper_ctr_add_entry(tcg_env, src, dest, type);
+}
+#endif
+
 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 {
     TCGv succ_pc = dest_gpr(ctx, rd);
@@ -575,6 +615,12 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
         }
     }
 
+#ifndef CONFIG_USER_ONLY
+    if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
+        gen_ctr_jal(ctx, rd, imm);
+    }
+#endif
+
     gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
     gen_set_gpr(ctx, rd, succ_pc);
 

-- 
2.34.1



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v6 5/7] target/riscv: Add CTR sctrclr instruction.
  2025-02-05 11:18 [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
                   ` (3 preceding siblings ...)
  2025-02-05 11:18 ` [PATCH v6 4/7] target/riscv: Add support to record CTR entries Rajnesh Kanwal
@ 2025-02-05 11:18 ` Rajnesh Kanwal
  2025-02-05 11:18 ` [PATCH v6 6/7] target/riscv: machine: Add Control Transfer Record state description Rajnesh Kanwal
                   ` (2 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Rajnesh Kanwal @ 2025-02-05 11:18 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: alistair.francis, bin.meng, liweiwei, dbarboza, zhiwei_liu,
	atishp, apatel, rkanwal, beeman, jason.chien, frank.chang,
	richard.henderson, bmeng.cn

CTR extension adds a new instruction sctrclr to quickly
clear the recorded entries buffer.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                             |  1 +
 target/riscv/cpu_helper.c                      |  7 +++++++
 target/riscv/helper.h                          |  1 +
 target/riscv/insn32.decode                     |  1 +
 target/riscv/insn_trans/trans_privileged.c.inc | 11 ++++++++++
 target/riscv/op_helper.c                       | 29 ++++++++++++++++++++++++++
 6 files changed, 50 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2d8212e2fefe21defb4ca007d894f02592ed3c89..88d47f6b4f19efe74afa51bdd1494706ac382b7b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -618,6 +618,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en);
 
 void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
     enum CTRType type, target_ulong prev_priv, bool prev_virt);
+void riscv_ctr_clear(CPURISCVState *env);
 
 void riscv_translate_init(void);
 void riscv_translate_code(CPUState *cs, TranslationBlock *tb,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index afecc822ae7d07a0904f1ec8c223845bbac92523..6225d42a5688f84eb2229a852f34f4a89b0de9fa 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -887,6 +887,13 @@ static void riscv_ctr_freeze(CPURISCVState *env, uint64_t freeze_mask,
     }
 }
 
+void riscv_ctr_clear(CPURISCVState *env)
+{
+    memset(env->ctr_src, 0x0, sizeof(env->ctr_src));
+    memset(env->ctr_dst, 0x0, sizeof(env->ctr_dst));
+    memset(env->ctr_data, 0x0, sizeof(env->ctr_data));
+}
+
 static uint64_t riscv_ctr_priv_to_mask(target_ulong priv, bool virt)
 {
     switch (priv) {
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 163121ade599f5ec2682ecea25a59b664593fba3..85d73e492d77f839613ecb6dd73cf1ec2a8f1567 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -132,6 +132,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(mnret, tl, env)
+DEF_HELPER_1(ctr_clear, void, env)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a98dab02057648d9dae28eaf9f9ddb00079211e2..6d1a13c82603e47b7c5153389888ceffd13773c9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -114,6 +114,7 @@
 # *** Privileged Instructions ***
 ecall       000000000000     00000 000 00000 1110011
 ebreak      000000000001     00000 000 00000 1110011
+sctrclr     000100000100     00000 000 00000 1110011
 uret        0000000    00010 00000 000 00000 1110011
 sret        0001000    00010 00000 000 00000 1110011
 mret        0011000    00010 00000 000 00000 1110011
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index ca52405d7da411907f1d52234df955940efdc25d..8a62b4cfcd9f9859bc24fbe4594e79d066df5df8 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -75,6 +75,17 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     return true;
 }
 
+static bool trans_sctrclr(DisasContext *ctx, arg_sctrclr *a)
+{
+#ifndef CONFIG_USER_ONLY
+    if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
+        gen_helper_ctr_clear(tcg_env);
+        return true;
+    }
+#endif
+    return false;
+}
+
 static bool trans_uret(DisasContext *ctx, arg_uret *a)
 {
     return false;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 5a99c47b128caf847df76cd1b534f9fdf15a28a8..f156bfab12da6cb4c1e55a4e94592c1d2d0e0e7c 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -485,6 +485,35 @@ void helper_ctr_add_entry(CPURISCVState *env, target_ulong src,
                         env->priv, env->virt_enabled);
 }
 
+void helper_ctr_clear(CPURISCVState *env)
+{
+    /*
+     * It's safe to call smstateen_acc_ok() for umode access regardless of the
+     * state of bit 54 (CTR bit in case of m/hstateen) of sstateen. If the bit
+     * is zero, smstateen_acc_ok() will return the correct exception code and
+     * if it's one, smstateen_acc_ok() will return RISCV_EXCP_NONE. In that
+     * scenario the U-mode check below will handle that case.
+     */
+    RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_CTR);
+    if (ret != RISCV_EXCP_NONE) {
+        riscv_raise_exception(env, ret, GETPC());
+    }
+
+    if (env->priv == PRV_U) {
+        /*
+         * One corner case is when sctrclr is executed from VU-mode and
+         * mstateen.CTR = 0, in which case we are supposed to raise
+         * RISCV_EXCP_ILLEGAL_INST. This case is already handled in
+         * smstateen_acc_ok().
+         */
+        uint32_t excep = env->virt_enabled ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT :
+            RISCV_EXCP_ILLEGAL_INST;
+        riscv_raise_exception(env, excep, GETPC());
+    }
+
+    riscv_ctr_clear(env);
+}
+
 void helper_wfi(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);

-- 
2.34.1



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v6 6/7] target/riscv: machine: Add Control Transfer Record state description
  2025-02-05 11:18 [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
                   ` (4 preceding siblings ...)
  2025-02-05 11:18 ` [PATCH v6 5/7] target/riscv: Add CTR sctrclr instruction Rajnesh Kanwal
@ 2025-02-05 11:18 ` Rajnesh Kanwal
  2025-02-05 11:18 ` [PATCH v6 7/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs Rajnesh Kanwal
  2025-02-06  5:38 ` [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Alistair Francis
  7 siblings, 0 replies; 12+ messages in thread
From: Rajnesh Kanwal @ 2025-02-05 11:18 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: alistair.francis, bin.meng, liweiwei, dbarboza, zhiwei_liu,
	atishp, apatel, rkanwal, beeman, jason.chien, frank.chang,
	richard.henderson, bmeng.cn

Add a subsection to machine.c to migrate CTR CSR state

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/machine.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index d8445244ab251e23c07877d9f2a7c1c08f09d736..889e2b6570132950c25df6395794875df604cd11 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -300,6 +300,30 @@ static const VMStateDescription vmstate_envcfg = {
     }
 };
 
+static bool ctr_needed(void *opaque)
+{
+    RISCVCPU *cpu = opaque;
+
+    return cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr;
+}
+
+static const VMStateDescription vmstate_ctr = {
+    .name = "cpu/ctr",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = ctr_needed,
+    .fields = (const VMStateField[]) {
+        VMSTATE_UINT64(env.mctrctl, RISCVCPU),
+        VMSTATE_UINT32(env.sctrdepth, RISCVCPU),
+        VMSTATE_UINT32(env.sctrstatus, RISCVCPU),
+        VMSTATE_UINT64(env.vsctrctl, RISCVCPU),
+        VMSTATE_UINT64_ARRAY(env.ctr_src, RISCVCPU, 16 << SCTRDEPTH_MAX),
+        VMSTATE_UINT64_ARRAY(env.ctr_dst, RISCVCPU, 16 << SCTRDEPTH_MAX),
+        VMSTATE_UINT64_ARRAY(env.ctr_data, RISCVCPU, 16 << SCTRDEPTH_MAX),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static bool pmu_needed(void *opaque)
 {
     RISCVCPU *cpu = opaque;
@@ -450,6 +474,7 @@ const VMStateDescription vmstate_riscv_cpu = {
         &vmstate_jvt,
         &vmstate_elp,
         &vmstate_ssp,
+        &vmstate_ctr,
         NULL
     }
 };

-- 
2.34.1



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v6 7/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
  2025-02-05 11:18 [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
                   ` (5 preceding siblings ...)
  2025-02-05 11:18 ` [PATCH v6 6/7] target/riscv: machine: Add Control Transfer Record state description Rajnesh Kanwal
@ 2025-02-05 11:18 ` Rajnesh Kanwal
  2025-02-06  5:38 ` [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Alistair Francis
  7 siblings, 0 replies; 12+ messages in thread
From: Rajnesh Kanwal @ 2025-02-05 11:18 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: alistair.francis, bin.meng, liweiwei, dbarboza, zhiwei_liu,
	atishp, apatel, rkanwal, beeman, jason.chien, frank.chang,
	richard.henderson, bmeng.cn

CTR entries are accessed using ctrsource, ctrtarget and ctrdata
registers using smcsrind/sscsrind extension. This commits extends
the csrind extension to support CTR registers.

ctrsource is accessible through xireg CSR, ctrtarget is accessible
through xireg1 and ctrdata is accessible through xireg2 CSR.

CTR supports maximum depth of 256 entries which are accessed using
xiselect range 0x200 to 0x2ff.

This commits also adds properties to enable CTR extension. CTR can be
enabled using smctr=true and ssctr=true now.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         |  26 +++++++-
 target/riscv/csr.c         | 150 ++++++++++++++++++++++++++++++++++++++++++++-
 target/riscv/tcg/tcg-cpu.c |  11 ++++
 3 files changed, 185 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3d4bd157d2cc56ca67eac10a7b62089ea8252b7d..b37769567e88b0221733ef180d9559119c1ecba4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -215,6 +215,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm),
     ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
+    ISA_EXT_DATA_ENTRY(smctr, PRIV_VERSION_1_12_0, ext_smctr),
+    ISA_EXT_DATA_ENTRY(ssctr, PRIV_VERSION_1_12_0, ext_ssctr),
     ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
     ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
     ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
@@ -1598,6 +1600,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false),
     MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false),
     MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false),
+    MULTI_EXT_CFG_BOOL("smctr", ext_smctr, false),
+    MULTI_EXT_CFG_BOOL("ssctr", ext_ssctr, false),
     MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
     MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false),
     MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false),
@@ -2803,6 +2807,26 @@ static RISCVCPUImpliedExtsRule SSPM_IMPLIED = {
     },
 };
 
+static RISCVCPUImpliedExtsRule SMCTR_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_smctr),
+    .implied_misa_exts = RVS,
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_sscsrind),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
+static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = {
+    .ext = CPU_CFG_OFFSET(ext_ssctr),
+    .implied_misa_exts = RVS,
+    .implied_multi_exts = {
+        CPU_CFG_OFFSET(ext_sscsrind),
+
+        RISCV_IMPLIED_EXTS_RULE_END
+    },
+};
+
 RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
     &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
     &RVM_IMPLIED, &RVV_IMPLIED, NULL
@@ -2821,7 +2845,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
     &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
     &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
     &ZVKS_IMPLIED,  &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED,
-    &SUPM_IMPLIED, &SSPM_IMPLIED,
+    &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, &SSCTR_IMPLIED,
     NULL
 };
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 07a591fc90a8a516888dd465292f4e4b4178524d..e2754ac7778a28dc38307da7bb6726ea3025cb4d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2431,6 +2431,13 @@ static bool xiselect_cd_range(target_ulong isel)
     return (ISELECT_CD_FIRST <= isel && isel <= ISELECT_CD_LAST);
 }
 
+static bool xiselect_ctr_range(int csrno, target_ulong isel)
+{
+    /* MIREG-MIREG6 for the range 0x200-0x2ff are not used by CTR. */
+    return CTR_ENTRIES_FIRST <= isel && isel <= CTR_ENTRIES_LAST &&
+           csrno < CSR_MIREG;
+}
+
 static int rmw_iprio(target_ulong xlen,
                      target_ulong iselect, uint8_t *iprio,
                      target_ulong *val, target_ulong new_val,
@@ -2476,6 +2483,124 @@ static int rmw_iprio(target_ulong xlen,
     return 0;
 }
 
+static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *val,
+                          target_ulong new_val, target_ulong wr_mask)
+{
+    /*
+     * CTR arrays are treated as circular buffers and TOS always points to next
+     * empty slot, keeping TOS - 1 always pointing to latest entry. Given entry
+     * 0 is always the latest one, traversal is a bit different here. See the
+     * below example.
+     *
+     * Depth = 16.
+     *
+     * idx    [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
+     * TOS                                 H
+     * entry   6   5   4   3   2   1   0   F   E   D   C   B   A   9   8   7
+     */
+    const uint64_t entry = isel - CTR_ENTRIES_FIRST;
+    const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
+    uint64_t idx;
+
+    /* Entry greater than depth-1 is read-only zero */
+    if (entry >= depth) {
+        if (val) {
+            *val = 0;
+        }
+        return 0;
+    }
+
+    idx = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
+    idx = (idx - entry - 1) & (depth - 1);
+
+    if (val) {
+        *val = env->ctr_src[idx];
+    }
+
+    env->ctr_src[idx] = (env->ctr_src[idx] & ~wr_mask) | (new_val & wr_mask);
+
+    return 0;
+}
+
+static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *val,
+                          target_ulong new_val, target_ulong wr_mask)
+{
+    /*
+     * CTR arrays are treated as circular buffers and TOS always points to next
+     * empty slot, keeping TOS - 1 always pointing to latest entry. Given entry
+     * 0 is always the latest one, traversal is a bit different here. See the
+     * below example.
+     *
+     * Depth = 16.
+     *
+     * idx    [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
+     * head                                H
+     * entry   6   5   4   3   2   1   0   F   E   D   C   B   A   9   8   7
+     */
+    const uint64_t entry = isel - CTR_ENTRIES_FIRST;
+    const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
+    uint64_t idx;
+
+    /* Entry greater than depth-1 is read-only zero */
+    if (entry >= depth) {
+        if (val) {
+            *val = 0;
+        }
+        return 0;
+    }
+
+    idx = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
+    idx = (idx - entry - 1) & (depth - 1);
+
+    if (val) {
+        *val = env->ctr_dst[idx];
+    }
+
+    env->ctr_dst[idx] = (env->ctr_dst[idx] & ~wr_mask) | (new_val & wr_mask);
+
+    return 0;
+}
+
+static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val,
+                        target_ulong new_val, target_ulong wr_mask)
+{
+    /*
+     * CTR arrays are treated as circular buffers and TOS always points to next
+     * empty slot, keeping TOS - 1 always pointing to latest entry. Given entry
+     * 0 is always the latest one, traversal is a bit different here. See the
+     * below example.
+     *
+     * Depth = 16.
+     *
+     * idx    [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
+     * head                                H
+     * entry   6   5   4   3   2   1   0   F   E   D   C   B   A   9   8   7
+     */
+    const uint64_t entry = isel - CTR_ENTRIES_FIRST;
+    const uint64_t mask = wr_mask & CTRDATA_MASK;
+    const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
+    uint64_t idx;
+
+    /* Entry greater than depth-1 is read-only zero */
+    if (entry >= depth) {
+        if (val) {
+            *val = 0;
+        }
+        return 0;
+    }
+
+    idx = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
+    idx = (idx - entry - 1) & (depth - 1);
+
+    if (val) {
+        *val = env->ctr_data[idx];
+    }
+
+    env->ctr_data[idx] = (env->ctr_data[idx] & ~mask) | (new_val & mask);
+
+    return 0;
+}
+
 static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno,
                          target_ulong isel, target_ulong *val,
                          target_ulong new_val, target_ulong wr_mask)
@@ -2628,6 +2753,27 @@ done:
     return ret;
 }
 
+static int rmw_xireg_ctr(CPURISCVState *env, int csrno,
+                        target_ulong isel, target_ulong *val,
+                        target_ulong new_val, target_ulong wr_mask)
+{
+    if (!riscv_cpu_cfg(env)->ext_smctr && !riscv_cpu_cfg(env)->ext_ssctr) {
+        return -EINVAL;
+    }
+
+    if (csrno == CSR_SIREG || csrno == CSR_VSIREG) {
+        return rmw_ctrsource(env, isel, val, new_val, wr_mask);
+    } else if (csrno == CSR_SIREG2 || csrno == CSR_VSIREG2) {
+        return rmw_ctrtarget(env, isel, val, new_val, wr_mask);
+    } else if (csrno == CSR_SIREG3 || csrno == CSR_VSIREG3) {
+        return rmw_ctrdata(env, isel, val, new_val, wr_mask);
+    } else if (val) {
+        *val = 0;
+    }
+
+    return 0;
+}
+
 /*
  * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6
  *
@@ -2639,11 +2785,13 @@ static int rmw_xireg_csrind(CPURISCVState *env, int csrno,
                               target_ulong isel, target_ulong *val,
                               target_ulong new_val, target_ulong wr_mask)
 {
-    int ret = -EINVAL;
     bool virt = csrno == CSR_VSIREG ? true : false;
+    int ret = -EINVAL;
 
     if (xiselect_cd_range(isel)) {
         ret = rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask);
+    } else if (xiselect_ctr_range(csrno, isel)) {
+        ret = rmw_xireg_ctr(env, csrno, isel, val, new_val, wr_mask);
     } else {
         /*
          * As per the specification, access to unimplented region is undefined
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 0a137281de15f030678aae034c24ca2382ca6e3a..96b586fe3c0b573076f1af061911dcafe06f129f 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -681,6 +681,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
+    if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) &&
+        (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) {
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) ||
+            cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) {
+            error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind");
+            return;
+        }
+        cpu->cfg.ext_smctr = false;
+        cpu->cfg.ext_ssctr = false;
+    }
+
     /*
      * Disable isa extensions based on priv spec after we
      * validated and set everything we need.

-- 
2.34.1



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.
  2025-02-05 11:18 [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
                   ` (6 preceding siblings ...)
  2025-02-05 11:18 ` [PATCH v6 7/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs Rajnesh Kanwal
@ 2025-02-06  5:38 ` Alistair Francis
  2025-02-06 11:45   ` Rajnesh Kanwal
  7 siblings, 1 reply; 12+ messages in thread
From: Alistair Francis @ 2025-02-06  5:38 UTC (permalink / raw)
  To: Rajnesh Kanwal
  Cc: qemu-riscv, qemu-devel, alistair.francis, bin.meng, liweiwei,
	dbarboza, zhiwei_liu, atishp, apatel, beeman, jason.chien,
	frank.chang, richard.henderson, bmeng.cn

On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
>
> This series enables Control Transfer Records extension support on riscv
> platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
> The Extension has been ratified and this series is based on v1.0 [0]
>
> CTR extension depends on both the implementation of S-mode and Sscsrind
> extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs using
> sscsrind extension.
>
> The series is based on Smcdeleg/Ssccfg counter delegation extension [2]
> patches [3]. CTR itself doesn't depend on counter delegation support. This
> rebase is basically to include the Smcsrind patches.
>
> Here is the link to a quick start guide [4] to setup and run a basic perf demo
> on Linux to use CTR Ext.
>
> Qemu patches can be found here:
> https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v6
>
> Opensbi patch can be found here:
> https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2
>
> Linux kernel patches can be found here:
> https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v2
>
> [0]: https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0
> [1]: https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0
> [2]: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0
> [3]: https://lore.kernel.org/qemu-riscv/20241203-counter_delegation-v4-0-c12a89baed86@rivosinc.com/
> [4]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine
>
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> ---
> Changelog:
> v6: Rebased on latest riscv-to-apply.for-upstream.

It should be rebased on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next

I applied the first 6 patches as they apply cleanly

Alistair

>
> v5: Improvements based on Richard Henderson's feedback.
>   - Fixed code gen logic to use gen_update_pc() instead of
>     tcg_constant_tl().
>   - Some function renaming.
>   - Rebased onto v4 of counter delegation series.
>   - https://lore.kernel.org/qemu-riscv/20241205-b4-ctr_upstream_v3-v5-0-60b993aa567d@rivosinc.com/
>
> v4: Improvements based on Richard Henderson's feedback.
>   - Refactored CTR related code generation to move more code into
>     translation side and avoid unnecessary code execution in generated
>     code.
>   - Added missing code in machine.c to migrate the new state.
>   - https://lore.kernel.org/r/20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com
>
> v3: Improvements based on Jason Chien and Frank Chang's feedback.
>   - Created single set of MACROs for CTR CSRs in cpu_bit.h
>   - Some fixes in riscv_ctr_add_entry.
>   - Return zero for vs/sireg4-6 for CTR 0x200 to 0x2ff range.
>   - Improved extension dependency check.
>   - Fixed invalid ctrctl csr selection bug in riscv_ctr_freeze.
>   - Added implied rules for Smctr and Ssctr.
>   - Added missing SMSTATEEN0_CTR bit in mstateen0 and hstateen0 write ops.
>   - Some more cosmetic changes.
>   - https://lore.kernel.org/qemu-riscv/20241104-b4-ctr_upstream_v3-v3-0-32fd3c48205f@rivosinc.com/
>
> v2: Lots of improvements based on Jason Chien's feedback including:
>   - Added CTR recording for cm.jalt, cm.jt, cm.popret, cm.popretz.
>   - Fixed and added more CTR extension enable checks.
>   - Fixed CTR CSR predicate functions.
>   - Fixed external trap xTE bit checks.
>   - One fix in freeze function for VS-mode.
>   - Lots of minor code improvements.
>   - Added checks in sctrclr instruction helper.
>   - https://lore.kernel.org/qemu-riscv/20240619152708.135991-1-rkanwal@rivosinc.com/
>
> v1:
>   - https://lore.kernel.org/qemu-riscv/20240529160950.132754-1-rkanwal@rivosinc.com/
>
> ---
> Rajnesh Kanwal (7):
>       target/riscv: Remove obsolete sfence.vm instruction
>       target/riscv: Add Control Transfer Records CSR definitions.
>       target/riscv: Add support for Control Transfer Records extension CSRs.
>       target/riscv: Add support to record CTR entries.
>       target/riscv: Add CTR sctrclr instruction.
>       target/riscv: machine: Add Control Transfer Record state description
>       target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
>
>  target/riscv/cpu.c                             |  26 ++-
>  target/riscv/cpu.h                             |  13 ++
>  target/riscv/cpu_bits.h                        | 145 ++++++++++++
>  target/riscv/cpu_cfg.h                         |   2 +
>  target/riscv/cpu_helper.c                      | 266 ++++++++++++++++++++++
>  target/riscv/csr.c                             | 294 ++++++++++++++++++++++++-
>  target/riscv/helper.h                          |   2 +
>  target/riscv/insn32.decode                     |   2 +-
>  target/riscv/insn_trans/trans_privileged.c.inc |  18 +-
>  target/riscv/insn_trans/trans_rvi.c.inc        |  75 +++++++
>  target/riscv/insn_trans/trans_rvzce.c.inc      |  21 ++
>  target/riscv/machine.c                         |  25 +++
>  target/riscv/op_helper.c                       |  48 ++++
>  target/riscv/tcg/tcg-cpu.c                     |  11 +
>  target/riscv/translate.c                       |  46 ++++
>  15 files changed, 986 insertions(+), 8 deletions(-)
> ---
> base-commit: 699291ba7774f1580584cd96f84ceda8cc4edb7e
> change-id: 20250205-b4-ctr_upstream_v6-71418cd245ee
> --
> Best Regards,
> Rajnesh Kanwal
>
>


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.
  2025-02-06  5:38 ` [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Alistair Francis
@ 2025-02-06 11:45   ` Rajnesh Kanwal
  2025-02-10  4:11     ` Alistair Francis
  0 siblings, 1 reply; 12+ messages in thread
From: Rajnesh Kanwal @ 2025-02-06 11:45 UTC (permalink / raw)
  To: Alistair Francis
  Cc: qemu-riscv, qemu-devel, alistair.francis, bin.meng, liweiwei,
	dbarboza, zhiwei_liu, atishp, apatel, beeman, jason.chien,
	frank.chang, richard.henderson, bmeng.cn

On Thu, Feb 6, 2025 at 5:39 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
> >
> > This series enables Control Transfer Records extension support on riscv
> > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
> > The Extension has been ratified and this series is based on v1.0 [0]
> >
> > CTR extension depends on both the implementation of S-mode and Sscsrind
> > extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs using
> > sscsrind extension.
> >
> > The series is based on Smcdeleg/Ssccfg counter delegation extension [2]
> > patches [3]. CTR itself doesn't depend on counter delegation support. This
> > rebase is basically to include the Smcsrind patches.
> >
> > Here is the link to a quick start guide [4] to setup and run a basic perf demo
> > on Linux to use CTR Ext.
> >
> > Qemu patches can be found here:
> > https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v6
> >
> > Opensbi patch can be found here:
> > https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2
> >
> > Linux kernel patches can be found here:
> > https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v2
> >
> > [0]: https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0
> > [1]: https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0
> > [2]: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0
> > [3]: https://lore.kernel.org/qemu-riscv/20241203-counter_delegation-v4-0-c12a89baed86@rivosinc.com/
> > [4]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine
> >
> > Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> > ---
> > Changelog:
> > v6: Rebased on latest riscv-to-apply.for-upstream.
>
> It should be rebased on
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next
>
> I applied the first 6 patches as they apply cleanly
>
> Alistair
>

Sorry for the inconvenience. Strangely cherry-pick, patch and git am -3
all seem to work fine but git am seems to be failing.

I looked into the conflict and it looks like am expects
ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
but gets this in cpu.c.
ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12),

I have tried following cmds on top of riscv-to-apply.next and these
fetch the last patch
only and apply the last patch perfectly fine.

b4 am -i  -P="-1" 20250205-b4-ctr_upstream_v6-v6-0-439d8e06c8ef@rivosinc.com
git am -3 ./v6_20250205_rkanwal_target_riscv_add_support_for_control_transfer_records_ext.mbx

If you want I can send v7 as well rebased on top of riscv-to-apply.next.

Thanks
Rajnesh

> >
> > v5: Improvements based on Richard Henderson's feedback.
> >   - Fixed code gen logic to use gen_update_pc() instead of
> >     tcg_constant_tl().
> >   - Some function renaming.
> >   - Rebased onto v4 of counter delegation series.
> >   - https://lore.kernel.org/qemu-riscv/20241205-b4-ctr_upstream_v3-v5-0-60b993aa567d@rivosinc.com/
> >
> > v4: Improvements based on Richard Henderson's feedback.
> >   - Refactored CTR related code generation to move more code into
> >     translation side and avoid unnecessary code execution in generated
> >     code.
> >   - Added missing code in machine.c to migrate the new state.
> >   - https://lore.kernel.org/r/20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com
> >
> > v3: Improvements based on Jason Chien and Frank Chang's feedback.
> >   - Created single set of MACROs for CTR CSRs in cpu_bit.h
> >   - Some fixes in riscv_ctr_add_entry.
> >   - Return zero for vs/sireg4-6 for CTR 0x200 to 0x2ff range.
> >   - Improved extension dependency check.
> >   - Fixed invalid ctrctl csr selection bug in riscv_ctr_freeze.
> >   - Added implied rules for Smctr and Ssctr.
> >   - Added missing SMSTATEEN0_CTR bit in mstateen0 and hstateen0 write ops.
> >   - Some more cosmetic changes.
> >   - https://lore.kernel.org/qemu-riscv/20241104-b4-ctr_upstream_v3-v3-0-32fd3c48205f@rivosinc.com/
> >
> > v2: Lots of improvements based on Jason Chien's feedback including:
> >   - Added CTR recording for cm.jalt, cm.jt, cm.popret, cm.popretz.
> >   - Fixed and added more CTR extension enable checks.
> >   - Fixed CTR CSR predicate functions.
> >   - Fixed external trap xTE bit checks.
> >   - One fix in freeze function for VS-mode.
> >   - Lots of minor code improvements.
> >   - Added checks in sctrclr instruction helper.
> >   - https://lore.kernel.org/qemu-riscv/20240619152708.135991-1-rkanwal@rivosinc.com/
> >
> > v1:
> >   - https://lore.kernel.org/qemu-riscv/20240529160950.132754-1-rkanwal@rivosinc.com/
> >
> > ---
> > Rajnesh Kanwal (7):
> >       target/riscv: Remove obsolete sfence.vm instruction
> >       target/riscv: Add Control Transfer Records CSR definitions.
> >       target/riscv: Add support for Control Transfer Records extension CSRs.
> >       target/riscv: Add support to record CTR entries.
> >       target/riscv: Add CTR sctrclr instruction.
> >       target/riscv: machine: Add Control Transfer Record state description
> >       target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
> >
> >  target/riscv/cpu.c                             |  26 ++-
> >  target/riscv/cpu.h                             |  13 ++
> >  target/riscv/cpu_bits.h                        | 145 ++++++++++++
> >  target/riscv/cpu_cfg.h                         |   2 +
> >  target/riscv/cpu_helper.c                      | 266 ++++++++++++++++++++++
> >  target/riscv/csr.c                             | 294 ++++++++++++++++++++++++-
> >  target/riscv/helper.h                          |   2 +
> >  target/riscv/insn32.decode                     |   2 +-
> >  target/riscv/insn_trans/trans_privileged.c.inc |  18 +-
> >  target/riscv/insn_trans/trans_rvi.c.inc        |  75 +++++++
> >  target/riscv/insn_trans/trans_rvzce.c.inc      |  21 ++
> >  target/riscv/machine.c                         |  25 +++
> >  target/riscv/op_helper.c                       |  48 ++++
> >  target/riscv/tcg/tcg-cpu.c                     |  11 +
> >  target/riscv/translate.c                       |  46 ++++
> >  15 files changed, 986 insertions(+), 8 deletions(-)
> > ---
> > base-commit: 699291ba7774f1580584cd96f84ceda8cc4edb7e
> > change-id: 20250205-b4-ctr_upstream_v6-71418cd245ee
> > --
> > Best Regards,
> > Rajnesh Kanwal
> >
> >


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.
  2025-02-06 11:45   ` Rajnesh Kanwal
@ 2025-02-10  4:11     ` Alistair Francis
  2025-02-12 16:46       ` Rajnesh Kanwal
  0 siblings, 1 reply; 12+ messages in thread
From: Alistair Francis @ 2025-02-10  4:11 UTC (permalink / raw)
  To: Rajnesh Kanwal
  Cc: qemu-riscv, qemu-devel, alistair.francis, bin.meng, liweiwei,
	dbarboza, zhiwei_liu, atishp, apatel, beeman, jason.chien,
	frank.chang, richard.henderson, bmeng.cn

On Thu, Feb 6, 2025 at 9:45 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
>
> On Thu, Feb 6, 2025 at 5:39 AM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
> > >
> > > This series enables Control Transfer Records extension support on riscv
> > > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
> > > The Extension has been ratified and this series is based on v1.0 [0]
> > >
> > > CTR extension depends on both the implementation of S-mode and Sscsrind
> > > extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs using
> > > sscsrind extension.
> > >
> > > The series is based on Smcdeleg/Ssccfg counter delegation extension [2]
> > > patches [3]. CTR itself doesn't depend on counter delegation support. This
> > > rebase is basically to include the Smcsrind patches.
> > >
> > > Here is the link to a quick start guide [4] to setup and run a basic perf demo
> > > on Linux to use CTR Ext.
> > >
> > > Qemu patches can be found here:
> > > https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v6
> > >
> > > Opensbi patch can be found here:
> > > https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2
> > >
> > > Linux kernel patches can be found here:
> > > https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v2
> > >
> > > [0]: https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0
> > > [1]: https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0
> > > [2]: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0
> > > [3]: https://lore.kernel.org/qemu-riscv/20241203-counter_delegation-v4-0-c12a89baed86@rivosinc.com/
> > > [4]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine
> > >
> > > Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> > > ---
> > > Changelog:
> > > v6: Rebased on latest riscv-to-apply.for-upstream.
> >
> > It should be rebased on
> > https://github.com/alistair23/qemu/tree/riscv-to-apply.next
> >
> > I applied the first 6 patches as they apply cleanly
> >
> > Alistair
> >
>
> Sorry for the inconvenience. Strangely cherry-pick, patch and git am -3
> all seem to work fine but git am seems to be failing.
>
> I looked into the conflict and it looks like am expects
> ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
> but gets this in cpu.c.
> ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12),
>
> I have tried following cmds on top of riscv-to-apply.next and these
> fetch the last patch
> only and apply the last patch perfectly fine.
>
> b4 am -i  -P="-1" 20250205-b4-ctr_upstream_v6-v6-0-439d8e06c8ef@rivosinc.com
> git am -3 ./v6_20250205_rkanwal_target_riscv_add_support_for_control_transfer_records_ext.mbx

The threeway merge is failing for me

>
> If you want I can send v7 as well rebased on top of riscv-to-apply.next.

Yes please :)

Alistair

>
> Thanks
> Rajnesh
>
> > >
> > > v5: Improvements based on Richard Henderson's feedback.
> > >   - Fixed code gen logic to use gen_update_pc() instead of
> > >     tcg_constant_tl().
> > >   - Some function renaming.
> > >   - Rebased onto v4 of counter delegation series.
> > >   - https://lore.kernel.org/qemu-riscv/20241205-b4-ctr_upstream_v3-v5-0-60b993aa567d@rivosinc.com/
> > >
> > > v4: Improvements based on Richard Henderson's feedback.
> > >   - Refactored CTR related code generation to move more code into
> > >     translation side and avoid unnecessary code execution in generated
> > >     code.
> > >   - Added missing code in machine.c to migrate the new state.
> > >   - https://lore.kernel.org/r/20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com
> > >
> > > v3: Improvements based on Jason Chien and Frank Chang's feedback.
> > >   - Created single set of MACROs for CTR CSRs in cpu_bit.h
> > >   - Some fixes in riscv_ctr_add_entry.
> > >   - Return zero for vs/sireg4-6 for CTR 0x200 to 0x2ff range.
> > >   - Improved extension dependency check.
> > >   - Fixed invalid ctrctl csr selection bug in riscv_ctr_freeze.
> > >   - Added implied rules for Smctr and Ssctr.
> > >   - Added missing SMSTATEEN0_CTR bit in mstateen0 and hstateen0 write ops.
> > >   - Some more cosmetic changes.
> > >   - https://lore.kernel.org/qemu-riscv/20241104-b4-ctr_upstream_v3-v3-0-32fd3c48205f@rivosinc.com/
> > >
> > > v2: Lots of improvements based on Jason Chien's feedback including:
> > >   - Added CTR recording for cm.jalt, cm.jt, cm.popret, cm.popretz.
> > >   - Fixed and added more CTR extension enable checks.
> > >   - Fixed CTR CSR predicate functions.
> > >   - Fixed external trap xTE bit checks.
> > >   - One fix in freeze function for VS-mode.
> > >   - Lots of minor code improvements.
> > >   - Added checks in sctrclr instruction helper.
> > >   - https://lore.kernel.org/qemu-riscv/20240619152708.135991-1-rkanwal@rivosinc.com/
> > >
> > > v1:
> > >   - https://lore.kernel.org/qemu-riscv/20240529160950.132754-1-rkanwal@rivosinc.com/
> > >
> > > ---
> > > Rajnesh Kanwal (7):
> > >       target/riscv: Remove obsolete sfence.vm instruction
> > >       target/riscv: Add Control Transfer Records CSR definitions.
> > >       target/riscv: Add support for Control Transfer Records extension CSRs.
> > >       target/riscv: Add support to record CTR entries.
> > >       target/riscv: Add CTR sctrclr instruction.
> > >       target/riscv: machine: Add Control Transfer Record state description
> > >       target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
> > >
> > >  target/riscv/cpu.c                             |  26 ++-
> > >  target/riscv/cpu.h                             |  13 ++
> > >  target/riscv/cpu_bits.h                        | 145 ++++++++++++
> > >  target/riscv/cpu_cfg.h                         |   2 +
> > >  target/riscv/cpu_helper.c                      | 266 ++++++++++++++++++++++
> > >  target/riscv/csr.c                             | 294 ++++++++++++++++++++++++-
> > >  target/riscv/helper.h                          |   2 +
> > >  target/riscv/insn32.decode                     |   2 +-
> > >  target/riscv/insn_trans/trans_privileged.c.inc |  18 +-
> > >  target/riscv/insn_trans/trans_rvi.c.inc        |  75 +++++++
> > >  target/riscv/insn_trans/trans_rvzce.c.inc      |  21 ++
> > >  target/riscv/machine.c                         |  25 +++
> > >  target/riscv/op_helper.c                       |  48 ++++
> > >  target/riscv/tcg/tcg-cpu.c                     |  11 +
> > >  target/riscv/translate.c                       |  46 ++++
> > >  15 files changed, 986 insertions(+), 8 deletions(-)
> > > ---
> > > base-commit: 699291ba7774f1580584cd96f84ceda8cc4edb7e
> > > change-id: 20250205-b4-ctr_upstream_v6-71418cd245ee
> > > --
> > > Best Regards,
> > > Rajnesh Kanwal
> > >
> > >


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext.
  2025-02-10  4:11     ` Alistair Francis
@ 2025-02-12 16:46       ` Rajnesh Kanwal
  0 siblings, 0 replies; 12+ messages in thread
From: Rajnesh Kanwal @ 2025-02-12 16:46 UTC (permalink / raw)
  To: Alistair Francis
  Cc: qemu-riscv, qemu-devel, alistair.francis, bin.meng, liweiwei,
	dbarboza, zhiwei_liu, atishp, apatel, beeman, jason.chien,
	frank.chang, richard.henderson, bmeng.cn

On Mon, Feb 10, 2025 at 4:11 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Thu, Feb 6, 2025 at 9:45 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
> >
> > On Thu, Feb 6, 2025 at 5:39 AM Alistair Francis <alistair23@gmail.com> wrote:
> > >
> > > On Wed, Feb 5, 2025 at 9:21 PM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
> > > >
> > > > This series enables Control Transfer Records extension support on riscv
> > > > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
> > > > The Extension has been ratified and this series is based on v1.0 [0]
> > > >
> > > > CTR extension depends on both the implementation of S-mode and Sscsrind
> > > > extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs using
> > > > sscsrind extension.
> > > >
> > > > The series is based on Smcdeleg/Ssccfg counter delegation extension [2]
> > > > patches [3]. CTR itself doesn't depend on counter delegation support. This
> > > > rebase is basically to include the Smcsrind patches.
> > > >
> > > > Here is the link to a quick start guide [4] to setup and run a basic perf demo
> > > > on Linux to use CTR Ext.
> > > >
> > > > Qemu patches can be found here:
> > > > https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v6
> > > >
> > > > Opensbi patch can be found here:
> > > > https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2
> > > >
> > > > Linux kernel patches can be found here:
> > > > https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v2
> > > >
> > > > [0]: https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0
> > > > [1]: https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0
> > > > [2]: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0
> > > > [3]: https://lore.kernel.org/qemu-riscv/20241203-counter_delegation-v4-0-c12a89baed86@rivosinc.com/
> > > > [4]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine
> > > >
> > > > Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
> > > > ---
> > > > Changelog:
> > > > v6: Rebased on latest riscv-to-apply.for-upstream.
> > >
> > > It should be rebased on
> > > https://github.com/alistair23/qemu/tree/riscv-to-apply.next
> > >
> > > I applied the first 6 patches as they apply cleanly
> > >
> > > Alistair
> > >
> >
> > Sorry for the inconvenience. Strangely cherry-pick, patch and git am -3
> > all seem to work fine but git am seems to be failing.
> >
> > I looked into the conflict and it looks like am expects
> > ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
> > but gets this in cpu.c.
> > ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12),
> >
> > I have tried following cmds on top of riscv-to-apply.next and these
> > fetch the last patch
> > only and apply the last patch perfectly fine.
> >
> > b4 am -i  -P="-1" 20250205-b4-ctr_upstream_v6-v6-0-439d8e06c8ef@rivosinc.com
> > git am -3 ./v6_20250205_rkanwal_target_riscv_add_support_for_control_transfer_records_ext.mbx
>
> The threeway merge is failing for me
>
> >
> > If you want I can send v7 as well rebased on top of riscv-to-apply.next.
>
> Yes please :)
>
> Alistair
>

Here is the link to v7.
https://lore.kernel.org/qemu-riscv/20250212-b4-ctr_upstream_v6-v7-1-4e8159ea33bf@rivosinc.com/

Thanks
Rajnesh

> >
> > Thanks
> > Rajnesh
> >
> > > >
> > > > v5: Improvements based on Richard Henderson's feedback.
> > > >   - Fixed code gen logic to use gen_update_pc() instead of
> > > >     tcg_constant_tl().
> > > >   - Some function renaming.
> > > >   - Rebased onto v4 of counter delegation series.
> > > >   - https://lore.kernel.org/qemu-riscv/20241205-b4-ctr_upstream_v3-v5-0-60b993aa567d@rivosinc.com/
> > > >
> > > > v4: Improvements based on Richard Henderson's feedback.
> > > >   - Refactored CTR related code generation to move more code into
> > > >     translation side and avoid unnecessary code execution in generated
> > > >     code.
> > > >   - Added missing code in machine.c to migrate the new state.
> > > >   - https://lore.kernel.org/r/20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com
> > > >
> > > > v3: Improvements based on Jason Chien and Frank Chang's feedback.
> > > >   - Created single set of MACROs for CTR CSRs in cpu_bit.h
> > > >   - Some fixes in riscv_ctr_add_entry.
> > > >   - Return zero for vs/sireg4-6 for CTR 0x200 to 0x2ff range.
> > > >   - Improved extension dependency check.
> > > >   - Fixed invalid ctrctl csr selection bug in riscv_ctr_freeze.
> > > >   - Added implied rules for Smctr and Ssctr.
> > > >   - Added missing SMSTATEEN0_CTR bit in mstateen0 and hstateen0 write ops.
> > > >   - Some more cosmetic changes.
> > > >   - https://lore.kernel.org/qemu-riscv/20241104-b4-ctr_upstream_v3-v3-0-32fd3c48205f@rivosinc.com/
> > > >
> > > > v2: Lots of improvements based on Jason Chien's feedback including:
> > > >   - Added CTR recording for cm.jalt, cm.jt, cm.popret, cm.popretz.
> > > >   - Fixed and added more CTR extension enable checks.
> > > >   - Fixed CTR CSR predicate functions.
> > > >   - Fixed external trap xTE bit checks.
> > > >   - One fix in freeze function for VS-mode.
> > > >   - Lots of minor code improvements.
> > > >   - Added checks in sctrclr instruction helper.
> > > >   - https://lore.kernel.org/qemu-riscv/20240619152708.135991-1-rkanwal@rivosinc.com/
> > > >
> > > > v1:
> > > >   - https://lore.kernel.org/qemu-riscv/20240529160950.132754-1-rkanwal@rivosinc.com/
> > > >
> > > > ---
> > > > Rajnesh Kanwal (7):
> > > >       target/riscv: Remove obsolete sfence.vm instruction
> > > >       target/riscv: Add Control Transfer Records CSR definitions.
> > > >       target/riscv: Add support for Control Transfer Records extension CSRs.
> > > >       target/riscv: Add support to record CTR entries.
> > > >       target/riscv: Add CTR sctrclr instruction.
> > > >       target/riscv: machine: Add Control Transfer Record state description
> > > >       target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
> > > >
> > > >  target/riscv/cpu.c                             |  26 ++-
> > > >  target/riscv/cpu.h                             |  13 ++
> > > >  target/riscv/cpu_bits.h                        | 145 ++++++++++++
> > > >  target/riscv/cpu_cfg.h                         |   2 +
> > > >  target/riscv/cpu_helper.c                      | 266 ++++++++++++++++++++++
> > > >  target/riscv/csr.c                             | 294 ++++++++++++++++++++++++-
> > > >  target/riscv/helper.h                          |   2 +
> > > >  target/riscv/insn32.decode                     |   2 +-
> > > >  target/riscv/insn_trans/trans_privileged.c.inc |  18 +-
> > > >  target/riscv/insn_trans/trans_rvi.c.inc        |  75 +++++++
> > > >  target/riscv/insn_trans/trans_rvzce.c.inc      |  21 ++
> > > >  target/riscv/machine.c                         |  25 +++
> > > >  target/riscv/op_helper.c                       |  48 ++++
> > > >  target/riscv/tcg/tcg-cpu.c                     |  11 +
> > > >  target/riscv/translate.c                       |  46 ++++
> > > >  15 files changed, 986 insertions(+), 8 deletions(-)
> > > > ---
> > > > base-commit: 699291ba7774f1580584cd96f84ceda8cc4edb7e
> > > > change-id: 20250205-b4-ctr_upstream_v6-71418cd245ee
> > > > --
> > > > Best Regards,
> > > > Rajnesh Kanwal
> > > >
> > > >


^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2025-02-12 16:47 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-05 11:18 [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
2025-02-05 11:18 ` [PATCH v6 1/7] target/riscv: Remove obsolete sfence.vm instruction Rajnesh Kanwal
2025-02-05 11:18 ` [PATCH v6 2/7] target/riscv: Add Control Transfer Records CSR definitions Rajnesh Kanwal
2025-02-05 11:18 ` [PATCH v6 3/7] target/riscv: Add support for Control Transfer Records extension CSRs Rajnesh Kanwal
2025-02-05 11:18 ` [PATCH v6 4/7] target/riscv: Add support to record CTR entries Rajnesh Kanwal
2025-02-05 11:18 ` [PATCH v6 5/7] target/riscv: Add CTR sctrclr instruction Rajnesh Kanwal
2025-02-05 11:18 ` [PATCH v6 6/7] target/riscv: machine: Add Control Transfer Record state description Rajnesh Kanwal
2025-02-05 11:18 ` [PATCH v6 7/7] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs Rajnesh Kanwal
2025-02-06  5:38 ` [PATCH v6 0/7] target/riscv: Add support for Control Transfer Records Ext Alistair Francis
2025-02-06 11:45   ` Rajnesh Kanwal
2025-02-10  4:11     ` Alistair Francis
2025-02-12 16:46       ` Rajnesh Kanwal

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).