[PATCH v2 0/2] target/sparc: Fix register selection for all F*TOx and FxTO* instructions

[PATCH v2 0/2] target/sparc: Fix register selection for all F*TOx and FxTO* instructions

[Mikael Szreder]

This patchset resolves issues with incorrect register selection for the
F*TOx(destination registers) and FxTO*(source registers) instructions
in the Sparc architecture.

An updated testing program can be found in issue #2802[1].

[1]: https://gitlab.com/qemu-project/qemu/-/issues/2802

Changelog:
v2:
- Corrected a mistake I made in the FqTOx instruction
- Fixed issues in the FsTOx, FxTOs, FxTOd, FxTOq instructions as well

Mikael Szreder (2):
  target/sparc: Fix register selection for the fdtox and fqtox
    instructions
  target/sparc: Fix register selection for all F*TOx and FxTO*
    instructions

 target/sparc/insns.decode | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

-- 
2.48.1

[PATCH v2 1/2] target/sparc: Fix register selection for the fdtox and fqtox instructions

[Mikael Szreder]

A bug was introduced in commit 0bba7572d40d which causes the fdtox and
 fqtox instructions to incorrectly select the destination registers.
More information and a test program can be found in issue #2802.

Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802
Signed-off-by: Mikael Szreder <git@miszr.win>
---
 target/sparc/insns.decode | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 989c20b44a..694a28d88c 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -322,8 +322,8 @@ FNHADDs     10 ..... 110100 ..... 0 0111 0001 .....        @r_r_r
 FNHADDd     10 ..... 110100 ..... 0 0111 0010 .....        @d_d_d
 FNsMULd     10 ..... 110100 ..... 0 0111 1001 .....        @d_r_r
 FsTOx       10 ..... 110100 00000 0 1000 0001 .....        @r_r2
-FdTOx       10 ..... 110100 00000 0 1000 0010 .....        @r_d2
-FqTOx       10 ..... 110100 00000 0 1000 0011 .....        @r_q2
+FdTOx       10 ..... 110100 00000 0 1000 0010 .....        @d_d2
+FqTOx       10 ..... 110100 00000 0 1000 0011 .....        @q_q2
 FxTOs       10 ..... 110100 00000 0 1000 0100 .....        @r_r2
 FxTOd       10 ..... 110100 00000 0 1000 1000 .....        @d_r2
 FxTOq       10 ..... 110100 00000 0 1000 1100 .....        @q_r2
-- 
2.48.1

[PATCH v2 2/2] target/sparc: Fix register selection for all F*TOx and FxTO* instructions

[Mikael Szreder]

Fixed a mistake I made in the FqTOx instruction.
Fixed issues in the FsTOx, FxTOs, FxTOd, FxTOq instructions.

Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802
Signed-off-by: Mikael Szreder <git@miszr.win>
---
 target/sparc/insns.decode | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 694a28d88c..cfcdf6690e 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -321,12 +321,12 @@ FdMULq      10 ..... 110100 ..... 0 0110 1110 .....        @q_d_d
 FNHADDs     10 ..... 110100 ..... 0 0111 0001 .....        @r_r_r
 FNHADDd     10 ..... 110100 ..... 0 0111 0010 .....        @d_d_d
 FNsMULd     10 ..... 110100 ..... 0 0111 1001 .....        @d_r_r
-FsTOx       10 ..... 110100 00000 0 1000 0001 .....        @r_r2
+FsTOx       10 ..... 110100 00000 0 1000 0001 .....        @d_r2
 FdTOx       10 ..... 110100 00000 0 1000 0010 .....        @d_d2
-FqTOx       10 ..... 110100 00000 0 1000 0011 .....        @q_q2
-FxTOs       10 ..... 110100 00000 0 1000 0100 .....        @r_r2
-FxTOd       10 ..... 110100 00000 0 1000 1000 .....        @d_r2
-FxTOq       10 ..... 110100 00000 0 1000 1100 .....        @q_r2
+FqTOx       10 ..... 110100 00000 0 1000 0011 .....        @d_q2
+FxTOs       10 ..... 110100 00000 0 1000 0100 .....        @r_d2
+FxTOd       10 ..... 110100 00000 0 1000 1000 .....        @d_d2
+FxTOq       10 ..... 110100 00000 0 1000 1100 .....        @q_d2
 FiTOs       10 ..... 110100 00000 0 1100 0100 .....        @r_r2
 FdTOs       10 ..... 110100 00000 0 1100 0110 .....        @r_d2
 FqTOs       10 ..... 110100 00000 0 1100 0111 .....        @r_q2
-- 
2.48.1

Re: [PATCH v2 2/2] target/sparc: Fix register selection for all F*TOx and FxTO* instructions

[Artyom Tarasenko]

On Wed, Feb 5, 2025 at 10:03 AM Mikael Szreder <git@miszr.win> wrote:
>
> Fixed a mistake I made in the FqTOx instruction.
> Fixed issues in the FsTOx, FxTOs, FxTOd, FxTOq instructions.
>
> Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802
> Signed-off-by: Mikael Szreder <git@miszr.win>

Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>

> ---
>  target/sparc/insns.decode | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
> index 694a28d88c..cfcdf6690e 100644
> --- a/target/sparc/insns.decode
> +++ b/target/sparc/insns.decode
> @@ -321,12 +321,12 @@ FdMULq      10 ..... 110100 ..... 0 0110 1110 .....        @q_d_d
>  FNHADDs     10 ..... 110100 ..... 0 0111 0001 .....        @r_r_r
>  FNHADDd     10 ..... 110100 ..... 0 0111 0010 .....        @d_d_d
>  FNsMULd     10 ..... 110100 ..... 0 0111 1001 .....        @d_r_r
> -FsTOx       10 ..... 110100 00000 0 1000 0001 .....        @r_r2
> +FsTOx       10 ..... 110100 00000 0 1000 0001 .....        @d_r2
>  FdTOx       10 ..... 110100 00000 0 1000 0010 .....        @d_d2
> -FqTOx       10 ..... 110100 00000 0 1000 0011 .....        @q_q2
> -FxTOs       10 ..... 110100 00000 0 1000 0100 .....        @r_r2
> -FxTOd       10 ..... 110100 00000 0 1000 1000 .....        @d_r2
> -FxTOq       10 ..... 110100 00000 0 1000 1100 .....        @q_r2
> +FqTOx       10 ..... 110100 00000 0 1000 0011 .....        @d_q2
> +FxTOs       10 ..... 110100 00000 0 1000 0100 .....        @r_d2
> +FxTOd       10 ..... 110100 00000 0 1000 1000 .....        @d_d2
> +FxTOq       10 ..... 110100 00000 0 1000 1100 .....        @q_d2
>  FiTOs       10 ..... 110100 00000 0 1100 0100 .....        @r_r2
>  FdTOs       10 ..... 110100 00000 0 1100 0110 .....        @r_d2
>  FqTOs       10 ..... 110100 00000 0 1100 0111 .....        @r_q2
> --
> 2.48.1
>

Re: [PATCH v2 0/2] target/sparc: Fix register selection for all F*TOx and FxTO* instructions

[Richard Henderson]

On 2/5/25 01:03, Mikael Szreder wrote:
> Changelog:
> v2:
> - Corrected a mistake I made in the FqTOx instruction
> - Fixed issues in the FsTOx, FxTOs, FxTOd, FxTOq instructions as well

Queued, squashing the two patches together.


r~