* [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()
@ 2025-02-06 17:32 Philippe Mathieu-Daudé
2025-02-06 17:47 ` Richard Henderson
2025-02-07 8:49 ` Bastian Koppelmann
0 siblings, 2 replies; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-02-06 17:32 UTC (permalink / raw)
To: qemu-devel; +Cc: Bastian Koppelmann, Philippe Mathieu-Daudé
We only support 32-bit TriCore architecture.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 6819b776686..c5b783b6a70 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5936,7 +5936,7 @@ static void decode_rr_logical_shift(DisasContext *ctx)
break;
case OPC2_32_RR_CLO:
tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
- tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
+ tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32);
break;
case OPC2_32_RR_CLO_H:
gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
@@ -5948,7 +5948,7 @@ static void decode_rr_logical_shift(DisasContext *ctx)
gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
break;
case OPC2_32_RR_CLZ:
- tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
+ tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32);
break;
case OPC2_32_RR_CLZ_H:
gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
--
2.47.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()
2025-02-06 17:32 [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift() Philippe Mathieu-Daudé
@ 2025-02-06 17:47 ` Richard Henderson
2025-02-06 18:20 ` Philippe Mathieu-Daudé
2025-02-07 8:49 ` Bastian Koppelmann
1 sibling, 1 reply; 4+ messages in thread
From: Richard Henderson @ 2025-02-06 17:47 UTC (permalink / raw)
To: qemu-devel
On 2/6/25 09:32, Philippe Mathieu-Daudé wrote:
> We only support 32-bit TriCore architecture.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/tricore/translate.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index 6819b776686..c5b783b6a70 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -5936,7 +5936,7 @@ static void decode_rr_logical_shift(DisasContext *ctx)
> break;
> case OPC2_32_RR_CLO:
> tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
> - tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
> + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32);
> break;
> case OPC2_32_RR_CLO_H:
> gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
> @@ -5948,7 +5948,7 @@ static void decode_rr_logical_shift(DisasContext *ctx)
> gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
> break;
> case OPC2_32_RR_CLZ:
> - tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
> + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32);
> break;
> case OPC2_32_RR_CLZ_H:
> gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
Leave it alone unless you swap /_tl/_i32/ ?
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()
2025-02-06 17:47 ` Richard Henderson
@ 2025-02-06 18:20 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-02-06 18:20 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 6/2/25 18:47, Richard Henderson wrote:
> On 2/6/25 09:32, Philippe Mathieu-Daudé wrote:
>> We only support 32-bit TriCore architecture.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> target/tricore/translate.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
>> index 6819b776686..c5b783b6a70 100644
>> --- a/target/tricore/translate.c
>> +++ b/target/tricore/translate.c
>> @@ -5936,7 +5936,7 @@ static void decode_rr_logical_shift(DisasContext
>> *ctx)
>> break;
>> case OPC2_32_RR_CLO:
>> tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
>> - tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS);
>> + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32);
>> break;
>> case OPC2_32_RR_CLO_H:
>> gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
>> @@ -5948,7 +5948,7 @@ static void decode_rr_logical_shift(DisasContext
>> *ctx)
>> gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
>> break;
>> case OPC2_32_RR_CLZ:
>> - tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS);
>> + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32);
>> break;
>> case OPC2_32_RR_CLZ_H:
>> gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
>
> Leave it alone unless you swap /_tl/_i32/ ?
I was expecting something like that, fair enough :)
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift()
2025-02-06 17:32 [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift() Philippe Mathieu-Daudé
2025-02-06 17:47 ` Richard Henderson
@ 2025-02-07 8:49 ` Bastian Koppelmann
1 sibling, 0 replies; 4+ messages in thread
From: Bastian Koppelmann @ 2025-02-07 8:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel
On Thu, Feb 06, 2025 at 06:32:58PM +0100, Philippe Mathieu-Daudé wrote:
> We only support 32-bit TriCore architecture.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/tricore/translate.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cheers,
Bastian
^ permalink raw reply [flat|nested] 4+ messages in thread
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2025-02-06 17:32 [PATCH] target/tricore: Inline TARGET_LONG_BITS in decode_rr_logical_shift() Philippe Mathieu-Daudé
2025-02-06 17:47 ` Richard Henderson
2025-02-06 18:20 ` Philippe Mathieu-Daudé
2025-02-07 8:49 ` Bastian Koppelmann
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