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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
	qemu-riscv@nongnu.org,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Bin Meng" <bmeng.cn@gmail.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"Sunil V L" <sunilvl@ventanamicro.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 6/7] hw/riscv/hart: Make 'riscv_hart.h' header target-agnostic
Date: Thu,  6 Feb 2025 19:18:26 +0100	[thread overview]
Message-ID: <20250206181827.41557-7-philmd@linaro.org> (raw)
In-Reply-To: <20250206181827.41557-1-philmd@linaro.org>

Hardware code using HART rarely needs to knows its internals.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/riscv/riscv_hart.h | 4 ++--
 hw/riscv/virt-acpi-build.c    | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index a6ed73a1956..a2ca455d8b1 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -22,7 +22,7 @@
 #define HW_RISCV_HART_H
 
 #include "hw/sysbus.h"
-#include "target/riscv/cpu.h"
+#include "target/riscv/cpu-qom.h"
 #include "qom/object.h"
 
 #define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
@@ -42,7 +42,7 @@ struct RISCVHartArrayState {
     uint64_t *rnmi_irqvec;
     uint32_t num_rnmi_excpvec;
     uint64_t *rnmi_excpvec;
-    RISCVCPU *harts;
+    ArchCPU *harts;
 };
 
 #endif
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 1ad68005085..0030c21bc41 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -39,6 +39,7 @@
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "system/reset.h"
+#include "target/riscv/cpu.h"
 
 #define ACPI_BUILD_TABLE_SIZE             0x20000
 #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
-- 
2.47.1



  parent reply	other threads:[~2025-02-06 18:21 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-06 18:18 [PATCH 0/7] hw/riscv: Move few units to common_ss[] Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 1/7] MAINTAINERS: Unify Alistair's professional email address Philippe Mathieu-Daudé
2025-02-06 18:19   ` Philippe Mathieu-Daudé
2025-02-06 20:54   ` Richard Henderson
2025-02-10  0:24   ` Alistair Francis
2025-02-06 18:18 ` [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h' Philippe Mathieu-Daudé
2025-02-08 16:51   ` Philippe Mathieu-Daudé
2025-02-09  7:34   ` Paolo Bonzini
2025-03-06  7:47     ` Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 3/7] hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header Philippe Mathieu-Daudé
2025-02-06 20:54   ` Richard Henderson
2025-02-10  0:21   ` Alistair Francis
2025-02-06 18:18 ` [PATCH 4/7] hw/riscv/boot: Use 'hwaddr' type for firmware addresses Philippe Mathieu-Daudé
2025-02-06 18:18 ` [PATCH 5/7] hw/riscv/iommu: Reduce needs for target-specific code Philippe Mathieu-Daudé
2025-02-06 18:18 ` Philippe Mathieu-Daudé [this message]
2025-02-06 18:18 ` [PATCH 7/7] hw/riscv: Move few objects to common_ss[] to build them once Philippe Mathieu-Daudé

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