[PATCH 0/7] hw/riscv: Move few units to common_ss[]

[PATCH 0/7] hw/riscv: Move few units to common_ss[]

[Philippe Mathieu-Daudé]

Remove target-specificity in some units and move them to
the meson common_ss[] source set to build them once.

Philippe Mathieu-Daudé (7):
  MAINTAINERS: Unify Alistair's professional email address
  target/riscv: Move target-agnostic definitions to 'cpu-qom.h'
  hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header
  hw/riscv/boot: Use 'hwaddr' type for firmware addresses
  hw/riscv/iommu: Reduce needs for target-specific code
  hw/riscv/hart: Make 'riscv_hart.h' header target-agnostic
  hw/riscv: Move few objects to common_ss[] to build them once

 MAINTAINERS                     | 12 +++++-----
 include/hw/riscv/boot.h         | 21 +++++++++--------
 include/hw/riscv/boot_opensbi.h | 14 ++++++------
 include/hw/riscv/riscv_hart.h   |  4 ++--
 target/riscv/cpu-qom.h          | 40 +++++++++++++++++++++++++++++++++
 target/riscv/cpu.h              | 24 --------------------
 target/riscv/cpu_bits.h         | 15 -------------
 hw/riscv/boot.c                 | 28 +++++++++++------------
 hw/riscv/opentitan.c            |  1 +
 hw/riscv/riscv-iommu-pci.c      |  5 +++--
 hw/riscv/riscv-iommu-sys.c      |  1 -
 hw/riscv/riscv-iommu.c          |  1 +
 hw/riscv/virt-acpi-build.c      |  1 +
 hw/riscv/meson.build            |  5 +++--
 14 files changed, 88 insertions(+), 84 deletions(-)

-- 
2.47.1

[PATCH 1/7] MAINTAINERS: Unify Alistair's professional email address

[Philippe Mathieu-Daudé]

Alistair's email is typed differently, so the get_maintainer.pl
script add it twice :) Unify to reduce traffic.

  $ git grep -h 'Alistair Francis' -- MAINTAINERS | sort -u
  M: Alistair Francis <Alistair.Francis@wdc.com>
  M: Alistair Francis <alistair.francis@wdc.com>
  M: Alistair Francis <alistair@alistair23.me>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 MAINTAINERS | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0cf37fce7b5..b7ac1519ee3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -318,7 +318,7 @@ F: tests/functional/test_ppc_74xx.py
 
 RISC-V TCG CPUs
 M: Palmer Dabbelt <palmer@dabbelt.com>
-M: Alistair Francis <alistair.francis@wdc.com>
+M: alistair.francis <alistair.francis@wdc.com>
 M: Bin Meng <bmeng.cn@gmail.com>
 R: Weiwei Li <liwei1518@gmail.com>
 R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
@@ -753,7 +753,7 @@ F: docs/system/arm/digic.rst
 
 Goldfish RTC
 M: Anup Patel <anup.patel@wdc.com>
-M: Alistair Francis <Alistair.Francis@wdc.com>
+M: alistair.francis <alistair.francis@wdc.com>
 L: qemu-riscv@nongnu.org
 S: Maintained
 F: hw/rtc/goldfish_rtc.c
@@ -1009,7 +1009,7 @@ F: tests/functional/test_arm_tuxrun.py
 
 Xilinx Zynq
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-M: Alistair Francis <alistair@alistair23.me>
+M: alistair.francis <alistair@alistair23.me>
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
@@ -1593,7 +1593,7 @@ F: pc-bios/vof*
 RISC-V Machines
 ---------------
 OpenTitan
-M: Alistair Francis <Alistair.Francis@wdc.com>
+M: Alistair Francis <alistair.francis@wdc.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: hw/riscv/opentitan.c
@@ -1628,7 +1628,7 @@ F: include/hw/riscv/shakti_c.h
 F: include/hw/char/shakti_uart.h
 
 SiFive Machines
-M: Alistair Francis <Alistair.Francis@wdc.com>
+M: Alistair Francis <alistair.francis@wdc.com>
 M: Bin Meng <bmeng.cn@gmail.com>
 M: Palmer Dabbelt <palmer@dabbelt.com>
 L: qemu-riscv@nongnu.org
@@ -3842,7 +3842,7 @@ F: tcg/ppc/
 
 RISC-V TCG target
 M: Palmer Dabbelt <palmer@dabbelt.com>
-M: Alistair Francis <Alistair.Francis@wdc.com>
+M: Alistair Francis <alistair.francis@wdc.com>
 L: qemu-riscv@nongnu.org
 S: Maintained
 F: tcg/riscv/
-- 
2.47.1

Re: [PATCH 1/7] MAINTAINERS: Unify Alistair's professional email address

[Philippe Mathieu-Daudé]

On 6/2/25 19:18, Philippe Mathieu-Daudé wrote:
> Alistair's email is typed differently, so the get_maintainer.pl
> script add it twice :) Unify to reduce traffic.
> 
>    $ git grep -h 'Alistair Francis' -- MAINTAINERS | sort -u
>    M: Alistair Francis <Alistair.Francis@wdc.com>
>    M: Alistair Francis <alistair.francis@wdc.com>
>    M: Alistair Francis <alistair@alistair23.me>
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   MAINTAINERS | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 0cf37fce7b5..b7ac1519ee3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -318,7 +318,7 @@ F: tests/functional/test_ppc_74xx.py
>   
>   RISC-V TCG CPUs
>   M: Palmer Dabbelt <palmer@dabbelt.com>
> -M: Alistair Francis <alistair.francis@wdc.com>
> +M: alistair.francis <alistair.francis@wdc.com>

Grr this isn't the version I wanted to post, sorry for the noise...

Re: [PATCH 1/7] MAINTAINERS: Unify Alistair's professional email address

[Richard Henderson]

On 2/6/25 10:18, Philippe Mathieu-Daudé wrote:
> -M: Alistair Francis<alistair.francis@wdc.com>
> +M: alistair.francis<alistair.francis@wdc.com>

Well this isn't right.


r~

Re: [PATCH 1/7] MAINTAINERS: Unify Alistair's professional email address

[Alistair Francis]

On Fri, Feb 7, 2025 at 4:22 AM Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> Alistair's email is typed differently, so the get_maintainer.pl
> script add it twice :) Unify to reduce traffic.
>
>   $ git grep -h 'Alistair Francis' -- MAINTAINERS | sort -u
>   M: Alistair Francis <Alistair.Francis@wdc.com>
>   M: Alistair Francis <alistair.francis@wdc.com>

These two should be combined

>   M: Alistair Francis <alistair@alistair23.me>

But this is actually my personal email for older non WDC work
(basically not RISC-V stuff).

It all goes to the same place but there is some distinction between
the two, so I'd probably like to keep this one separate. If it's too
annoying for others then I'm happy to consolidate them though

Alistair

>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  MAINTAINERS | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 0cf37fce7b5..b7ac1519ee3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -318,7 +318,7 @@ F: tests/functional/test_ppc_74xx.py
>
>  RISC-V TCG CPUs
>  M: Palmer Dabbelt <palmer@dabbelt.com>
> -M: Alistair Francis <alistair.francis@wdc.com>
> +M: alistair.francis <alistair.francis@wdc.com>
>  M: Bin Meng <bmeng.cn@gmail.com>
>  R: Weiwei Li <liwei1518@gmail.com>
>  R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> @@ -753,7 +753,7 @@ F: docs/system/arm/digic.rst
>
>  Goldfish RTC
>  M: Anup Patel <anup.patel@wdc.com>
> -M: Alistair Francis <Alistair.Francis@wdc.com>
> +M: alistair.francis <alistair.francis@wdc.com>
>  L: qemu-riscv@nongnu.org
>  S: Maintained
>  F: hw/rtc/goldfish_rtc.c
> @@ -1009,7 +1009,7 @@ F: tests/functional/test_arm_tuxrun.py
>
>  Xilinx Zynq
>  M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> -M: Alistair Francis <alistair@alistair23.me>
> +M: alistair.francis <alistair@alistair23.me>
>  M: Peter Maydell <peter.maydell@linaro.org>
>  L: qemu-arm@nongnu.org
>  S: Maintained
> @@ -1593,7 +1593,7 @@ F: pc-bios/vof*
>  RISC-V Machines
>  ---------------
>  OpenTitan
> -M: Alistair Francis <Alistair.Francis@wdc.com>
> +M: Alistair Francis <alistair.francis@wdc.com>
>  L: qemu-riscv@nongnu.org
>  S: Supported
>  F: hw/riscv/opentitan.c
> @@ -1628,7 +1628,7 @@ F: include/hw/riscv/shakti_c.h
>  F: include/hw/char/shakti_uart.h
>
>  SiFive Machines
> -M: Alistair Francis <Alistair.Francis@wdc.com>
> +M: Alistair Francis <alistair.francis@wdc.com>
>  M: Bin Meng <bmeng.cn@gmail.com>
>  M: Palmer Dabbelt <palmer@dabbelt.com>
>  L: qemu-riscv@nongnu.org
> @@ -3842,7 +3842,7 @@ F: tcg/ppc/
>
>  RISC-V TCG target
>  M: Palmer Dabbelt <palmer@dabbelt.com>
> -M: Alistair Francis <Alistair.Francis@wdc.com>
> +M: Alistair Francis <alistair.francis@wdc.com>
>  L: qemu-riscv@nongnu.org
>  S: Maintained
>  F: tcg/riscv/
> --
> 2.47.1
>
>

[PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h'

[Philippe Mathieu-Daudé]

"cpu.h" is target-specific. Definitions which can be used
by hw/ code when building QOM blocks can be in "cpu-qom.h",
which is target-agnostic.

Move the MISA bits (removing the pointless target_ulong cast)
and the IRQ index definitions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/cpu-qom.h  | 40 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/cpu.h      | 24 ------------------------
 target/riscv/cpu_bits.h | 15 ---------------
 3 files changed, 40 insertions(+), 39 deletions(-)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index d56b067bf24..6028aa38fb2 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -55,4 +55,44 @@
 
 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
 
+/* Interrupt causes */
+#define IRQ_U_SOFT                         0
+#define IRQ_S_SOFT                         1
+#define IRQ_VS_SOFT                        2
+#define IRQ_M_SOFT                         3
+#define IRQ_U_TIMER                        4
+#define IRQ_S_TIMER                        5
+#define IRQ_VS_TIMER                       6
+#define IRQ_M_TIMER                        7
+#define IRQ_U_EXT                          8
+#define IRQ_S_EXT                          9
+#define IRQ_VS_EXT                         10
+#define IRQ_M_EXT                          11
+#define IRQ_S_GEXT                         12
+#define IRQ_PMU_OVF                        13
+
+#define RV(x) (1UL << (x - 'A'))
+
+/*
+ * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
+ * when adding new MISA bits here.
+ */
+#define RVI RV('I')
+#define RVE RV('E') /* E and I are mutually exclusive */
+#define RVM RV('M')
+#define RVA RV('A')
+#define RVF RV('F')
+#define RVD RV('D')
+#define RVV RV('V')
+#define RVC RV('C')
+#define RVS RV('S')
+#define RVU RV('U')
+#define RVH RV('H')
+#define RVG RV('G')
+#define RVB RV('B')
+
+extern const uint32_t misa_bits[];
+const char *riscv_get_misa_ext_name(uint32_t bit);
+const char *riscv_get_misa_ext_description(uint32_t bit);
+
 #endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 97713681cbe..4e681ad3917 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -54,30 +54,6 @@ typedef struct CPUArchState CPURISCVState;
  */
 #define RISCV_UW2_ALWAYS_STORE_AMO 1
 
-#define RV(x) ((target_ulong)1 << (x - 'A'))
-
-/*
- * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
- * when adding new MISA bits here.
- */
-#define RVI RV('I')
-#define RVE RV('E') /* E and I are mutually exclusive */
-#define RVM RV('M')
-#define RVA RV('A')
-#define RVF RV('F')
-#define RVD RV('D')
-#define RVV RV('V')
-#define RVC RV('C')
-#define RVS RV('S')
-#define RVU RV('U')
-#define RVH RV('H')
-#define RVG RV('G')
-#define RVB RV('B')
-
-extern const uint32_t misa_bits[];
-const char *riscv_get_misa_ext_name(uint32_t bit);
-const char *riscv_get_misa_ext_description(uint32_t bit);
-
 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
 
 typedef struct riscv_cpu_profile {
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index f97c48a3943..80701bc77fe 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -720,21 +720,6 @@ typedef enum RISCVException {
 #define RISCV_EXCP_INT_FLAG                0x80000000
 #define RISCV_EXCP_INT_MASK                0x7fffffff
 
-/* Interrupt causes */
-#define IRQ_U_SOFT                         0
-#define IRQ_S_SOFT                         1
-#define IRQ_VS_SOFT                        2
-#define IRQ_M_SOFT                         3
-#define IRQ_U_TIMER                        4
-#define IRQ_S_TIMER                        5
-#define IRQ_VS_TIMER                       6
-#define IRQ_M_TIMER                        7
-#define IRQ_U_EXT                          8
-#define IRQ_S_EXT                          9
-#define IRQ_VS_EXT                         10
-#define IRQ_M_EXT                          11
-#define IRQ_S_GEXT                         12
-#define IRQ_PMU_OVF                        13
 #define IRQ_LOCAL_MAX                      64
 /* -1 is due to bit zero of hgeip and hgeie being ROZ. */
 #define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)
-- 
2.47.1

Re: [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h'

[Philippe Mathieu-Daudé]

On 6/2/25 19:18, Philippe Mathieu-Daudé wrote:
> "cpu.h" is target-specific. Definitions which can be used
> by hw/ code when building QOM blocks can be in "cpu-qom.h",
> which is target-agnostic.

What I'm trying to allow here are QOM uses such:

../../hw/riscv/opentitan.c:199:61: error: use of undeclared identifier 
'IRQ_M_EXT'
   199 |                               qdev_get_gpio_in(DEVICE(cpu), 
IRQ_M_EXT));
       |                                                             ^
../../hw/riscv/opentitan.c:230:44: error: use of undeclared identifier 
'IRQ_M_TIMER'; did you mean 'IBEX_TIMER'?
   230 |                                            IRQ_M_TIMER));
       |                                            ^~~~~~~~~~~

> Move the MISA bits (removing the pointless target_ulong cast)
> and the IRQ index definitions.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/cpu-qom.h  | 40 ++++++++++++++++++++++++++++++++++++++++
>   target/riscv/cpu.h      | 24 ------------------------
>   target/riscv/cpu_bits.h | 15 ---------------
>   3 files changed, 40 insertions(+), 39 deletions(-)

Re: [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h'

[Paolo Bonzini]

On 2/6/25 19:18, Philippe Mathieu-Daudé wrote:
> "cpu.h" is target-specific. Definitions which can be used
> by hw/ code when building QOM blocks can be in "cpu-qom.h",
> which is target-agnostic.
> 
> Move the MISA bits (removing the pointless target_ulong cast)
> and the IRQ index definitions.

This seems wrong.  Why not move from cpu.h to cpu_bits.h, and include that?

Paolo

> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/cpu-qom.h  | 40 ++++++++++++++++++++++++++++++++++++++++
>   target/riscv/cpu.h      | 24 ------------------------
>   target/riscv/cpu_bits.h | 15 ---------------
>   3 files changed, 40 insertions(+), 39 deletions(-)
> 
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index d56b067bf24..6028aa38fb2 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -55,4 +55,44 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
>   
> +/* Interrupt causes */
> +#define IRQ_U_SOFT                         0
> +#define IRQ_S_SOFT                         1
> +#define IRQ_VS_SOFT                        2
> +#define IRQ_M_SOFT                         3
> +#define IRQ_U_TIMER                        4
> +#define IRQ_S_TIMER                        5
> +#define IRQ_VS_TIMER                       6
> +#define IRQ_M_TIMER                        7
> +#define IRQ_U_EXT                          8
> +#define IRQ_S_EXT                          9
> +#define IRQ_VS_EXT                         10
> +#define IRQ_M_EXT                          11
> +#define IRQ_S_GEXT                         12
> +#define IRQ_PMU_OVF                        13
> +
> +#define RV(x) (1UL << (x - 'A'))
> +
> +/*
> + * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
> + * when adding new MISA bits here.
> + */
> +#define RVI RV('I')
> +#define RVE RV('E') /* E and I are mutually exclusive */
> +#define RVM RV('M')
> +#define RVA RV('A')
> +#define RVF RV('F')
> +#define RVD RV('D')
> +#define RVV RV('V')
> +#define RVC RV('C')
> +#define RVS RV('S')
> +#define RVU RV('U')
> +#define RVH RV('H')
> +#define RVG RV('G')
> +#define RVB RV('B')
> +
> +extern const uint32_t misa_bits[];
> +const char *riscv_get_misa_ext_name(uint32_t bit);
> +const char *riscv_get_misa_ext_description(uint32_t bit);
> +
>   #endif /* RISCV_CPU_QOM_H */
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 97713681cbe..4e681ad3917 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -54,30 +54,6 @@ typedef struct CPUArchState CPURISCVState;
>    */
>   #define RISCV_UW2_ALWAYS_STORE_AMO 1
>   
> -#define RV(x) ((target_ulong)1 << (x - 'A'))
> -
> -/*
> - * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
> - * when adding new MISA bits here.
> - */
> -#define RVI RV('I')
> -#define RVE RV('E') /* E and I are mutually exclusive */
> -#define RVM RV('M')
> -#define RVA RV('A')
> -#define RVF RV('F')
> -#define RVD RV('D')
> -#define RVV RV('V')
> -#define RVC RV('C')
> -#define RVS RV('S')
> -#define RVU RV('U')
> -#define RVH RV('H')
> -#define RVG RV('G')
> -#define RVB RV('B')
> -
> -extern const uint32_t misa_bits[];
> -const char *riscv_get_misa_ext_name(uint32_t bit);
> -const char *riscv_get_misa_ext_description(uint32_t bit);
> -
>   #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
>   
>   typedef struct riscv_cpu_profile {
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index f97c48a3943..80701bc77fe 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -720,21 +720,6 @@ typedef enum RISCVException {
>   #define RISCV_EXCP_INT_FLAG                0x80000000
>   #define RISCV_EXCP_INT_MASK                0x7fffffff
>   
> -/* Interrupt causes */
> -#define IRQ_U_SOFT                         0
> -#define IRQ_S_SOFT                         1
> -#define IRQ_VS_SOFT                        2
> -#define IRQ_M_SOFT                         3
> -#define IRQ_U_TIMER                        4
> -#define IRQ_S_TIMER                        5
> -#define IRQ_VS_TIMER                       6
> -#define IRQ_M_TIMER                        7
> -#define IRQ_U_EXT                          8
> -#define IRQ_S_EXT                          9
> -#define IRQ_VS_EXT                         10
> -#define IRQ_M_EXT                          11
> -#define IRQ_S_GEXT                         12
> -#define IRQ_PMU_OVF                        13
>   #define IRQ_LOCAL_MAX                      64
>   /* -1 is due to bit zero of hgeip and hgeie being ROZ. */
>   #define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)

Re: [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h'

[Philippe Mathieu-Daudé]

On 9/2/25 08:34, Paolo Bonzini wrote:
> On 2/6/25 19:18, Philippe Mathieu-Daudé wrote:
>> "cpu.h" is target-specific. Definitions which can be used
>> by hw/ code when building QOM blocks can be in "cpu-qom.h",
>> which is target-agnostic.
>>
>> Move the MISA bits (removing the pointless target_ulong cast)
>> and the IRQ index definitions.
> 
> This seems wrong.  Why not move from cpu.h to cpu_bits.h, and include that?

Because of ...

> 
> Paolo
> 
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   target/riscv/cpu-qom.h  | 40 ++++++++++++++++++++++++++++++++++++++++
>>   target/riscv/cpu.h      | 24 ------------------------
>>   target/riscv/cpu_bits.h | 15 ---------------
>>   3 files changed, 40 insertions(+), 39 deletions(-)


>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>> index f97c48a3943..80701bc77fe 100644
>> --- a/target/riscv/cpu_bits.h
>> +++ b/target/riscv/cpu_bits.h
>> @@ -720,21 +720,6 @@ typedef enum RISCVException {
>>   #define RISCV_EXCP_INT_FLAG                0x80000000
>>   #define RISCV_EXCP_INT_MASK                0x7fffffff
>> -/* Interrupt causes */
>> -#define IRQ_U_SOFT                         0
>> -#define IRQ_S_SOFT                         1
>> -#define IRQ_VS_SOFT                        2
>> -#define IRQ_M_SOFT                         3
>> -#define IRQ_U_TIMER                        4
>> -#define IRQ_S_TIMER                        5
>> -#define IRQ_VS_TIMER                       6
>> -#define IRQ_M_TIMER                        7
>> -#define IRQ_U_EXT                          8
>> -#define IRQ_S_EXT                          9
>> -#define IRQ_VS_EXT                         10
>> -#define IRQ_M_EXT                          11
>> -#define IRQ_S_GEXT                         12
>> -#define IRQ_PMU_OVF                        13
>>   #define IRQ_LOCAL_MAX                      64
>>   /* -1 is due to bit zero of hgeip and hgeie being ROZ. */
>>   #define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)

... this TARGET_LONG_BITS use in cpu_bits.h.

and:

target/riscv/cpu_bits.h:1070:44: error: attempt to use a poisoned identifier
  1070 | #define CPU_INTERRUPT_RNMI                 CPU_INTERRUPT_TGT_EXT_0
       |                                            ^

But I got your idea and will only move these 2 to "cpu.h".

[PATCH 3/7] hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header

[Philippe Mathieu-Daudé]

opentitan_machine_init() calls get_system_memory(),
which is declared in "exec/address-spaces.h". Include
it in order to avoid when refactoring unrelated headers:

  hw/riscv/opentitan.c:83:29: error: call to undeclared function 'get_system_memory'
     83 |     MemoryRegion *sys_mem = get_system_memory();
        |                             ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/riscv/opentitan.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index b9e56235d87..98a67fe52a8 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -28,6 +28,7 @@
 #include "hw/riscv/boot.h"
 #include "qemu/units.h"
 #include "system/system.h"
+#include "exec/address-spaces.h"
 
 /*
  * This version of the OpenTitan machine currently supports
-- 
2.47.1

Re: [PATCH 3/7] hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header

[Richard Henderson]

On 2/6/25 10:18, Philippe Mathieu-Daudé wrote:
> opentitan_machine_init() calls get_system_memory(),
> which is declared in "exec/address-spaces.h". Include
> it in order to avoid when refactoring unrelated headers:
> 
>    hw/riscv/opentitan.c:83:29: error: call to undeclared function 'get_system_memory'
>       83 |     MemoryRegion *sys_mem = get_system_memory();
>          |                             ^
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/riscv/opentitan.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index b9e56235d87..98a67fe52a8 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -28,6 +28,7 @@
>   #include "hw/riscv/boot.h"
>   #include "qemu/units.h"
>   #include "system/system.h"
> +#include "exec/address-spaces.h"
>   
>   /*
>    * This version of the OpenTitan machine currently supports

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 3/7] hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header

[Alistair Francis]

On Fri, Feb 7, 2025 at 4:20 AM Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> opentitan_machine_init() calls get_system_memory(),
> which is declared in "exec/address-spaces.h". Include
> it in order to avoid when refactoring unrelated headers:
>
>   hw/riscv/opentitan.c:83:29: error: call to undeclared function 'get_system_memory'
>      83 |     MemoryRegion *sys_mem = get_system_memory();
>         |                             ^
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/opentitan.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index b9e56235d87..98a67fe52a8 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -28,6 +28,7 @@
>  #include "hw/riscv/boot.h"
>  #include "qemu/units.h"
>  #include "system/system.h"
> +#include "exec/address-spaces.h"
>
>  /*
>   * This version of the OpenTitan machine currently supports
> --
> 2.47.1
>
>

[PATCH 4/7] hw/riscv/boot: Use 'hwaddr' type for firmware addresses

[Philippe Mathieu-Daudé]

Some places already use the hwaddr type. Use it all over
the API allows it to be target agnostic. Use cpu_env() in
riscv_plic_hart_config_string() to shorten the access.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/riscv/boot.h         | 21 ++++++++++-----------
 include/hw/riscv/boot_opensbi.h | 14 +++++++-------
 hw/riscv/boot.c                 | 28 ++++++++++++++--------------
 3 files changed, 31 insertions(+), 32 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 7d59b2e6c63..1f66432eaed 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -20,7 +20,6 @@
 #ifndef RISCV_BOOT_H
 #define RISCV_BOOT_H
 
-#include "exec/cpu-defs.h"
 #include "hw/loader.h"
 #include "hw/riscv/riscv_hart.h"
 
@@ -43,21 +42,21 @@ bool riscv_is_32bit(RISCVHartArrayState *harts);
 char *riscv_plic_hart_config_string(int hart_count);
 
 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);
-target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
-                                          target_ulong firmware_end_addr);
-target_ulong riscv_find_and_load_firmware(MachineState *machine,
-                                          const char *default_machine_firmware,
-                                          hwaddr *firmware_load_addr,
-                                          symbol_fn_t sym_cb);
+hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,
+                                    hwaddr firmware_end_addr);
+hwaddr riscv_find_and_load_firmware(MachineState *machine,
+                                    const char *default_machine_firmware,
+                                    hwaddr *firmware_load_addr,
+                                    symbol_fn_t sym_cb);
 const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
 char *riscv_find_firmware(const char *firmware_filename,
                           const char *default_machine_firmware);
-target_ulong riscv_load_firmware(const char *firmware_filename,
-                                 hwaddr *firmware_load_addr,
-                                 symbol_fn_t sym_cb);
+hwaddr riscv_load_firmware(const char *firmware_filename,
+                           hwaddr *firmware_load_addr,
+                           symbol_fn_t sym_cb);
 void riscv_load_kernel(MachineState *machine,
                        RISCVBootInfo *info,
-                       target_ulong kernel_start_addr,
+                       hwaddr kernel_start_addr,
                        bool load_initrd,
                        symbol_fn_t sym_cb);
 uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h
index 18664a174b5..e6998c668ad 100644
--- a/include/hw/riscv/boot_opensbi.h
+++ b/include/hw/riscv/boot_opensbi.h
@@ -8,7 +8,7 @@
 #ifndef RISCV_BOOT_OPENSBI_H
 #define RISCV_BOOT_OPENSBI_H
 
-#include "exec/cpu-defs.h"
+#include "exec/hwaddr.h"
 
 /** Expected value of info magic ('OSBI' ascii string in hex) */
 #define FW_DYNAMIC_INFO_MAGIC_VALUE     0x4942534f
@@ -31,15 +31,15 @@ enum sbi_scratch_options {
 /** Representation dynamic info passed by previous booting stage */
 struct fw_dynamic_info {
     /** Info magic */
-    target_long magic;
+    hwaddr magic;
     /** Info version */
-    target_long version;
+    hwaddr version;
     /** Next booting stage address */
-    target_long next_addr;
+    hwaddr next_addr;
     /** Next booting stage mode */
-    target_long next_mode;
+    hwaddr next_mode;
     /** Options for OpenSBI library */
-    target_long options;
+    hwaddr options;
     /**
      * Preferred boot HART id
      *
@@ -55,7 +55,7 @@ struct fw_dynamic_info {
      * stage can set it to -1UL which will force the FW_DYNAMIC firmware
      * to use the relocation lottery mechanism.
      */
-    target_long boot_hart;
+    hwaddr boot_hart;
 };
 
 /** Representation dynamic info passed by previous booting stage */
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index c309441b7d8..acc0d221fce 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -21,7 +21,6 @@
 #include "qemu/datadir.h"
 #include "qemu/units.h"
 #include "qemu/error-report.h"
-#include "exec/cpu-defs.h"
 #include "hw/boards.h"
 #include "hw/loader.h"
 #include "hw/riscv/boot.h"
@@ -31,6 +30,7 @@
 #include "system/qtest.h"
 #include "system/kvm.h"
 #include "system/reset.h"
+#include "target/riscv/cpu.h"
 
 #include <libfdt.h>
 
@@ -51,7 +51,7 @@ char *riscv_plic_hart_config_string(int hart_count)
 
     for (i = 0; i < hart_count; i++) {
         CPUState *cs = qemu_get_cpu(i);
-        CPURISCVState *env = &RISCV_CPU(cs)->env;
+        CPURISCVState *env = cpu_env(cs);
 
         if (kvm_enabled()) {
             vals[i] = "S";
@@ -74,8 +74,8 @@ void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
     info->is_32bit = riscv_is_32bit(harts);
 }
 
-target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
-                                          target_ulong firmware_end_addr) {
+hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,
+                                    hwaddr firmware_end_addr) {
     if (info->is_32bit) {
         return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
     } else {
@@ -133,13 +133,13 @@ char *riscv_find_firmware(const char *firmware_filename,
     return filename;
 }
 
-target_ulong riscv_find_and_load_firmware(MachineState *machine,
-                                          const char *default_machine_firmware,
-                                          hwaddr *firmware_load_addr,
-                                          symbol_fn_t sym_cb)
+hwaddr riscv_find_and_load_firmware(MachineState *machine,
+                                    const char *default_machine_firmware,
+                                    hwaddr *firmware_load_addr,
+                                    symbol_fn_t sym_cb)
 {
     char *firmware_filename;
-    target_ulong firmware_end_addr = *firmware_load_addr;
+    hwaddr firmware_end_addr = *firmware_load_addr;
 
     firmware_filename = riscv_find_firmware(machine->firmware,
                                             default_machine_firmware);
@@ -154,11 +154,11 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
     return firmware_end_addr;
 }
 
-target_ulong riscv_load_firmware(const char *firmware_filename,
-                                 hwaddr *firmware_load_addr,
-                                 symbol_fn_t sym_cb)
+hwaddr riscv_load_firmware(const char *firmware_filename,
+                           hwaddr *firmware_load_addr,
+                           symbol_fn_t sym_cb)
 {
-    uint64_t firmware_entry, firmware_end;
+    hwaddr firmware_entry, firmware_end;
     ssize_t firmware_size;
 
     g_assert(firmware_filename != NULL);
@@ -227,7 +227,7 @@ static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)
 
 void riscv_load_kernel(MachineState *machine,
                        RISCVBootInfo *info,
-                       target_ulong kernel_start_addr,
+                       hwaddr kernel_start_addr,
                        bool load_initrd,
                        symbol_fn_t sym_cb)
 {
-- 
2.47.1

[PATCH 5/7] hw/riscv/iommu: Reduce needs for target-specific code

[Philippe Mathieu-Daudé]

Use the qemu_target_page_size() runtime function instead
of the TARGET_PAGE_SIZE definition, remove unnecessary
"exec/exec-all.h" header.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/riscv/riscv-iommu-pci.c | 5 +++--
 hw/riscv/riscv-iommu-sys.c | 1 -
 hw/riscv/riscv-iommu.c     | 1 +
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c
index 12451869e41..d8779481421 100644
--- a/hw/riscv/riscv-iommu-pci.c
+++ b/hw/riscv/riscv-iommu-pci.c
@@ -22,13 +22,13 @@
 #include "hw/pci/pci_bus.h"
 #include "hw/qdev-properties.h"
 #include "hw/riscv/riscv_hart.h"
+#include "exec/target_page.h"
 #include "migration/vmstate.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "qemu/host-utils.h"
 #include "qom/object.h"
 
-#include "cpu_bits.h"
 #include "riscv-iommu.h"
 #include "riscv-iommu-bits.h"
 #include "trace.h"
@@ -102,7 +102,8 @@ static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp)
     qdev_realize(DEVICE(iommu), NULL, errp);
 
     memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0",
-        QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE));
+        QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr),
+                      qemu_target_page_size()));
     memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr);
 
     pcie_endpoint_cap_init(dev, 0);
diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
index 65b24fb07de..bbe839ed241 100644
--- a/hw/riscv/riscv-iommu-sys.c
+++ b/hw/riscv/riscv-iommu-sys.c
@@ -26,7 +26,6 @@
 #include "qemu/host-utils.h"
 #include "qemu/module.h"
 #include "qom/object.h"
-#include "exec/exec-all.h"
 #include "trace.h"
 
 #include "riscv-iommu.h"
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index e7568ca227a..fb763e6e69d 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -26,6 +26,7 @@
 #include "qapi/error.h"
 #include "qemu/timer.h"
 
+#include "target/riscv/cpu.h"
 #include "cpu_bits.h"
 #include "riscv-iommu.h"
 #include "riscv-iommu-bits.h"
-- 
2.47.1

[PATCH 6/7] hw/riscv/hart: Make 'riscv_hart.h' header target-agnostic

[Philippe Mathieu-Daudé]

Hardware code using HART rarely needs to knows its internals.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/riscv/riscv_hart.h | 4 ++--
 hw/riscv/virt-acpi-build.c    | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index a6ed73a1956..a2ca455d8b1 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -22,7 +22,7 @@
 #define HW_RISCV_HART_H
 
 #include "hw/sysbus.h"
-#include "target/riscv/cpu.h"
+#include "target/riscv/cpu-qom.h"
 #include "qom/object.h"
 
 #define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
@@ -42,7 +42,7 @@ struct RISCVHartArrayState {
     uint64_t *rnmi_irqvec;
     uint32_t num_rnmi_excpvec;
     uint64_t *rnmi_excpvec;
-    RISCVCPU *harts;
+    ArchCPU *harts;
 };
 
 #endif
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 1ad68005085..0030c21bc41 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -39,6 +39,7 @@
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "system/reset.h"
+#include "target/riscv/cpu.h"
 
 #define ACPI_BUILD_TABLE_SIZE             0x20000
 #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
-- 
2.47.1

[PATCH 7/7] hw/riscv: Move few objects to common_ss[] to build them once

[Philippe Mathieu-Daudé]

opentitan.c, riscv-iommu-pci.c, riscv-iommu-sys.c don't depend
on target-specific knowledge. Move them to common_ss[] to build
them once.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/riscv/meson.build | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 3c7e083aca1..ff578a2e01a 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -2,7 +2,7 @@ riscv_ss = ss.source_set()
 riscv_ss.add(files('boot.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
 riscv_ss.add(files('riscv_hart.c'))
-riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
+common_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
@@ -10,7 +10,8 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
-riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c'))
+riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c'))
+common_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu-pci.c', 'riscv-iommu-sys.c'))
 riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))
 
 hw_arch += {'riscv': riscv_ss}
-- 
2.47.1