From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com
Subject: [PATCH 19/22] target/riscv: convert Ventana V1 to RISCVCPUDef
Date: Thu, 6 Feb 2025 19:27:07 +0100 [thread overview]
Message-ID: <20250206182711.2420505-20-pbonzini@redhat.com> (raw)
In-Reply-To: <20250206182711.2420505-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 75 ++++++++++++++++++++++------------------------
1 file changed, 35 insertions(+), 40 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b2b9b4f6e39..7ebf007c129 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -485,45 +485,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, RISCVCSR *csr_list)
#endif
#if defined(TARGET_RISCV64)
-static void rv64_veyron_v1_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH);
- env->priv_ver = PRIV_VERSION_1_12_0;
-
- /* Enable ISA extensions */
- cpu->cfg.mmu = true;
- cpu->cfg.ext_zifencei = true;
- cpu->cfg.ext_zicsr = true;
- cpu->cfg.pmp = true;
- cpu->cfg.ext_zicbom = true;
- cpu->cfg.cbom_blocksize = 64;
- cpu->cfg.cboz_blocksize = 64;
- cpu->cfg.ext_zicboz = true;
- cpu->cfg.ext_smaia = true;
- cpu->cfg.ext_ssaia = true;
- cpu->cfg.ext_sscofpmf = true;
- cpu->cfg.ext_sstc = true;
- cpu->cfg.ext_svinval = true;
- cpu->cfg.ext_svnapot = true;
- cpu->cfg.ext_svpbmt = true;
- cpu->cfg.ext_smstateen = true;
- cpu->cfg.ext_zba = true;
- cpu->cfg.ext_zbb = true;
- cpu->cfg.ext_zbc = true;
- cpu->cfg.ext_zbs = true;
- cpu->cfg.ext_XVentanaCondOps = true;
-
- cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
- cpu->cfg.marchid = VEYRON_V1_MARCHID;
- cpu->cfg.mimpid = VEYRON_V1_MIMPID;
-
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_SV48);
-#endif
-}
static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
{
@@ -3089,7 +3050,41 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.satp_mode64 = VM_1_10_SV57,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVG | RVC | RVS | RVU | RVH,
+ .priv_spec = PRIV_VERSION_1_12_0,
+
+ /* ISA extensions */
+ .cfg.mmu = true,
+ .cfg.ext_zifencei = true,
+ .cfg.ext_zicsr = true,
+ .cfg.pmp = true,
+ .cfg.ext_zicbom = true,
+ .cfg.cbom_blocksize = 64,
+ .cfg.cboz_blocksize = 64,
+ .cfg.ext_zicboz = true,
+ .cfg.ext_smaia = true,
+ .cfg.ext_ssaia = true,
+ .cfg.ext_sscofpmf = true,
+ .cfg.ext_sstc = true,
+ .cfg.ext_svinval = true,
+ .cfg.ext_svnapot = true,
+ .cfg.ext_svpbmt = true,
+ .cfg.ext_smstateen = true,
+ .cfg.ext_zba = true,
+ .cfg.ext_zbb = true,
+ .cfg.ext_zbc = true,
+ .cfg.ext_zbs = true,
+ .cfg.ext_XVentanaCondOps = true,
+
+ .cfg.mvendorid = VEYRON_V1_MVENDORID,
+ .cfg.marchid = VEYRON_V1_MARCHID,
+ .cfg.mimpid = VEYRON_V1_MIMPID,
+
+ .satp_mode64 = VM_1_10_SV48,
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
#ifdef CONFIG_TCG
--
2.48.1
next prev parent reply other threads:[~2025-02-06 18:28 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 18:26 [PATCH 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-06 18:26 ` [PATCH 01/22] target/riscv: remove unused macro DEFINE_CPU Paolo Bonzini
2025-02-10 0:44 ` Alistair Francis
2025-02-06 18:26 ` [PATCH 02/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-02-06 21:16 ` Richard Henderson
2025-02-09 18:44 ` Philippe Mathieu-Daudé
2025-02-09 18:53 ` Philippe Mathieu-Daudé
2025-02-09 22:20 ` Philippe Mathieu-Daudé
2025-02-09 22:32 ` Philippe Mathieu-Daudé
2025-02-06 18:26 ` [PATCH 03/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-02-18 0:02 ` Alistair Francis
2025-02-06 18:26 ` [PATCH 04/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-02-18 0:05 ` Alistair Francis
2025-02-06 18:26 ` [PATCH 05/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-02-18 0:06 ` Alistair Francis
2025-02-06 18:26 ` [PATCH 06/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-02-18 0:23 ` Alistair Francis
2025-02-18 9:30 ` Paolo Bonzini
2025-02-06 18:26 ` [PATCH 07/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-02-06 18:26 ` [PATCH 08/22] target/riscv: convert profile CPU models " Paolo Bonzini
2025-02-06 18:26 ` [PATCH 09/22] target/riscv: convert bare " Paolo Bonzini
2025-02-06 18:26 ` [PATCH 10/22] target/riscv: move 128-bit check to TCG realize Paolo Bonzini
2025-02-06 18:26 ` [PATCH 11/22] target/riscv: convert dynamic CPU models to RISCVCPUDef Paolo Bonzini
2025-02-06 18:27 ` [PATCH 12/22] target/riscv: convert SiFive E " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 13/22] target/riscv: convert ibex " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 14/22] target/riscv: convert SiFive U " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 15/22] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-02-06 18:27 ` [PATCH 16/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-02-06 18:27 ` [PATCH 17/22] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-02-06 18:27 ` [PATCH 18/22] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-02-06 18:27 ` Paolo Bonzini [this message]
2025-02-06 18:27 ` [PATCH 20/22] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 21/22] target/riscv: remove .instance_post_init Paolo Bonzini
2025-02-06 18:27 ` [PATCH 22/22] target/riscv: move SATP modes out of CPUConfig Paolo Bonzini
2025-02-18 0:25 ` [PATCH 00/22] target/riscv: declarative CPU definitions Alistair Francis
2025-02-18 8:27 ` Paolo Bonzini
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