From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com
Subject: [PATCH 04/22] target/riscv: merge riscv_cpu_class_init with the class_base function
Date: Thu, 6 Feb 2025 19:26:52 +0100 [thread overview]
Message-ID: <20250206182711.2420505-5-pbonzini@redhat.com> (raw)
In-Reply-To: <20250206182711.2420505-1-pbonzini@redhat.com>
Since all TYPE_RISCV_CPU subclasses support a class_data of type
RISCVCPUDef, process it even before calling the .class_init function
for the subclasses.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 803b2a7c3f4..baf4dd017b2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2961,15 +2961,18 @@ static void riscv_cpu_class_base_init(ObjectClass *c, void *data)
} else {
mcc->def = g_new0(RISCVCPUDef, 1);
}
-}
-static void riscv_cpu_class_init(ObjectClass *c, void *data)
-{
- RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
- RISCVCPUDef *def = data;
+ if (data) {
+ RISCVCPUDef *def = data;
+ if (def->misa_mxl_max) {
+ assert(def->misa_mxl_max <= MXL_RV128);
+ mcc->def->misa_mxl_max = def->misa_mxl_max;
+ }
+ }
- mcc->def->misa_mxl_max = def->misa_mxl_max;
- riscv_cpu_validate_misa_mxl(mcc);
+ if (!object_class_is_abstract(c)) {
+ riscv_cpu_validate_misa_mxl(mcc);
+ }
}
static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
@@ -3069,7 +3072,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.name = (type_name), \
.parent = TYPE_RISCV_DYNAMIC_CPU, \
.instance_init = (initfn), \
- .class_init = riscv_cpu_class_init, \
.class_data = &((RISCVCPUDef) { \
.misa_mxl_max = (misa_mxl_max_), \
}), \
@@ -3080,7 +3082,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.name = (type_name), \
.parent = TYPE_RISCV_VENDOR_CPU, \
.instance_init = (initfn), \
- .class_init = riscv_cpu_class_init, \
.class_data = &((RISCVCPUDef) { \
.misa_mxl_max = (misa_mxl_max_), \
}), \
@@ -3091,7 +3092,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
- .class_init = riscv_cpu_class_init, \
.class_data = &((RISCVCPUDef) { \
.misa_mxl_max = (misa_mxl_max_), \
}), \
@@ -3102,7 +3102,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
- .class_init = riscv_cpu_class_init, \
.class_data = &((RISCVCPUDef) { \
.misa_mxl_max = (misa_mxl_max_), \
}), \
--
2.48.1
next prev parent reply other threads:[~2025-02-06 18:27 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 18:26 [PATCH 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-06 18:26 ` [PATCH 01/22] target/riscv: remove unused macro DEFINE_CPU Paolo Bonzini
2025-02-10 0:44 ` Alistair Francis
2025-02-06 18:26 ` [PATCH 02/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-02-06 21:16 ` Richard Henderson
2025-02-09 18:44 ` Philippe Mathieu-Daudé
2025-02-09 18:53 ` Philippe Mathieu-Daudé
2025-02-09 22:20 ` Philippe Mathieu-Daudé
2025-02-09 22:32 ` Philippe Mathieu-Daudé
2025-02-06 18:26 ` [PATCH 03/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-02-18 0:02 ` Alistair Francis
2025-02-06 18:26 ` Paolo Bonzini [this message]
2025-02-18 0:05 ` [PATCH 04/22] target/riscv: merge riscv_cpu_class_init with the class_base function Alistair Francis
2025-02-06 18:26 ` [PATCH 05/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-02-18 0:06 ` Alistair Francis
2025-02-06 18:26 ` [PATCH 06/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-02-18 0:23 ` Alistair Francis
2025-02-18 9:30 ` Paolo Bonzini
2025-02-06 18:26 ` [PATCH 07/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-02-06 18:26 ` [PATCH 08/22] target/riscv: convert profile CPU models " Paolo Bonzini
2025-02-06 18:26 ` [PATCH 09/22] target/riscv: convert bare " Paolo Bonzini
2025-02-06 18:26 ` [PATCH 10/22] target/riscv: move 128-bit check to TCG realize Paolo Bonzini
2025-02-06 18:26 ` [PATCH 11/22] target/riscv: convert dynamic CPU models to RISCVCPUDef Paolo Bonzini
2025-02-06 18:27 ` [PATCH 12/22] target/riscv: convert SiFive E " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 13/22] target/riscv: convert ibex " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 14/22] target/riscv: convert SiFive U " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 15/22] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-02-06 18:27 ` [PATCH 16/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-02-06 18:27 ` [PATCH 17/22] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-02-06 18:27 ` [PATCH 18/22] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 19/22] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 20/22] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-02-06 18:27 ` [PATCH 21/22] target/riscv: remove .instance_post_init Paolo Bonzini
2025-02-06 18:27 ` [PATCH 22/22] target/riscv: move SATP modes out of CPUConfig Paolo Bonzini
2025-02-18 0:25 ` [PATCH 00/22] target/riscv: declarative CPU definitions Alistair Francis
2025-02-18 8:27 ` Paolo Bonzini
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