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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 06/61] tcg: Split out tcg_gen_gvec_3_var
Date: Thu,  6 Feb 2025 11:56:20 -0800	[thread overview]
Message-ID: <20250206195715.2150758-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250206195715.2150758-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg-op-gvec-common.h |   4 ++
 tcg/tcg-op-gvec.c                | 102 +++++++++++++++++++------------
 2 files changed, 68 insertions(+), 38 deletions(-)

diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-common.h
index 877871c101..6e8fccad01 100644
--- a/include/tcg/tcg-op-gvec-common.h
+++ b/include/tcg/tcg-op-gvec-common.h
@@ -236,6 +236,10 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
                      uint32_t maxsz, int64_t c, const GVecGen2i *);
 void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
                      uint32_t maxsz, TCGv_i64 c, const GVecGen2s *);
+void tcg_gen_gvec_3_var(TCGv_ptr dbase, uint32_t dofs,
+                        TCGv_ptr abase, uint32_t aofs,
+                        TCGv_ptr bbase, uint32_t bofs,
+                        uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
 void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
                     uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
 void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 08019421f2..3e53e43354 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -178,9 +178,11 @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
 }
 
 /* Generate a call to a gvec-style helper with three vector operands.  */
-void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
-                        uint32_t oprsz, uint32_t maxsz, int32_t data,
-                        gen_helper_gvec_3 *fn)
+static void expand_3_ool(TCGv_ptr dbase, uint32_t dofs,
+                         TCGv_ptr abase, uint32_t aofs,
+                         TCGv_ptr bbase, uint32_t bofs,
+                         uint32_t oprsz, uint32_t maxsz,
+                         int32_t data, gen_helper_gvec_3 *fn)
 {
     TCGv_ptr a0, a1, a2;
     TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data));
@@ -189,9 +191,9 @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
     a1 = tcg_temp_ebb_new_ptr();
     a2 = tcg_temp_ebb_new_ptr();
 
-    tcg_gen_addi_ptr(a0, tcg_env, dofs);
-    tcg_gen_addi_ptr(a1, tcg_env, aofs);
-    tcg_gen_addi_ptr(a2, tcg_env, bofs);
+    tcg_gen_addi_ptr(a0, dbase, dofs);
+    tcg_gen_addi_ptr(a1, abase, aofs);
+    tcg_gen_addi_ptr(a2, bbase, bofs);
 
     fn(a0, a1, a2, desc);
 
@@ -200,6 +202,14 @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
     tcg_temp_free_ptr(a2);
 }
 
+void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+                        uint32_t oprsz, uint32_t maxsz, int32_t data,
+                        gen_helper_gvec_3 *fn)
+{
+    expand_3_ool(tcg_env, dofs, tcg_env, aofs, tcg_env, bofs,
+                 oprsz, maxsz, data, fn);
+}
+
 /* Generate a call to a gvec-style helper with four vector operands.  */
 void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
                         uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
@@ -789,8 +799,10 @@ static void expand_2s_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
 }
 
 /* Expand OPSZ bytes worth of three-operand operations using i32 elements.  */
-static void expand_3_i32(uint32_t dofs, uint32_t aofs,
-                         uint32_t bofs, uint32_t oprsz, bool load_dest,
+static void expand_3_i32(TCGv_ptr dbase, uint32_t dofs,
+                         TCGv_ptr abase, uint32_t aofs,
+                         TCGv_ptr bbase, uint32_t bofs,
+                         uint32_t oprsz, bool load_dest,
                          void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32))
 {
     TCGv_i32 t0 = tcg_temp_new_i32();
@@ -799,13 +811,13 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs,
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 4) {
-        tcg_gen_ld_i32(t0, tcg_env, aofs + i);
-        tcg_gen_ld_i32(t1, tcg_env, bofs + i);
+        tcg_gen_ld_i32(t0, abase, aofs + i);
+        tcg_gen_ld_i32(t1, bbase, bofs + i);
         if (load_dest) {
-            tcg_gen_ld_i32(t2, tcg_env, dofs + i);
+            tcg_gen_ld_i32(t2, dbase, dofs + i);
         }
         fni(t2, t0, t1);
-        tcg_gen_st_i32(t2, tcg_env, dofs + i);
+        tcg_gen_st_i32(t2, dbase, dofs + i);
     }
     tcg_temp_free_i32(t2);
     tcg_temp_free_i32(t1);
@@ -953,8 +965,10 @@ static void expand_2s_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
 }
 
 /* Expand OPSZ bytes worth of three-operand operations using i64 elements.  */
-static void expand_3_i64(uint32_t dofs, uint32_t aofs,
-                         uint32_t bofs, uint32_t oprsz, bool load_dest,
+static void expand_3_i64(TCGv_ptr dbase, uint32_t dofs,
+                         TCGv_ptr abase, uint32_t aofs,
+                         TCGv_ptr bbase, uint32_t bofs,
+                         uint32_t oprsz, bool load_dest,
                          void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64))
 {
     TCGv_i64 t0 = tcg_temp_new_i64();
@@ -963,13 +977,13 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs,
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 8) {
-        tcg_gen_ld_i64(t0, tcg_env, aofs + i);
-        tcg_gen_ld_i64(t1, tcg_env, bofs + i);
+        tcg_gen_ld_i64(t0, abase, aofs + i);
+        tcg_gen_ld_i64(t1, bbase, bofs + i);
         if (load_dest) {
-            tcg_gen_ld_i64(t2, tcg_env, dofs + i);
+            tcg_gen_ld_i64(t2, dbase, dofs + i);
         }
         fni(t2, t0, t1);
-        tcg_gen_st_i64(t2, tcg_env, dofs + i);
+        tcg_gen_st_i64(t2, dbase, dofs + i);
     }
     tcg_temp_free_i64(t2);
     tcg_temp_free_i64(t1);
@@ -1114,8 +1128,9 @@ static void expand_2s_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
 }
 
 /* Expand OPSZ bytes worth of three-operand operations using host vectors.  */
-static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
-                         uint32_t bofs, uint32_t oprsz,
+static void expand_3_vec(unsigned vece, TCGv_ptr dbase, uint32_t dofs,
+                         TCGv_ptr abase, uint32_t aofs,
+                         TCGv_ptr bbase, uint32_t bofs, uint32_t oprsz,
                          uint32_t tysz, TCGType type, bool load_dest,
                          void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
 {
@@ -1124,13 +1139,13 @@ static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
         TCGv_vec t1 = tcg_temp_new_vec(type);
         TCGv_vec t2 = tcg_temp_new_vec(type);
 
-        tcg_gen_ld_vec(t0, tcg_env, aofs + i);
-        tcg_gen_ld_vec(t1, tcg_env, bofs + i);
+        tcg_gen_ld_vec(t0, abase, aofs + i);
+        tcg_gen_ld_vec(t1, bbase, bofs + i);
         if (load_dest) {
-            tcg_gen_ld_vec(t2, tcg_env, dofs + i);
+            tcg_gen_ld_vec(t2, dbase, dofs + i);
         }
         fni(vece, t2, t0, t1);
-        tcg_gen_st_vec(t2, tcg_env, dofs + i);
+        tcg_gen_st_vec(t2, dbase, dofs + i);
     }
 }
 
@@ -1432,8 +1447,10 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
 }
 
 /* Expand a vector three-operand operation.  */
-void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
-                    uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
+void tcg_gen_gvec_3_var(TCGv_ptr dbase, uint32_t dofs,
+                        TCGv_ptr abase, uint32_t aofs,
+                        TCGv_ptr bbase, uint32_t bofs,
+                        uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
 {
     const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
     const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
@@ -1441,7 +1458,7 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
     uint32_t some;
 
     check_size_align(oprsz, maxsz, dofs | aofs | bofs);
-    check_overlap_3(tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, maxsz);
+    check_overlap_3(dbase, dofs, abase, aofs, bbase, bofs, maxsz);
 
     type = 0;
     if (g->fniv) {
@@ -1454,8 +1471,8 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
          * that e.g. size == 80 would be expanded with 2x32 + 1x16.
          */
         some = QEMU_ALIGN_DOWN(oprsz, 32);
-        expand_3_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256,
-                     g->load_dest, g->fniv);
+        expand_3_vec(g->vece, dbase, dofs, abase, aofs, bbase, bofs,
+                     some, 32, TCG_TYPE_V256, g->load_dest, g->fniv);
         if (some == oprsz) {
             break;
         }
@@ -1466,23 +1483,25 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
         maxsz -= some;
         /* fallthru */
     case TCG_TYPE_V128:
-        expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128,
-                     g->load_dest, g->fniv);
+        expand_3_vec(g->vece, dbase, dofs, abase, aofs, bbase, bofs,
+                     oprsz, 16, TCG_TYPE_V128, g->load_dest, g->fniv);
         break;
     case TCG_TYPE_V64:
-        expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64,
-                     g->load_dest, g->fniv);
+        expand_3_vec(g->vece, dbase, dofs, abase, aofs, bbase, bofs,
+                     oprsz, 8, TCG_TYPE_V64, g->load_dest, g->fniv);
         break;
 
     case 0:
         if (g->fni8 && check_size_impl(oprsz, 8)) {
-            expand_3_i64(dofs, aofs, bofs, oprsz, g->load_dest, g->fni8);
+            expand_3_i64(dbase, dofs, abase, aofs, bbase, bofs,
+                         oprsz, g->load_dest, g->fni8);
         } else if (g->fni4 && check_size_impl(oprsz, 4)) {
-            expand_3_i32(dofs, aofs, bofs, oprsz, g->load_dest, g->fni4);
+            expand_3_i32(dbase, dofs, abase, aofs, bbase, bofs,
+                         oprsz, g->load_dest, g->fni4);
         } else {
             assert(g->fno != NULL);
-            tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz,
-                               maxsz, g->data, g->fno);
+            expand_3_ool(dbase, dofs, abase, aofs, bbase, bofs,
+                         oprsz, maxsz, g->data, g->fno);
             oprsz = maxsz;
         }
         break;
@@ -1493,10 +1512,17 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
     tcg_swap_vecop_list(hold_list);
 
     if (oprsz < maxsz) {
-        expand_clr(tcg_env, dofs + oprsz, maxsz - oprsz);
+        expand_clr(dbase, dofs + oprsz, maxsz - oprsz);
     }
 }
 
+void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+                    uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
+{
+    tcg_gen_gvec_3_var(tcg_env, dofs, tcg_env, aofs, tcg_env, bofs,
+                       oprsz, maxsz, g);
+}
+
 /* Expand a vector operation with three vectors and an immediate.  */
 void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
                      uint32_t oprsz, uint32_t maxsz, int64_t c,
-- 
2.43.0



  parent reply	other threads:[~2025-02-06 19:58 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-06 19:56 [PATCH 00/61] target/arm: Implement FEAT_SME2 Richard Henderson
2025-02-06 19:56 ` [PATCH 01/61] tcg: Add dbase argument to do_dup_store Richard Henderson
2025-02-06 19:56 ` [PATCH 02/61] tcg: Add dbase argument to do_dup Richard Henderson
2025-02-06 19:56 ` [PATCH 03/61] tcg: Add dbase argument to expand_clr Richard Henderson
2025-02-06 19:56 ` [PATCH 04/61] tcg: Add base arguments to check_overlap_[234] Richard Henderson
2025-02-06 19:56 ` [PATCH 05/61] tcg: Split out tcg_gen_gvec_2_var Richard Henderson
2025-02-06 19:56 ` Richard Henderson [this message]
2025-02-06 19:56 ` [PATCH 07/61] tcg: Split out tcg_gen_gvec_mov_var Richard Henderson
2025-02-06 19:56 ` [PATCH 08/61] tcg: Split out tcg_gen_gvec_{add,sub}_var Richard Henderson
2025-02-06 19:56 ` [PATCH 09/61] target/arm: Introduce FPST_ZA, FPST_ZA_F16 Richard Henderson
2025-02-06 19:56 ` [PATCH 10/61] target/arm: Use FPST_ZA for sme_fmopa_[hsd] Richard Henderson
2025-02-06 19:56 ` [PATCH 11/61] target/arm: Rename zarray to za_state.za Richard Henderson
2025-02-06 19:56 ` [PATCH 12/61] target/arm: Add isar_feature_aa64_sme2* Richard Henderson
2025-02-06 19:56 ` [PATCH 13/61] target/arm: Add ZT0 Richard Henderson
2025-02-06 19:56 ` [PATCH 14/61] target/arm: Add zt0_excp_el to DisasContext Richard Henderson
2025-02-06 19:56 ` [PATCH 15/61] target/arm: Implement SME2 ZERO ZT0 Richard Henderson
2025-02-06 19:56 ` [PATCH 16/61] target/arm: Implement SME2 LDR/STR ZT0 Richard Henderson
2025-02-06 19:56 ` [PATCH 17/61] target/arm: Implement SME2 MOVT Richard Henderson
2025-02-06 19:56 ` [PATCH 18/61] target/arm: Split get_tile_rowcol argument tile_index Richard Henderson
2025-02-06 19:56 ` [PATCH 19/61] target/arm: Rename MOVA for translate Richard Henderson
2025-02-06 19:56 ` [PATCH 20/61] target/arm: Implement SME2 MOVA to/from tile, multiple registers Richard Henderson
2025-02-06 19:56 ` [PATCH 21/61] target/arm: Split out get_zarray Richard Henderson
2025-02-06 19:56 ` [PATCH 22/61] target/arm: Implement SME2 MOVA to/from array, multiple registers Richard Henderson
2025-02-06 19:56 ` [PATCH 23/61] target/arm: Implement SME2 BMOPA Richard Henderson
2025-02-06 19:56 ` [PATCH 24/61] target/arm: Implement SME2 SMOPS, UMOPS (2-way) Richard Henderson
2025-02-06 19:56 ` [PATCH 25/61] target/arm: Introduce gen_gvec_sve2_sqdmulh Richard Henderson
2025-02-06 19:56 ` [PATCH 26/61] target/arm: Implement SME2 Multiple and Single SVE Destructive Richard Henderson
2025-02-06 19:56 ` [PATCH 27/61] target/arm: Implement SME2 Multiple Vectors " Richard Henderson
2025-02-06 19:56 ` [PATCH 28/61] target/arm: Implement SME2 ADD/SUB (array results, multiple and single vector) Richard Henderson
2025-02-06 19:56 ` [PATCH 29/61] target/arm: Implement SME2 ADD/SUB (array results, multiple vectors) Richard Henderson
2025-02-06 19:56 ` [PATCH 30/61] target/arm: Pass ZA to helper_sve2_fmlal_zz[zx]w_s Richard Henderson
2025-02-06 19:56 ` [PATCH 31/61] target/arm: Implement SME2 FMLAL, BFMLAL Richard Henderson
2025-02-06 19:56 ` [PATCH 32/61] target/arm: Implement SME2 FDOT Richard Henderson
2025-02-06 19:56 ` [PATCH 33/61] target/arm: Implement SME2 BFDOT Richard Henderson
2025-02-06 19:56 ` [PATCH 34/61] target/arm: Implement SME2 FVDOT, BFVDOT Richard Henderson
2025-02-06 19:56 ` [PATCH 35/61] target/arm: Rename helper_gvec_*dot_[bh] to *_4[bh] Richard Henderson
2025-02-06 19:56 ` [PATCH 36/61] target/arm: Remove helper_gvec_sudot_idx_4b Richard Henderson
2025-02-06 19:56 ` [PATCH 37/61] target/arm: Implemement SME2 SDOT, UDOT, USDOT, SUDOT Richard Henderson
2025-02-06 19:56 ` [PATCH 38/61] target/arm: Implement SME2 SVDOT, UVDOT, SUVDOT, USVDOT Richard Henderson
2025-02-06 19:56 ` [PATCH 39/61] target/arm: Implement SME2 SMLAL, SMLSL, UMLAL, UMLSL Richard Henderson
2025-02-06 19:56 ` [PATCH 40/61] target/arm: Implement SME2 SMLALL, SMLSLL, UMLALL, UMLSLL Richard Henderson
2025-02-06 19:56 ` [PATCH 41/61] target/arm: Rename gvec_fml[as]_[hs] with _nf_ infix Richard Henderson
2025-02-06 19:56 ` [PATCH 42/61] target/arm: Implement SME2 FMLA, FMLS Richard Henderson
2025-02-06 19:56 ` [PATCH 43/61] target/arm: Implement SME2 BFMLA, BFMLS Richard Henderson
2025-02-06 19:56 ` [PATCH 44/61] target/arm: Implement SME2 FADD, FSUB, BFADD, BFSUB Richard Henderson
2025-02-06 19:56 ` [PATCH 45/61] target/arm: Remove CPUARMState.vfp.scratch Richard Henderson
2025-02-06 19:57 ` [PATCH 46/61] target/arm: Implement SME2 BFCVT, BFCVTN, FCVT, FCVTN Richard Henderson
2025-02-06 19:57 ` [PATCH 47/61] target/arm: Implement SME2 FCVT (widening), FCVTL Richard Henderson
2025-02-06 19:57 ` [PATCH 48/61] target/arm: Implement SME2 FCVTZS, FCVTZU Richard Henderson
2025-02-06 19:57 ` [PATCH 49/61] target/arm: Implement SME2 SCVTF, UCVTF Richard Henderson
2025-02-06 19:57 ` [PATCH 50/61] target/arm: Implement SME2 FRINTN, FRINTP, FRINTM, FRINTA Richard Henderson
2025-02-06 19:57 ` [PATCH 51/61] target/arm: Introduce do_[us]sat_[bhs] macros Richard Henderson
2025-02-06 19:57 ` [PATCH 52/61] target/arm: Use do_[us]sat_[bhs] in sve_helper.c Richard Henderson
2025-02-06 19:57 ` [PATCH 53/61] target/arm: Implement SME2 SQCVT, UQCVT, SQCVTU Richard Henderson
2025-02-06 19:57 ` [PATCH 54/61] target/arm: Implement SME2 SUNPK, UUNPK Richard Henderson
2025-02-06 19:57 ` [PATCH 55/61] target/arm: Implement SME2 ZIP, UZP (four registers) Richard Henderson
2025-02-06 19:57 ` [PATCH 56/61] target/arm: Move do_urshr, do_srshr to vec_internal.h Richard Henderson
2025-02-06 19:57 ` [PATCH 57/61] target/arm: Implement SME2 SQRSHR, UQRSHR, SQRSHRN Richard Henderson
2025-02-06 19:57 ` [PATCH 58/61] target/arm: Implement SME2 ZIP, UZP (two registers) Richard Henderson
2025-02-06 19:57 ` [PATCH 59/61] target/arm: Implement SME2 FCLAMP, SCLAMP, UCLAMP Richard Henderson
2025-02-06 19:57 ` [PATCH 60/61] target/arm: Implement SME2 SEL Richard Henderson
2025-02-06 19:57 ` [PATCH 61/61] target/arm: Enable FEAT_SME2, FEAT_SME_F16F16, FEAT_SVE_B16B16 on -cpu max Richard Henderson
2025-02-24 20:27 ` [PATCH 00/61] target/arm: Implement FEAT_SME2 Richard Henderson
2025-02-24 20:35   ` Richard Henderson

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