* [PATCH] target/sparc: fake UltraSPARC T1 PCR and PIC registers
@ 2025-01-31 21:44 Artyom Tarasenko
2025-02-02 21:46 ` Richard Henderson
0 siblings, 1 reply; 6+ messages in thread
From: Artyom Tarasenko @ 2025-01-31 21:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Artyom Tarasenko, Richard Henderson, Mark Cave-Ayland
fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara target.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
target/sparc/insns.decode | 7 ++++++-
target/sparc/translate.c | 20 ++++++++++++++++++++
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 989c20b44a..504147563c 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -96,7 +96,10 @@ CALL 01 i:s30
RDTICK 10 rd:5 101000 00100 0 0000000000000
RDPC 10 rd:5 101000 00101 0 0000000000000
RDFPRS 10 rd:5 101000 00110 0 0000000000000
- RDASR17 10 rd:5 101000 10001 0 0000000000000
+ {
+ RDASR17 10 rd:5 101000 10001 0 0000000000000
+ RDPIC 10 rd:5 101000 10001 0 0000000000000
+ }
RDGSR 10 rd:5 101000 10011 0 0000000000000
RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
@@ -114,6 +117,8 @@ CALL 01 i:s30
WRCCR 10 00010 110000 ..... . ............. @n_r_ri
WRASI 10 00011 110000 ..... . ............. @n_r_ri
WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
+ WRPCR 10 10000 110000 01000 0 0000000000000
+ WRPIC 10 10001 110000 01000 0 0000000000000
{
WRGSR 10 10011 110000 ..... . ............. @n_r_ri
WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 7e5c7351cb..285c9b0a59 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2882,6 +2882,15 @@ static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
+static TCGv do_rdpic(DisasContext *dc, TCGv dst)
+{
+ tcg_gen_movi_tl(dst, 0UL);
+ return dst;
+}
+
+TRANS(RDPIC, HYPV, do_rd_special, true, a->rd, do_rdpic)
+
+
static TCGv do_rdccr(DisasContext *dc, TCGv dst)
{
gen_helper_rdccr(dst, tcg_env);
@@ -3315,6 +3324,17 @@ static void do_wrfprs(DisasContext *dc, TCGv src)
TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs)
+static bool do_priv_nop(DisasContext *dc, bool priv)
+{
+ if (!priv) {
+ return raise_priv(dc);
+ }
+ return advance_pc(dc);
+}
+
+TRANS(WRPCR, HYPV, do_priv_nop, supervisor(dc))
+TRANS(WRPIC, HYPV, do_priv_nop, supervisor(dc))
+
static void do_wrgsr(DisasContext *dc, TCGv src)
{
gen_trap_ifnofpu(dc);
--
2.43.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] target/sparc: fake UltraSPARC T1 PCR and PIC registers
2025-01-31 21:44 [PATCH] target/sparc: fake UltraSPARC T1 PCR and PIC registers Artyom Tarasenko
@ 2025-02-02 21:46 ` Richard Henderson
2025-02-02 21:57 ` Richard Henderson
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Richard Henderson @ 2025-02-02 21:46 UTC (permalink / raw)
To: Artyom Tarasenko, qemu-devel; +Cc: Mark Cave-Ayland
On 1/31/25 13:44, Artyom Tarasenko wrote:
> fake access to
> PCR Performance Control Register
> and
> PIC Performance Instrumentation Counter.
>
> Ignore writes in privileged mode, and return 0 on reads.
>
> This allows booting Tribblix, MilaX and v9os under Niagara target.
>
> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
> ---
> target/sparc/insns.decode | 7 ++++++-
> target/sparc/translate.c | 20 ++++++++++++++++++++
> 2 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
> index 989c20b44a..504147563c 100644
> --- a/target/sparc/insns.decode
> +++ b/target/sparc/insns.decode
> @@ -96,7 +96,10 @@ CALL 01 i:s30
> RDTICK 10 rd:5 101000 00100 0 0000000000000
> RDPC 10 rd:5 101000 00101 0 0000000000000
> RDFPRS 10 rd:5 101000 00110 0 0000000000000
> - RDASR17 10 rd:5 101000 10001 0 0000000000000
> + {
> + RDASR17 10 rd:5 101000 10001 0 0000000000000
> + RDPIC 10 rd:5 101000 10001 0 0000000000000
> + }
> RDGSR 10 rd:5 101000 10011 0 0000000000000
> RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
> RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
> @@ -114,6 +117,8 @@ CALL 01 i:s30
> WRCCR 10 00010 110000 ..... . ............. @n_r_ri
> WRASI 10 00011 110000 ..... . ............. @n_r_ri
> WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
> + WRPCR 10 10000 110000 01000 0 0000000000000
> + WRPIC 10 10001 110000 01000 0 0000000000000
> {
> WRGSR 10 10011 110000 ..... . ............. @n_r_ri
> WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
> diff --git a/target/sparc/translate.c b/target/sparc/translate.c
> index 7e5c7351cb..285c9b0a59 100644
> --- a/target/sparc/translate.c
> +++ b/target/sparc/translate.c
> @@ -2882,6 +2882,15 @@ static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
>
> TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
>
> +static TCGv do_rdpic(DisasContext *dc, TCGv dst)
> +{
> + tcg_gen_movi_tl(dst, 0UL);
> + return dst;
> +}
return tcg_constant_tl(0);
> +
> +TRANS(RDPIC, HYPV, do_rd_special, true, a->rd, do_rdpic)
Surely reads are not allowed in user mode.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/sparc: fake UltraSPARC T1 PCR and PIC registers
2025-02-02 21:46 ` Richard Henderson
@ 2025-02-02 21:57 ` Richard Henderson
2025-02-09 21:12 ` [PATCH v2] " Artyom Tarasenko
2025-02-09 21:16 ` [PATCH] " Artyom Tarasenko
2 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2025-02-02 21:57 UTC (permalink / raw)
To: Artyom Tarasenko, qemu-devel; +Cc: Mark Cave-Ayland
On 2/2/25 13:46, Richard Henderson wrote:
> On 1/31/25 13:44, Artyom Tarasenko wrote:
>> fake access to
>> PCR Performance Control Register
>> and
>> PIC Performance Instrumentation Counter.
>>
>> Ignore writes in privileged mode, and return 0 on reads.
>>
>> This allows booting Tribblix, MilaX and v9os under Niagara target.
>>
>> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
>> ---
>> target/sparc/insns.decode | 7 ++++++-
>> target/sparc/translate.c | 20 ++++++++++++++++++++
>> 2 files changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
>> index 989c20b44a..504147563c 100644
>> --- a/target/sparc/insns.decode
>> +++ b/target/sparc/insns.decode
>> @@ -96,7 +96,10 @@ CALL 01 i:s30
>> RDTICK 10 rd:5 101000 00100 0 0000000000000
>> RDPC 10 rd:5 101000 00101 0 0000000000000
>> RDFPRS 10 rd:5 101000 00110 0 0000000000000
>> - RDASR17 10 rd:5 101000 10001 0 0000000000000
>> + {
>> + RDASR17 10 rd:5 101000 10001 0 0000000000000
>> + RDPIC 10 rd:5 101000 10001 0 0000000000000
>> + }
>> RDGSR 10 rd:5 101000 10011 0 0000000000000
>> RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
>> RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
>> @@ -114,6 +117,8 @@ CALL 01 i:s30
>> WRCCR 10 00010 110000 ..... . ............. @n_r_ri
>> WRASI 10 00011 110000 ..... . ............. @n_r_ri
>> WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
>> + WRPCR 10 10000 110000 01000 0 0000000000000
>> + WRPIC 10 10001 110000 01000 0 0000000000000
>> {
>> WRGSR 10 10011 110000 ..... . ............. @n_r_ri
>> WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
>> diff --git a/target/sparc/translate.c b/target/sparc/translate.c
>> index 7e5c7351cb..285c9b0a59 100644
>> --- a/target/sparc/translate.c
>> +++ b/target/sparc/translate.c
>> @@ -2882,6 +2882,15 @@ static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
>> TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
>> +static TCGv do_rdpic(DisasContext *dc, TCGv dst)
>> +{
>> + tcg_gen_movi_tl(dst, 0UL);
>> + return dst;
>> +}
>
> return tcg_constant_tl(0);
>
>> +
>> +TRANS(RDPIC, HYPV, do_rd_special, true, a->rd, do_rdpic)
>
> Surely reads are not allowed in user mode.
You might as well implement RDPCR as well, which *is* privileged.
Since PCR=0, then RDPCR is allowed.
It might be worthwhile to implement PCR, or at least PCR.PRIV.
r~
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2] target/sparc: fake UltraSPARC T1 PCR and PIC registers
2025-02-02 21:46 ` Richard Henderson
2025-02-02 21:57 ` Richard Henderson
@ 2025-02-09 21:12 ` Artyom Tarasenko
2025-02-15 20:05 ` Richard Henderson
2025-02-09 21:16 ` [PATCH] " Artyom Tarasenko
2 siblings, 1 reply; 6+ messages in thread
From: Artyom Tarasenko @ 2025-02-09 21:12 UTC (permalink / raw)
To: qemu-devel; +Cc: Artyom Tarasenko, Richard Henderson, Mark Cave-Ayland
fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara target.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
target/sparc/insns.decode | 7 ++++++-
target/sparc/translate.c | 19 +++++++++++++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 989c20b44a..504147563c 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -96,7 +96,10 @@ CALL 01 i:s30
RDTICK 10 rd:5 101000 00100 0 0000000000000
RDPC 10 rd:5 101000 00101 0 0000000000000
RDFPRS 10 rd:5 101000 00110 0 0000000000000
- RDASR17 10 rd:5 101000 10001 0 0000000000000
+ {
+ RDASR17 10 rd:5 101000 10001 0 0000000000000
+ RDPIC 10 rd:5 101000 10001 0 0000000000000
+ }
RDGSR 10 rd:5 101000 10011 0 0000000000000
RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
@@ -114,6 +117,8 @@ CALL 01 i:s30
WRCCR 10 00010 110000 ..... . ............. @n_r_ri
WRASI 10 00011 110000 ..... . ............. @n_r_ri
WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
+ WRPCR 10 10000 110000 01000 0 0000000000000
+ WRPIC 10 10001 110000 01000 0 0000000000000
{
WRGSR 10 10011 110000 ..... . ............. @n_r_ri
WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 7e5c7351cb..bfe63649db 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2882,6 +2882,14 @@ static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
+static TCGv do_rdpic(DisasContext *dc, TCGv dst)
+{
+ return tcg_constant_tl(0);
+}
+
+TRANS(RDPIC, HYPV, do_rd_special, supervisor(dc), a->rd, do_rdpic)
+
+
static TCGv do_rdccr(DisasContext *dc, TCGv dst)
{
gen_helper_rdccr(dst, tcg_env);
@@ -3315,6 +3323,17 @@ static void do_wrfprs(DisasContext *dc, TCGv src)
TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs)
+static bool do_priv_nop(DisasContext *dc, bool priv)
+{
+ if (!priv) {
+ return raise_priv(dc);
+ }
+ return advance_pc(dc);
+}
+
+TRANS(WRPCR, HYPV, do_priv_nop, supervisor(dc))
+TRANS(WRPIC, HYPV, do_priv_nop, supervisor(dc))
+
static void do_wrgsr(DisasContext *dc, TCGv src)
{
gen_trap_ifnofpu(dc);
--
2.43.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] target/sparc: fake UltraSPARC T1 PCR and PIC registers
2025-02-02 21:46 ` Richard Henderson
2025-02-02 21:57 ` Richard Henderson
2025-02-09 21:12 ` [PATCH v2] " Artyom Tarasenko
@ 2025-02-09 21:16 ` Artyom Tarasenko
2 siblings, 0 replies; 6+ messages in thread
From: Artyom Tarasenko @ 2025-02-09 21:16 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Mark Cave-Ayland
On Sun, Feb 2, 2025 at 10:47 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 1/31/25 13:44, Artyom Tarasenko wrote:
> > fake access to
> > PCR Performance Control Register
> > and
> > PIC Performance Instrumentation Counter.
> >
> > Ignore writes in privileged mode, and return 0 on reads.
> >
> > This allows booting Tribblix, MilaX and v9os under Niagara target.
> >
> > Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
> > ---
> > target/sparc/insns.decode | 7 ++++++-
> > target/sparc/translate.c | 20 ++++++++++++++++++++
> > 2 files changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
> > index 989c20b44a..504147563c 100644
> > --- a/target/sparc/insns.decode
> > +++ b/target/sparc/insns.decode
> > @@ -96,7 +96,10 @@ CALL 01 i:s30
> > RDTICK 10 rd:5 101000 00100 0 0000000000000
> > RDPC 10 rd:5 101000 00101 0 0000000000000
> > RDFPRS 10 rd:5 101000 00110 0 0000000000000
> > - RDASR17 10 rd:5 101000 10001 0 0000000000000
> > + {
> > + RDASR17 10 rd:5 101000 10001 0 0000000000000
> > + RDPIC 10 rd:5 101000 10001 0 0000000000000
> > + }
> > RDGSR 10 rd:5 101000 10011 0 0000000000000
> > RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
> > RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
> > @@ -114,6 +117,8 @@ CALL 01 i:s30
> > WRCCR 10 00010 110000 ..... . ............. @n_r_ri
> > WRASI 10 00011 110000 ..... . ............. @n_r_ri
> > WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
> > + WRPCR 10 10000 110000 01000 0 0000000000000
> > + WRPIC 10 10001 110000 01000 0 0000000000000
> > {
> > WRGSR 10 10011 110000 ..... . ............. @n_r_ri
> > WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
> > diff --git a/target/sparc/translate.c b/target/sparc/translate.c
> > index 7e5c7351cb..285c9b0a59 100644
> > --- a/target/sparc/translate.c
> > +++ b/target/sparc/translate.c
> > @@ -2882,6 +2882,15 @@ static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst)
> >
> > TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config)
> >
> > +static TCGv do_rdpic(DisasContext *dc, TCGv dst)
> > +{
> > + tcg_gen_movi_tl(dst, 0UL);
> > + return dst;
> > +}
>
> return tcg_constant_tl(0);
>
> > +
> > +TRANS(RDPIC, HYPV, do_rd_special, true, a->rd, do_rdpic)
>
> Surely reads are not allowed in user mode.
Thanks Richard, addressed it in v2.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] target/sparc: fake UltraSPARC T1 PCR and PIC registers
2025-02-09 21:12 ` [PATCH v2] " Artyom Tarasenko
@ 2025-02-15 20:05 ` Richard Henderson
0 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2025-02-15 20:05 UTC (permalink / raw)
To: Artyom Tarasenko, qemu-devel; +Cc: Mark Cave-Ayland
On 2/9/25 13:12, Artyom Tarasenko wrote:
> fake access to
> PCR Performance Control Register
> and
> PIC Performance Instrumentation Counter.
>
> Ignore writes in privileged mode, and return 0 on reads.
>
> This allows booting Tribblix, MilaX and v9os under Niagara target.
>
> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
> ---
> target/sparc/insns.decode | 7 ++++++-
> target/sparc/translate.c | 19 +++++++++++++++++++
> 2 files changed, 25 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
and queued, thanks.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2025-01-31 21:44 [PATCH] target/sparc: fake UltraSPARC T1 PCR and PIC registers Artyom Tarasenko
2025-02-02 21:46 ` Richard Henderson
2025-02-02 21:57 ` Richard Henderson
2025-02-09 21:12 ` [PATCH v2] " Artyom Tarasenko
2025-02-15 20:05 ` Richard Henderson
2025-02-09 21:16 ` [PATCH] " Artyom Tarasenko
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