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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	qemu-riscv@nongnu.org
Subject: [PATCH v2 05/11] target/riscv: Convert misa_mxl_max using GLib macros
Date: Mon, 10 Feb 2025 14:31:28 +0100	[thread overview]
Message-ID: <20250210133134.90879-6-philmd@linaro.org> (raw)
In-Reply-To: <20250210133134.90879-1-philmd@linaro.org>

Use GLib conversion macros to pass misa_mxl_max as
riscv_cpu_class_init() class data.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
Cc: qemu-riscv@nongnu.org
---
 target/riscv/cpu.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f3ad7f88f0e..9fe1b23a297 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2955,7 +2955,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
 {
     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 
-    mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
+    mcc->misa_mxl_max = (RISCVMXL)GPOINTER_TO_UINT(data);
     riscv_cpu_validate_misa_mxl(mcc);
 }
 
@@ -3057,7 +3057,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
         .parent = TYPE_RISCV_CPU,                           \
         .instance_init = (initfn),                          \
         .class_init = riscv_cpu_class_init,                 \
-        .class_data = (void *)(misa_mxl_max)                \
+        .class_data = GUINT_TO_POINTER(misa_mxl_max)        \
     }
 
 #define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \
@@ -3066,7 +3066,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
         .parent = TYPE_RISCV_DYNAMIC_CPU,                   \
         .instance_init = (initfn),                          \
         .class_init = riscv_cpu_class_init,                 \
-        .class_data = (void *)(misa_mxl_max)                \
+        .class_data = GUINT_TO_POINTER(misa_mxl_max)        \
     }
 
 #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn)  \
@@ -3075,7 +3075,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
         .parent = TYPE_RISCV_VENDOR_CPU,                    \
         .instance_init = (initfn),                          \
         .class_init = riscv_cpu_class_init,                 \
-        .class_data = (void *)(misa_mxl_max)                \
+        .class_data = GUINT_TO_POINTER(misa_mxl_max)        \
     }
 
 #define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn)    \
@@ -3084,7 +3084,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
         .parent = TYPE_RISCV_BARE_CPU,                      \
         .instance_init = (initfn),                          \
         .class_init = riscv_cpu_class_init,                 \
-        .class_data = (void *)(misa_mxl_max)                \
+        .class_data = GUINT_TO_POINTER(misa_mxl_max)        \
     }
 
 #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
@@ -3093,7 +3093,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
         .parent = TYPE_RISCV_BARE_CPU,                      \
         .instance_init = (initfn),                          \
         .class_init = riscv_cpu_class_init,                 \
-        .class_data = (void *)(misa_mxl_max)                \
+        .class_data = GUINT_TO_POINTER(misa_mxl_max)        \
     }
 
 static const TypeInfo riscv_cpu_type_infos[] = {
-- 
2.47.1



  parent reply	other threads:[~2025-02-10 13:33 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-10 13:31 [PATCH v2 00/11] qom: Constify class_data Philippe Mathieu-Daudé
2025-02-10 13:31 ` [PATCH v2 01/11] target/i386: Constify X86CPUModel uses Philippe Mathieu-Daudé
2025-02-10 16:30   ` Richard Henderson
2025-02-10 13:31 ` [PATCH v2 02/11] target/sparc: Constify SPARCCPUClass::cpu_def Philippe Mathieu-Daudé
2025-02-10 16:30   ` Richard Henderson
2025-02-10 13:31 ` [PATCH v2 03/11] target/xtensa: Finalize config in xtensa_register_core() Philippe Mathieu-Daudé
2025-02-10 16:30   ` Richard Henderson
2025-02-10 17:02     ` Max Filippov
2025-02-10 13:31 ` [PATCH v2 04/11] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Philippe Mathieu-Daudé
2025-02-10 16:31   ` Richard Henderson
2025-02-10 13:31 ` Philippe Mathieu-Daudé [this message]
2025-02-10 16:34   ` [PATCH v2 05/11] target/riscv: Convert misa_mxl_max using GLib macros Richard Henderson
2025-02-10 13:31 ` [PATCH v2 06/11] hw: Declare various const data as 'const' Philippe Mathieu-Daudé
2025-02-10 16:35   ` Richard Henderson
2025-02-10 13:31 ` [PATCH v2 07/11] hw: Make class data 'const' Philippe Mathieu-Daudé
2025-02-10 16:36   ` Richard Henderson
2025-02-10 13:31 ` [PATCH v2 08/11] qom: Have class_base_init() take a const data argument Philippe Mathieu-Daudé
2025-02-10 16:36   ` Richard Henderson
2025-02-10 13:31 ` [PATCH v2 09/11] qom: Have class_init() " Philippe Mathieu-Daudé
2025-02-10 16:51   ` Richard Henderson
2025-02-10 17:22     ` Philippe Mathieu-Daudé
2025-02-10 13:31 ` [PATCH v2 10/11] qom: Constify TypeInfo::class_data Philippe Mathieu-Daudé
2025-02-10 16:54   ` Richard Henderson
2025-02-10 13:31 ` [PATCH v2 11/11] qom: Constify InterfaceInfo[] interfaces Philippe Mathieu-Daudé
2025-02-10 16:55   ` Richard Henderson
2025-02-10 13:46 ` [PATCH v2 00/11] qom: Constify class_data Philippe Mathieu-Daudé
2025-02-10 17:02   ` Richard Henderson
2025-02-10 17:21     ` Philippe Mathieu-Daudé
2025-03-06 13:16 ` Philippe Mathieu-Daudé

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