* [PULL 00/12] target-arm queue
@ 2019-12-20 14:26 Peter Maydell
2020-01-06 10:32 ` Peter Maydell
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2019-12-20 14:26 UTC (permalink / raw)
To: qemu-devel
One last arm pullreq before I stop work for the end of the year...
-- PMM
The following changes since commit 8e5943260a8f765216674ee87ce8588cc4e7463e:
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-12-20 12:46:10 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191220
for you to fetch changes up to c8fa6079eb35888587f1be27c1590da4edcc5098:
arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() (2019-12-20 14:03:00 +0000)
----------------------------------------------------------------
target-arm queue:
* Support emulating the generic timers at frequencies other than 62.5MHz
* Various fixes for SMMUv3 emulation bugs
* Improve assert error message for hflags mismatches
* arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on()
----------------------------------------------------------------
Andrew Jeffery (4):
target/arm: Remove redundant scaling of nexttick
target/arm: Abstract the generic timer frequency
target/arm: Prepare generic timer for per-platform CNTFRQ
ast2600: Configure CNTFRQ at 1125MHz
Niek Linnenbank (1):
arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on()
Philippe Mathieu-Daudé (1):
target/arm: Display helpful message when hflags mismatch
Simon Veith (6):
hw/arm/smmuv3: Apply address mask to linear strtab base address
hw/arm/smmuv3: Correct SMMU_BASE_ADDR_MASK value
hw/arm/smmuv3: Check stream IDs against actual table LOG2SIZE
hw/arm/smmuv3: Align stream table base address to table size
hw/arm/smmuv3: Use correct bit positions in EVT_SET_ADDR2 macro
hw/arm/smmuv3: Report F_STE_FETCH fault address in correct word position
hw/arm/smmuv3-internal.h | 6 ++---
target/arm/cpu.h | 5 ++++
hw/arm/aspeed_ast2600.c | 3 +++
hw/arm/smmuv3.c | 28 +++++++++++++++-----
target/arm/arm-powerctl.c | 3 +++
target/arm/cpu.c | 65 +++++++++++++++++++++++++++++++++++++++++------
target/arm/helper.c | 42 +++++++++++++++++++++++-------
7 files changed, 125 insertions(+), 27 deletions(-)
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PULL 00/12] target-arm queue
2019-12-20 14:26 Peter Maydell
@ 2020-01-06 10:32 ` Peter Maydell
0 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2020-01-06 10:32 UTC (permalink / raw)
To: QEMU Developers
On Fri, 20 Dec 2019 at 14:26, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> One last arm pullreq before I stop work for the end of the year...
>
> -- PMM
>
> The following changes since commit 8e5943260a8f765216674ee87ce8588cc4e7463e:
>
> Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-12-20 12:46:10 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191220
>
> for you to fetch changes up to c8fa6079eb35888587f1be27c1590da4edcc5098:
>
> arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() (2019-12-20 14:03:00 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Support emulating the generic timers at frequencies other than 62.5MHz
> * Various fixes for SMMUv3 emulation bugs
> * Improve assert error message for hflags mismatches
> * arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on()
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL 00/12] target-arm queue
@ 2020-04-14 16:26 Peter Maydell
2020-04-14 19:09 ` Peter Maydell
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2020-04-14 16:26 UTC (permalink / raw)
To: qemu-devel
Almost nothing in here is arm-related, but the target-arm
queue was convenient for these last minute bits and pieces
for 5.0...
thanks
-- PMM
The following changes since commit 14e5526b51910efd62cd31cd95b49baca975c83f:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-04-13 15:42:51 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200414
for you to fetch changes up to 84f82ddcbb4ac4ed04c8675e85155329f23184f0:
Deprecate KVM support for AArch32 (2020-04-14 17:20:22 +0100)
----------------------------------------------------------------
patch queue:
* Fix some problems that trip up Coverity's scanner
* run-coverity-scan: New script automating the scan-and-upload process
* docs: Improve our gdbstub documentation
* configure: Honour --disable-werror for Sphinx
* docs: Fix errors produced when building with Sphinx 3.0
* docs: Require Sphinx 1.6 or better
* Add deprecation notice for KVM support on AArch32 hosts
----------------------------------------------------------------
Peter Maydell (12):
osdep.h: Drop no-longer-needed Coverity workarounds
thread.h: Fix Coverity version of qemu_cond_timedwait()
thread.h: Remove trailing semicolons from Coverity qemu_mutex_lock() etc
linux-user/flatload.c: Use "" for include of QEMU header target_flat.h
scripts/run-coverity-scan: Script to run Coverity Scan build
scripts/coverity-scan: Add Docker support
docs: Improve our gdbstub documentation
configure: Honour --disable-werror for Sphinx
scripts/kernel-doc: Add missing close-paren in c:function directives
kernel-doc: Use c:struct for Sphinx 3.0 and later
docs: Require Sphinx 1.6 or better
Deprecate KVM support for AArch32
configure | 9 +-
Makefile | 2 +-
include/qemu/osdep.h | 14 -
include/qemu/thread.h | 12 +-
linux-user/flatload.c | 2 +-
MAINTAINERS | 5 +
docs/conf.py | 6 +-
docs/sphinx/kerneldoc.py | 1 +
docs/system/deprecated.rst | 8 +
docs/system/gdb.rst | 22 +-
qemu-options.hx | 24 +-
scripts/coverity-scan/coverity-scan.docker | 131 ++++++++++
scripts/coverity-scan/run-coverity-scan | 401 +++++++++++++++++++++++++++++
scripts/kernel-doc | 18 +-
14 files changed, 615 insertions(+), 40 deletions(-)
create mode 100644 scripts/coverity-scan/coverity-scan.docker
create mode 100755 scripts/coverity-scan/run-coverity-scan
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PULL 00/12] target-arm queue
2020-04-14 16:26 Peter Maydell
@ 2020-04-14 19:09 ` Peter Maydell
0 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2020-04-14 19:09 UTC (permalink / raw)
To: QEMU Developers
On Tue, 14 Apr 2020 at 17:26, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Almost nothing in here is arm-related, but the target-arm
> queue was convenient for these last minute bits and pieces
> for 5.0...
>
> thanks
> -- PMM
>
> The following changes since commit 14e5526b51910efd62cd31cd95b49baca975c83f:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-04-13 15:42:51 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200414
>
> for you to fetch changes up to 84f82ddcbb4ac4ed04c8675e85155329f23184f0:
>
> Deprecate KVM support for AArch32 (2020-04-14 17:20:22 +0100)
>
> ----------------------------------------------------------------
> patch queue:
> * Fix some problems that trip up Coverity's scanner
> * run-coverity-scan: New script automating the scan-and-upload process
> * docs: Improve our gdbstub documentation
> * configure: Honour --disable-werror for Sphinx
> * docs: Fix errors produced when building with Sphinx 3.0
> * docs: Require Sphinx 1.6 or better
> * Add deprecation notice for KVM support on AArch32 hosts
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL 00/12] target-arm queue
@ 2020-07-20 12:56 Peter Maydell
2020-07-20 21:24 ` Peter Maydell
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2020-07-20 12:56 UTC (permalink / raw)
To: qemu-devel
Not much here, mostly documentation, but a few bug fixes.
thanks
-- PMM
The following changes since commit 873ec69aeb12e24eec7fb317fd0cd8494e8489dd:
Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging (2020-07-20 11:03:09 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200720
for you to fetch changes up to 6a0b7505f1fd6769c3f1558fda76464d51e4118a:
docs/system: Document the arm virt board (2020-07-20 11:35:17 +0100)
----------------------------------------------------------------
target-arm queue:
* virt: Don't enable MTE emulation by default
* virt: Diagnose attempts to use MTE with memory-hotplug or KVM
(rather than silently not working correctly)
* util: Implement qemu_get_thread_id() for OpenBSD
* qdev: Add doc comments for qdev_unrealize and GPIO functions,
and standardize on doc-comments-in-header-file
* hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
* docs/system: Document canon-a1100, collie, gumstix, virt boards
----------------------------------------------------------------
David CARLIER (1):
util: Implement qemu_get_thread_id() for OpenBSD
Peter Maydell (8):
qdev: Move doc comments from qdev.c to qdev-core.h
qdev: Document qdev_unrealize()
qdev: Document GPIO related functions
hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
docs/system: Briefly document canon-a1100 board
docs/system: Briefly document collie board
docs/system: Briefly document gumstix boards
docs/system: Document the arm virt board
Richard Henderson (3):
hw/arm/virt: Enable MTE via a machine property
hw/arm/virt: Error for MTE enabled with KVM
hw/arm/virt: Disable memory hotplug when MTE is enabled
docs/system/arm/collie.rst | 16 +++
docs/system/arm/digic.rst | 11 ++
docs/system/arm/gumstix.rst | 21 ++++
docs/system/arm/virt.rst | 161 ++++++++++++++++++++++++++
docs/system/target-arm.rst | 4 +
include/hw/arm/virt.h | 1 +
include/hw/qdev-core.h | 267 ++++++++++++++++++++++++++++++++++++++++++-
include/hw/qdev-properties.h | 13 +++
hw/arm/armsse.c | 2 +
hw/arm/virt.c | 50 +++++++-
hw/core/qdev.c | 33 ------
target/arm/cpu.c | 19 +--
target/arm/cpu64.c | 5 +-
util/oslib-posix.c | 2 +
MAINTAINERS | 4 +
15 files changed, 559 insertions(+), 50 deletions(-)
create mode 100644 docs/system/arm/collie.rst
create mode 100644 docs/system/arm/digic.rst
create mode 100644 docs/system/arm/gumstix.rst
create mode 100644 docs/system/arm/virt.rst
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PULL 00/12] target-arm queue
2020-07-20 12:56 Peter Maydell
@ 2020-07-20 21:24 ` Peter Maydell
0 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2020-07-20 21:24 UTC (permalink / raw)
To: QEMU Developers
On Mon, 20 Jul 2020 at 13:56, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Not much here, mostly documentation, but a few bug fixes.
>
> thanks
> -- PMM
>
> The following changes since commit 873ec69aeb12e24eec7fb317fd0cd8494e8489dd:
>
> Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging (2020-07-20 11:03:09 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200720
>
> for you to fetch changes up to 6a0b7505f1fd6769c3f1558fda76464d51e4118a:
>
> docs/system: Document the arm virt board (2020-07-20 11:35:17 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * virt: Don't enable MTE emulation by default
> * virt: Diagnose attempts to use MTE with memory-hotplug or KVM
> (rather than silently not working correctly)
> * util: Implement qemu_get_thread_id() for OpenBSD
> * qdev: Add doc comments for qdev_unrealize and GPIO functions,
> and standardize on doc-comments-in-header-file
> * hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
> * docs/system: Document canon-a1100, collie, gumstix, virt boards
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL 00/12] target-arm queue
@ 2020-10-08 14:25 Peter Maydell
0 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2020-10-08 14:25 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201008
for you to fetch changes up to ba118c26e16a97e6ff6de8184057d3420ce16a23:
target/arm: Make '-cpu max' have a 48-bit PA (2020-10-08 15:24:32 +0100)
----------------------------------------------------------------
target-arm queue:
* hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
* hw/arm/fsl-imx25: Fix a typo
* hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
* hw/arm/sbsa-ref : allocate IRQs for SMMUv3
* hw/char/bcm2835_aux: Allow less than 32-bit accesses
* hw/arm/virt: Implement kvm-steal-time
* target/arm: Make '-cpu max' have a 48-bit PA
----------------------------------------------------------------
Andrew Jones (6):
linux headers: sync to 5.9-rc7
target/arm/kvm: Make uncalled stubs explicitly unreachable
hw/arm/virt: Move post cpu realize check into its own function
hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
tests/qtest: Restore aarch64 arm-cpu-features test
hw/arm/virt: Implement kvm-steal-time
Graeme Gregory (2):
hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
hw/arm/sbsa-ref : allocate IRQs for SMMUv3
Peter Maydell (1):
target/arm: Make '-cpu max' have a 48-bit PA
Philippe Mathieu-Daudé (3):
hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
hw/arm/fsl-imx25: Fix a typo
hw/char/bcm2835_aux: Allow less than 32-bit accesses
docs/system/arm/cpu-features.rst | 11 ++++
include/hw/arm/fsl-imx25.h | 2 +-
include/hw/arm/virt.h | 5 ++
linux-headers/linux/kvm.h | 6 ++-
target/arm/cpu.h | 4 ++
target/arm/kvm_arm.h | 94 ++++++++++++++++++++++++++-------
hw/arm/sbsa-ref.c | 3 +-
hw/arm/virt.c | 110 ++++++++++++++++++++++++++++-----------
hw/char/bcm2835_aux.c | 4 +-
hw/ssi/npcm7xx_fiu.c | 12 ++---
target/arm/cpu.c | 8 +++
target/arm/cpu64.c | 4 ++
target/arm/kvm.c | 16 ++++++
target/arm/kvm64.c | 64 +++++++++++++++++++++--
target/arm/monitor.c | 2 +-
tests/qtest/arm-cpu-features.c | 25 +++++++--
hw/ssi/trace-events | 2 +-
tests/qtest/meson.build | 3 +-
18 files changed, 303 insertions(+), 72 deletions(-)
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL 00/12] target-arm queue
@ 2021-07-18 12:46 Peter Maydell
2021-07-18 16:35 ` Peter Maydell
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2021-07-18 12:46 UTC (permalink / raw)
To: qemu-devel
Last few changes before rc0: a few bug fixes, but mostly
docs stuff.
-- PMM
The following changes since commit a97fca4ceb9d9b10aa8b582e817a5ee6c42ffbaf:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream3' into staging (2021-07-16 16:34:42 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210718
for you to fetch changes up to 8fe612a183dec4c63afdc57537079bc742d024ca:
target/arm: Remove duplicate 'plus1' function from Neon and SVE decode (2021-07-18 10:59:47 +0100)
----------------------------------------------------------------
target-arm queue:
* Remove duplicate 'plus1' function from Neon and SVE decode
* Fix offsets for TTBCR for big-endian hosts
* docs: fix copyright date
* docs: add license/version info to HTML footers
* docs: add an About section
* docs: document some more arm boards
----------------------------------------------------------------
Peter Maydell (11):
docs: Fix documentation Copyright date
docs: Stop calling the top level subsections of our manual 'manuals'
docs: Remove "Contents:" lines from top-level subsections
docs: Move deprecation, build and license info out of system/
docs: Add some actual About text to about/index.rst
docs: Add license note to the HTML page footer
docs: Add QEMU version information to HTML footer
docs: Add skeletal documentation of cubieboard
docs: Add skeletal documentation of the emcraft-sf2
docs: Add skeletal documentation of highbank and midway
target/arm: Remove duplicate 'plus1' function from Neon and SVE decode
Richard Henderson (1):
target/arm: Fix offsets for TTBCR
docs/_templates/footer.html | 14 ++++++++++++++
docs/{system => about}/build-platforms.rst | 0
docs/{system => about}/deprecated.rst | 0
docs/about/index.rst | 27 +++++++++++++++++++++++++++
docs/{system => about}/license.rst | 0
docs/{system => about}/removed-features.rst | 0
docs/conf.py | 2 +-
docs/devel/index.rst | 7 +------
docs/index.rst | 1 +
docs/interop/index.rst | 9 ++-------
docs/meson.build | 3 ++-
docs/specs/index.rst | 7 ++-----
docs/system/arm/cubieboard.rst | 16 ++++++++++++++++
docs/system/arm/emcraft-sf2.rst | 15 +++++++++++++++
docs/system/arm/highbank.rst | 19 +++++++++++++++++++
docs/system/index.rst | 11 +----------
docs/system/target-arm.rst | 3 +++
docs/tools/index.rst | 7 ++-----
docs/user/index.rst | 7 +------
target/arm/neon-ls.decode | 4 ++--
target/arm/neon-shared.decode | 2 +-
target/arm/sve.decode | 2 +-
target/arm/helper.c | 11 +++++++----
target/arm/translate-neon.c | 5 -----
target/arm/translate-sve.c | 5 -----
MAINTAINERS | 4 ++++
26 files changed, 122 insertions(+), 59 deletions(-)
create mode 100644 docs/_templates/footer.html
rename docs/{system => about}/build-platforms.rst (100%)
rename docs/{system => about}/deprecated.rst (100%)
create mode 100644 docs/about/index.rst
rename docs/{system => about}/license.rst (100%)
rename docs/{system => about}/removed-features.rst (100%)
create mode 100644 docs/system/arm/cubieboard.rst
create mode 100644 docs/system/arm/emcraft-sf2.rst
create mode 100644 docs/system/arm/highbank.rst
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PULL 00/12] target-arm queue
2021-07-18 12:46 Peter Maydell
@ 2021-07-18 16:35 ` Peter Maydell
0 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2021-07-18 16:35 UTC (permalink / raw)
To: QEMU Developers
On Sun, 18 Jul 2021 at 13:46, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Last few changes before rc0: a few bug fixes, but mostly
> docs stuff.
>
> -- PMM
>
> The following changes since commit a97fca4ceb9d9b10aa8b582e817a5ee6c42ffbaf:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream3' into staging (2021-07-16 16:34:42 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210718
>
> for you to fetch changes up to 8fe612a183dec4c63afdc57537079bc742d024ca:
>
> target/arm: Remove duplicate 'plus1' function from Neon and SVE decode (2021-07-18 10:59:47 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Remove duplicate 'plus1' function from Neon and SVE decode
> * Fix offsets for TTBCR for big-endian hosts
> * docs: fix copyright date
> * docs: add license/version info to HTML footers
> * docs: add an About section
> * docs: document some more arm boards
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL 00/12] target-arm queue
@ 2023-05-12 15:34 Peter Maydell
2023-05-13 8:36 ` Richard Henderson
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2023-05-12 15:34 UTC (permalink / raw)
To: qemu-devel
Hi; here's a relatively small target-arm queue, pretty much all
bug fixes. (There are a few non-arm patches that I've thrown in
there too for my convenience :-))
thanks
-- PMM
The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1:
Merge tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu into staging (2023-05-11 11:44:23 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230512
for you to fetch changes up to 478dccbb99db0bf8f00537dd0b4d0de88d5cb537:
target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check (2023-05-12 16:01:25 +0100)
----------------------------------------------------------------
target-arm queue:
* More refactoring of files into tcg/
* Don't allow stage 2 page table walks to downgrade to NS
* Fix handling of SW and NSW bits for stage 2 walks
* MAINTAINERS: Update Akihiko Odaki's email address
* ui: Fix pixel colour channel order for PNG screenshots
* docs: Remove unused weirdly-named cross-reference targets
* hw/mips/malta: Fix minor dead code issue
* Fixes for the "allow CONFIG_TCG=n" changes
* tests/qtest: Don't run cdrom boot tests if no accelerator is present
* target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check
----------------------------------------------------------------
Akihiko Odaki (1):
MAINTAINERS: Update Akihiko Odaki's email address
Fabiano Rosas (3):
target/arm: Select SEMIHOSTING when using TCG
target/arm: Select CONFIG_ARM_V7M when TCG is enabled
tests/qtest: Don't run cdrom boot tests if no accelerator is present
Peter Maydell (6):
target/arm: Don't allow stage 2 page table walks to downgrade to NS
target/arm: Fix handling of SW and NSW bits for stage 2 walks
ui: Fix pixel colour channel order for PNG screenshots
docs: Remove unused weirdly-named cross-reference targets
hw/mips/malta: Fix minor dead code issue
target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check
Richard Henderson (2):
target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/
target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/
MAINTAINERS | 4 +-
docs/system/devices/igb.rst | 2 +-
docs/system/devices/ivshmem.rst | 2 -
docs/system/devices/net.rst | 2 +-
docs/system/devices/usb.rst | 2 -
docs/system/keys.rst | 2 +-
docs/system/linuxboot.rst | 2 +-
docs/system/target-i386.rst | 4 --
target/arm/helper.h | 8 +--
target/arm/internals.h | 12 +++-
target/arm/{ => tcg}/arm_ldst.h | 0
target/arm/{ => tcg}/helper-a64.h | 0
target/arm/{ => tcg}/helper-mve.h | 0
target/arm/{ => tcg}/helper-sme.h | 0
target/arm/{ => tcg}/helper-sve.h | 0
target/arm/{ => tcg}/sve_ldst_internal.h | 0
target/arm/{ => tcg}/translate-a32.h | 0
hw/mips/malta.c | 5 +-
target/arm/gdbstub64.c | 2 +-
target/arm/helper.c | 15 ++++-
target/arm/ptw.c | 95 +++++++++++++++++++-------------
target/arm/tcg/pauth_helper.c | 6 +-
tests/qtest/cdrom-test.c | 10 ++++
ui/console.c | 4 +-
target/arm/Kconfig | 9 +--
25 files changed, 109 insertions(+), 77 deletions(-)
rename target/arm/{ => tcg}/arm_ldst.h (100%)
rename target/arm/{ => tcg}/helper-a64.h (100%)
rename target/arm/{ => tcg}/helper-mve.h (100%)
rename target/arm/{ => tcg}/helper-sme.h (100%)
rename target/arm/{ => tcg}/helper-sve.h (100%)
rename target/arm/{ => tcg}/sve_ldst_internal.h (100%)
rename target/arm/{ => tcg}/translate-a32.h (100%)
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PULL 00/12] target-arm queue
2023-05-12 15:34 Peter Maydell
@ 2023-05-13 8:36 ` Richard Henderson
0 siblings, 0 replies; 27+ messages in thread
From: Richard Henderson @ 2023-05-13 8:36 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 5/12/23 16:34, Peter Maydell wrote:
> Hi; here's a relatively small target-arm queue, pretty much all
> bug fixes. (There are a few non-arm patches that I've thrown in
> there too for my convenience :-))
>
> thanks
> -- PMM
>
> The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1:
>
> Merge tag 'pull-tcg-20230511-2' ofhttps://gitlab.com/rth7680/qemu into staging (2023-05-11 11:44:23 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230512
>
> for you to fetch changes up to 478dccbb99db0bf8f00537dd0b4d0de88d5cb537:
>
> target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check (2023-05-12 16:01:25 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * More refactoring of files into tcg/
> * Don't allow stage 2 page table walks to downgrade to NS
> * Fix handling of SW and NSW bits for stage 2 walks
> * MAINTAINERS: Update Akihiko Odaki's email address
> * ui: Fix pixel colour channel order for PNG screenshots
> * docs: Remove unused weirdly-named cross-reference targets
> * hw/mips/malta: Fix minor dead code issue
> * Fixes for the "allow CONFIG_TCG=n" changes
> * tests/qtest: Don't run cdrom boot tests if no accelerator is present
> * target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.
r~
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL 00/12] target-arm queue
@ 2023-11-06 15:32 Peter Maydell
2023-11-07 3:02 ` Stefan Hajnoczi
0 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2023-11-06 15:32 UTC (permalink / raw)
To: qemu-devel
Hi; here's another arm pullreq. These changes are all bug fixes
(including some Coverity issue fixes), so are OK for applying
either before or after softfreeze.
thanks
-- PMM
The following changes since commit 3e01f1147a16ca566694b97eafc941d62fa1e8d8:
Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging (2023-11-06 09:34:22 +0800)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231106
for you to fetch changes up to 5722fc471296d5f042df4b005a851cc8008df0c9:
target/arm: Fix A64 LDRA immediate decode (2023-11-06 15:00:29 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/arm/virt: fix PMU IRQ registration
* hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables
* hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow
* util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow
* mc146818rtc: rtc_set_time(): initialize tm to zeroes
* block/nvme: nvme_process_completion() fix bound for cid
* hw/core/loader: gunzip(): initialize z_stream
* io/channel-socket: qio_channel_socket_flush(): improve msg validation
* hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0
* target/arm: Fix A64 LDRA immediate decode
----------------------------------------------------------------
Peter Maydell (4):
tests/qtest/bios-tables-test: Allow changes to virt SPCR and DBG2
tests/qtest/bios-tables-test: Update virt SPCR and DBG2 golden references
hw/arm/vexpress-a9: Remove useless mapping of RAM at address 0
target/arm: Fix A64 LDRA immediate decode
Sebastian Ott (1):
hw/arm/virt: fix PMU IRQ registration
Udo Steinberg (1):
hw/arm/virt: Report correct register sizes in ACPI DBG2/SPCR tables.
Vladimir Sementsov-Ogievskiy (6):
hw/i386/intel_iommu: vtd_slpte_nonzero_rsvd(): assert no overflow
util/filemonitor-inotify: qemu_file_monitor_watch(): assert no overflow
mc146818rtc: rtc_set_time(): initialize tm to zeroes
block/nvme: nvme_process_completion() fix bound for cid
hw/core/loader: gunzip(): initialize z_stream
io/channel-socket: qio_channel_socket_flush(): improve msg validation
docs/system/arm/vexpress.rst | 3 +++
target/arm/tcg/translate.h | 5 +++++
target/arm/tcg/a64.decode | 2 +-
block/nvme.c | 7 ++++---
hw/arm/vexpress.c | 14 +++-----------
hw/arm/virt-acpi-build.c | 4 ++--
hw/arm/virt.c | 3 ++-
hw/core/loader.c | 2 +-
hw/i386/intel_iommu.c | 23 ++++++++++++++++++++---
hw/rtc/mc146818rtc.c | 2 +-
io/channel-socket.c | 5 +++++
util/filemonitor-inotify.c | 25 +++++++++++++++++--------
tests/data/acpi/virt/DBG2 | Bin 87 -> 87 bytes
tests/data/acpi/virt/SPCR | Bin 80 -> 80 bytes
14 files changed, 64 insertions(+), 31 deletions(-)
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PULL 00/12] target-arm queue
2023-11-06 15:32 Peter Maydell
@ 2023-11-07 3:02 ` Stefan Hajnoczi
0 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2023-11-07 3:02 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 115 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL 00/12] target-arm queue
@ 2025-02-10 15:49 Peter Maydell
2025-02-10 15:49 ` [PULL 01/12] target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation Peter Maydell
` (12 more replies)
0 siblings, 13 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 131c58469f6fb68c89b38fee6aba8bbb20c7f4bf:
rust: add --rust-target option for bindgen (2025-02-06 13:51:46 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250210
for you to fetch changes up to 27a8d899c7a100fd5aa040a8b993bb257687c393:
linux-user: Do not define struct sched_attr if libc headers do (2025-02-07 16:09:20 +0000)
----------------------------------------------------------------
target-arm queue:
* Deprecate pxa2xx CPUs, iwMMXt emulation, -old-param option
* Drop unused AArch64DecodeTable typedefs
* Minor code cleanups
* hw/net/cadence_gem: Fix the mask/compare/disable-mask logic
* linux-user: Do not define struct sched_attr if libc headers do
----------------------------------------------------------------
Andrew Yuan (1):
hw/net/cadence_gem: Fix the mask/compare/disable-mask logic
Khem Raj (1):
linux-user: Do not define struct sched_attr if libc headers do
Peter Maydell (4):
target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation
tests/tcg/arm: Remove test-arm-iwmmxt test
target/arm: Drop unused AArch64DecodeTable typedefs
qemu-options: Deprecate -old-param command line option
Philippe Mathieu-Daudé (6):
hw/arm/boot: Propagate vCPU to arm_load_dtb()
hw/arm/fsl-imx6: Add local 'mpcore/gic' variables
hw/arm/fsl-imx6ul: Add local 'mpcore/gic' variables
hw/arm/fsl-imx7: Add local 'mpcore/gic' variables
hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE
hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro
docs/about/deprecated.rst | 34 ++++++++++++++++++++++
include/hw/arm/boot.h | 4 ++-
target/arm/cpu.h | 1 +
hw/arm/boot.c | 11 +++----
hw/arm/fsl-imx6.c | 52 ++++++++++++++-------------------
hw/arm/fsl-imx6ul.c | 64 +++++++++++++++++------------------------
hw/arm/fsl-imx7.c | 52 +++++++++++++++------------------
hw/arm/virt.c | 2 +-
hw/cpu/a15mpcore.c | 21 ++++++--------
hw/cpu/a9mpcore.c | 21 ++++++--------
hw/cpu/arm11mpcore.c | 21 ++++++--------
hw/cpu/realview_mpcore.c | 29 +++++++------------
hw/net/cadence_gem.c | 26 +++++++++++++----
linux-user/syscall.c | 4 ++-
system/vl.c | 1 +
target/arm/cpu.c | 3 ++
target/arm/tcg/cpu32.c | 36 +++++++++++++++--------
target/arm/tcg/translate-a64.c | 11 -------
tests/tcg/arm/Makefile.target | 7 -----
tests/tcg/arm/README | 5 ----
tests/tcg/arm/test-arm-iwmmxt.S | 49 -------------------------------
21 files changed, 205 insertions(+), 249 deletions(-)
delete mode 100644 tests/tcg/arm/test-arm-iwmmxt.S
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PULL 01/12] target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 02/12] tests/tcg/arm: Remove test-arm-iwmmxt test Peter Maydell
` (11 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
The pxa2xx CPUs are now only useful with user-mode emulation, because
we dropped all the machine types that used them in 9.2. (Technically
you could alse use "-cpu pxa270" with a board model like versatilepb
which doesn't sanity-check the CPU type, but that has never been a
supported config.)
To use them (or iwMMXt emulation) with QEMU user-mode you would need
to explicitly select them with the -cpu option or the QEMU_CPU
environment variable. A google search finds no examples of anybody
doing this in the last decade; I don't believe the GCC folks are
using QEMU to test their iwMMXt codegen either. In fact, GCC is in
the process of dropping support for iwMMXT entirely.
The iwMMXt emulation is thousands of lines of code in QEMU, and
is now the only bit of Arm insn decode which doesn't use decodetree.
We have no way to test or validate changes to it. This code is
just dead weight that is almost certainly not being used by anybody.
Mark it as deprecated.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250127112715.2936555-2-peter.maydell@linaro.org
---
docs/about/deprecated.rst | 21 +++++++++++++++++++++
target/arm/cpu.h | 1 +
target/arm/cpu.c | 3 +++
target/arm/tcg/cpu32.c | 36 ++++++++++++++++++++++++------------
4 files changed, 49 insertions(+), 12 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 4a3c302962a..29de49351d1 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -204,6 +204,27 @@ is going to be so much slower it wouldn't make sense for any serious
instrumentation. Due to implementation differences there will also be
anomalies in things like memory instrumentation.
+linux-user mode CPUs
+--------------------
+
+iwMMXt emulation and the ``pxa`` CPUs (since 10.0)
+''''''''''''''''''''''''''''''''''''''''''''''''''
+
+The ``pxa`` CPU family (``pxa250``, ``pxa255``, ``pxa260``,
+``pxa261``, ``pxa262``, ``pxa270-a0``, ``pxa270-a1``, ``pxa270``,
+``pxa270-b0``, ``pxa270-b1``, ``pxa270-c0``, ``pxa270-c5``) are no
+longer used in system emulation, because all the machine types which
+used these CPUs were removed in the QEMU 9.2 release. These CPUs can
+now only be used in linux-user mode, and to do that you would have to
+explicitly select one of these CPUs with the ``-cpu`` command line
+option or the ``QEMU_CPU`` environment variable.
+
+We don't believe that anybody is using the iwMMXt emulation, and we do
+not have any tests to validate it or any real hardware or similar
+known-good implementation to test against. GCC is in the process of
+dropping their support for iwMMXt codegen. These CPU types are
+therefore deprecated in QEMU, and will be removed in a future release.
+
System emulator CPUs
--------------------
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2213c277348..c2d2d99b462 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1118,6 +1118,7 @@ struct ArchCPU {
typedef struct ARMCPUInfo {
const char *name;
+ const char *deprecation_note;
void (*initfn)(Object *obj);
void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7a83b9ee34f..32dc7c1e692 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2758,6 +2758,9 @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
acc->info = data;
cc->gdb_core_xml_file = "arm-core.xml";
+ if (acc->info->deprecation_note) {
+ cc->deprecation_note = acc->info->deprecation_note;
+ }
}
void arm_cpu_register(const ARMCPUInfo *info)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 2ad21825255..0f1c5bc87e8 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -1026,19 +1026,31 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
{ .name = "ti925t", .initfn = ti925t_initfn },
{ .name = "sa1100", .initfn = sa1100_initfn },
{ .name = "sa1110", .initfn = sa1110_initfn },
- { .name = "pxa250", .initfn = pxa250_initfn },
- { .name = "pxa255", .initfn = pxa255_initfn },
- { .name = "pxa260", .initfn = pxa260_initfn },
- { .name = "pxa261", .initfn = pxa261_initfn },
- { .name = "pxa262", .initfn = pxa262_initfn },
+ { .name = "pxa250", .initfn = pxa250_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
+ { .name = "pxa255", .initfn = pxa255_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
+ { .name = "pxa260", .initfn = pxa260_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
+ { .name = "pxa261", .initfn = pxa261_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
+ { .name = "pxa262", .initfn = pxa262_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
/* "pxa270" is an alias for "pxa270-a0" */
- { .name = "pxa270", .initfn = pxa270a0_initfn },
- { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
- { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
- { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
- { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
- { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
- { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
+ { .name = "pxa270", .initfn = pxa270a0_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
+ { .name = "pxa270-a0", .initfn = pxa270a0_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
+ { .name = "pxa270-a1", .initfn = pxa270a1_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
+ { .name = "pxa270-b0", .initfn = pxa270b0_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
+ { .name = "pxa270-b1", .initfn = pxa270b1_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
+ { .name = "pxa270-c0", .initfn = pxa270c0_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
+ { .name = "pxa270-c5", .initfn = pxa270c5_initfn,
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
#ifndef TARGET_AARCH64
{ .name = "max", .initfn = arm_max_initfn },
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 02/12] tests/tcg/arm: Remove test-arm-iwmmxt test
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
2025-02-10 15:49 ` [PULL 01/12] target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 03/12] target/arm: Drop unused AArch64DecodeTable typedefs Peter Maydell
` (10 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
The test-arm-iwmmmxt test isn't testing what it thinks it's testing.
If you run it with a CPU type that supports iwMMXt then it will crash
immediately with a SIGILL, because (even with -marm) GCC will link it
against startup code that is in Thumb mode, and no iwMMXt CPU has
Thumb:
00010338 <_start>:
10338: f04f 0b00 mov.w fp, #0
1033c: f04f 0e00 mov.w lr, #0
If you run it with a CPU type which does *not* support iwMMXt, which
is what 'make check-tcg' does, then QEMU will not try to handle the
insns as iwMMXt. Instead the translator turns them into illegal
instructions. Then in the linux-user cpu_loop() code we identify
them as FPA11 instructions inside emulate_arm_fpa11(), because the
FPA11 happened to use the same coprocessor number as these iwMMXt
insns. So we execute a completely different set of FPA11 insns,
which means we don't crash, but we will print garbage to stdout.
Then the test binary always exits with a 0 return code, so 'make
check-tcg' thinks the test passes.
Modern gnueabihf toolchains assume in their startup code that the CPU
is not so old as to not support Thumb, so there's no way to get them
to generate a binary that actually does what the test wants. Since
we're deprecating iwMMXt emulation anyway, it's not worth trying to
salvage the test case to get it to really test the iwMMXt insns.
Delete the test entirely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250127112715.2936555-3-peter.maydell@linaro.org
---
tests/tcg/arm/Makefile.target | 7 -----
tests/tcg/arm/README | 5 ----
tests/tcg/arm/test-arm-iwmmxt.S | 49 ---------------------------------
3 files changed, 61 deletions(-)
delete mode 100644 tests/tcg/arm/test-arm-iwmmxt.S
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
index 06ddf3e04fc..99a953b6671 100644
--- a/tests/tcg/arm/Makefile.target
+++ b/tests/tcg/arm/Makefile.target
@@ -20,13 +20,6 @@ ARM_TESTS = hello-arm
hello-arm: CFLAGS+=-marm -ffreestanding -fno-stack-protector
hello-arm: LDFLAGS+=-nostdlib
-# IWMXT floating point extensions
-ARM_TESTS += test-arm-iwmmxt
-# Clang assembler does not support IWMXT, so use the external assembler.
-test-arm-iwmmxt: CFLAGS += -marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16 $(CROSS_CC_HAS_FNIA)
-test-arm-iwmmxt: test-arm-iwmmxt.S
- $(CC) $(CFLAGS) -Wa,--noexecstack $< -o $@ $(LDFLAGS)
-
# Float-convert Tests
ARM_TESTS += fcvt
fcvt: LDFLAGS += -lm
diff --git a/tests/tcg/arm/README b/tests/tcg/arm/README
index e6307116e23..aceccc127f7 100644
--- a/tests/tcg/arm/README
+++ b/tests/tcg/arm/README
@@ -4,8 +4,3 @@ hello-arm
---------
A very simple inline assembly, write syscall based hello world
-
-test-arm-iwmmxt
----------------
-
-A simple test case for older iwmmxt extended ARMs
diff --git a/tests/tcg/arm/test-arm-iwmmxt.S b/tests/tcg/arm/test-arm-iwmmxt.S
deleted file mode 100644
index d647f9404ae..00000000000
--- a/tests/tcg/arm/test-arm-iwmmxt.S
+++ /dev/null
@@ -1,49 +0,0 @@
-@ Checks whether iwMMXt is functional.
-.code 32
-.globl main
-
-main:
-ldr r0, =data0
-ldr r1, =data1
-ldr r2, =data2
-#ifndef FPA
-wldrd wr0, [r0, #0]
-wldrd wr1, [r0, #8]
-wldrd wr2, [r1, #0]
-wldrd wr3, [r1, #8]
-wsubb wr2, wr2, wr0
-wsubb wr3, wr3, wr1
-wldrd wr0, [r2, #0]
-wldrd wr1, [r2, #8]
-waddb wr0, wr0, wr2
-waddb wr1, wr1, wr3
-wstrd wr0, [r2, #0]
-wstrd wr1, [r2, #8]
-#else
-ldfe f0, [r0, #0]
-ldfe f1, [r0, #8]
-ldfe f2, [r1, #0]
-ldfe f3, [r1, #8]
-adfdp f2, f2, f0
-adfdp f3, f3, f1
-ldfe f0, [r2, #0]
-ldfe f1, [r2, #8]
-adfd f0, f0, f2
-adfd f1, f1, f3
-stfe f0, [r2, #0]
-stfe f1, [r2, #8]
-#endif
-mov r0, #1
-mov r1, r2
-mov r2, #0x11
-swi #0x900004
-mov r0, #0
-swi #0x900001
-
-.data
-data0:
-.string "aaaabbbbccccdddd"
-data1:
-.string "bbbbccccddddeeee"
-data2:
-.string "hvLLWs\x1fsdrs9\x1fNJ-\n"
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 03/12] target/arm: Drop unused AArch64DecodeTable typedefs
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
2025-02-10 15:49 ` [PULL 01/12] target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation Peter Maydell
2025-02-10 15:49 ` [PULL 02/12] tests/tcg/arm: Remove test-arm-iwmmxt test Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 04/12] hw/arm/boot: Propagate vCPU to arm_load_dtb() Peter Maydell
` (9 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
We removed the old table-based decoder in favour of decodetree, but
we left a couple of typedefs that are now unused; delete them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250128135046.4108775-1-peter.maydell@linaro.org
---
target/arm/tcg/translate-a64.c | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 0b76a2cdb78..d6ac2ed418a 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -75,17 +75,6 @@ static int scale_by_log2_tag_granule(DisasContext *s, int x)
#include "decode-sme-fa64.c.inc"
#include "decode-a64.c.inc"
-/* Table based decoder typedefs - used when the relevant bits for decode
- * are too awkwardly scattered across the instruction (eg SIMD).
- */
-typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
-
-typedef struct AArch64DecodeTable {
- uint32_t pattern;
- uint32_t mask;
- AArch64DecodeFn *disas_fn;
-} AArch64DecodeTable;
-
/* initialize TCG globals. */
void a64_translate_init(void)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 04/12] hw/arm/boot: Propagate vCPU to arm_load_dtb()
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2025-02-10 15:49 ` [PULL 03/12] target/arm: Drop unused AArch64DecodeTable typedefs Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 05/12] hw/arm/fsl-imx6: Add local 'mpcore/gic' variables Peter Maydell
` (8 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
In heterogeneous setup the first vCPU might not be
the one expected, better pass it explicitly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20250130112615.3219-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/boot.h | 4 +++-
hw/arm/boot.c | 11 ++++++-----
hw/arm/virt.c | 2 +-
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
index 80c492d7421..b12bf61ca81 100644
--- a/include/hw/arm/boot.h
+++ b/include/hw/arm/boot.h
@@ -160,6 +160,7 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
* @binfo: struct describing the boot environment
* @addr_limit: upper limit of the available memory area at @addr
* @as: address space to load image to
+ * @cpu: ARM CPU object
*
* Load a device tree supplied by the machine or by the user with the
* '-dtb' command line option, and put it at offset @addr in target
@@ -176,7 +177,8 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
* Note: Must not be called unless have_dtb(binfo) is true.
*/
int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
- hwaddr addr_limit, AddressSpace *as, MachineState *ms);
+ hwaddr addr_limit, AddressSpace *as, MachineState *ms,
+ ARMCPU *cpu);
/* Write a secure board setup routine with a dummy handler for SMCs */
void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index cbc24356fc1..42c18355e85 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -432,13 +432,12 @@ out:
return ret;
}
-static void fdt_add_psci_node(void *fdt)
+static void fdt_add_psci_node(void *fdt, ARMCPU *armcpu)
{
uint32_t cpu_suspend_fn;
uint32_t cpu_off_fn;
uint32_t cpu_on_fn;
uint32_t migrate_fn;
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
const char *psci_method;
int64_t psci_conduit;
int rc;
@@ -512,7 +511,8 @@ static void fdt_add_psci_node(void *fdt)
}
int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
- hwaddr addr_limit, AddressSpace *as, MachineState *ms)
+ hwaddr addr_limit, AddressSpace *as, MachineState *ms,
+ ARMCPU *cpu)
{
void *fdt = NULL;
int size, rc, n = 0;
@@ -655,7 +655,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
}
}
- fdt_add_psci_node(fdt);
+ fdt_add_psci_node(fdt, cpu);
if (binfo->modify_dtb) {
binfo->modify_dtb(binfo, fdt);
@@ -1327,7 +1327,8 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
* decided whether to enable PSCI and set the psci-conduit CPU properties.
*/
if (!info->skip_dtb_autoload && have_dtb(info)) {
- if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
+ if (arm_load_dtb(info->dtb_start, info, info->dtb_limit,
+ as, ms, cpu) < 0) {
exit(1);
}
}
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 99e0a68b6c5..d23b14718af 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1746,7 +1746,7 @@ void virt_machine_done(Notifier *notifier, void *data)
vms->memmap[VIRT_PLATFORM_BUS].size,
vms->irqmap[VIRT_PLATFORM_BUS]);
}
- if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
+ if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) {
exit(1);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 05/12] hw/arm/fsl-imx6: Add local 'mpcore/gic' variables
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2025-02-10 15:49 ` [PULL 04/12] hw/arm/boot: Propagate vCPU to arm_load_dtb() Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 06/12] hw/arm/fsl-imx6ul: " Peter Maydell
` (7 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The A9MPCore forward the IRQs from its internal GIC.
To make the code clearer, add the 'mpcore' and 'gic'
variables.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250130112615.3219-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/fsl-imx6.c | 52 +++++++++++++++++++----------------------------
1 file changed, 21 insertions(+), 31 deletions(-)
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 88b9ccff493..dc86338b3a5 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -117,6 +117,8 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
uint16_t i;
qemu_irq irq;
unsigned int smp_cpus = ms->smp.cpus;
+ DeviceState *mpcore = DEVICE(&s->a9mpcore);
+ DeviceState *gic;
if (smp_cpus > FSL_IMX6_NUM_CPUS) {
error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
@@ -143,21 +145,21 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
}
}
- object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus,
- &error_abort);
+ object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort);
- object_property_set_int(OBJECT(&s->a9mpcore), "num-irq",
+ object_property_set_int(OBJECT(mpcore), "num-irq",
FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(mpcore), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
+ sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
+ gic = mpcore;
for (i = 0; i < smp_cpus; i++) {
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
+ sysbus_connect_irq(SYS_BUS_DEVICE(gic), i,
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
+ sysbus_connect_irq(SYS_BUS_DEVICE(gic), i + smp_cpus,
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
}
@@ -195,8 +197,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- serial_table[i].irq));
+ qdev_get_gpio_in(gic, serial_table[i].irq));
}
s->gpt.ccm = IMX_CCM(&s->ccm);
@@ -207,8 +208,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- FSL_IMX6_GPT_IRQ));
+ qdev_get_gpio_in(gic, FSL_IMX6_GPT_IRQ));
/* Initialize all EPIT timers */
for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
@@ -228,8 +228,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- epit_table[i].irq));
+ qdev_get_gpio_in(gic, epit_table[i].irq));
}
/* Initialize all I2C */
@@ -249,8 +248,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- i2c_table[i].irq));
+ qdev_get_gpio_in(gic, i2c_table[i].irq));
}
/* Initialize all GPIOs */
@@ -307,11 +305,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- gpio_table[i].irq_low));
+ qdev_get_gpio_in(gic, gpio_table[i].irq_low));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- gpio_table[i].irq_high));
+ qdev_get_gpio_in(gic, gpio_table[i].irq_high));
}
/* Initialize all SDHC */
@@ -338,8 +334,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- esdhc_table[i].irq));
+ qdev_get_gpio_in(gic, esdhc_table[i].irq));
}
/* USB */
@@ -360,8 +355,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- FSL_IMX6_USBn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6_USBn_IRQ[i]));
}
/* Initialize all ECSPI */
@@ -384,8 +378,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- spi_table[i].irq));
+ qdev_get_gpio_in(gic, spi_table[i].irq));
}
object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num,
@@ -396,11 +389,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- FSL_IMX6_ENET_MAC_IRQ));
+ qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- FSL_IMX6_ENET_MAC_1588_IRQ));
+ qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_1588_IRQ));
/*
* SNVS
@@ -427,8 +418,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
- FSL_IMX6_WDOGn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6_WDOGn_IRQ[i]));
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 06/12] hw/arm/fsl-imx6ul: Add local 'mpcore/gic' variables
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2025-02-10 15:49 ` [PULL 05/12] hw/arm/fsl-imx6: Add local 'mpcore/gic' variables Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 07/12] hw/arm/fsl-imx7: " Peter Maydell
` (6 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The A7MPCore forward the IRQs from its internal GIC.
To make the code clearer, add the 'mpcore' and 'gic'
variables. Rename 'd' variable as 'cpu'.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250130112615.3219-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/fsl-imx6ul.c | 64 +++++++++++++++++++--------------------------
1 file changed, 27 insertions(+), 37 deletions(-)
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index 79e4847953a..34c4aa15cd0 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -157,10 +157,12 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6ULState *s = FSL_IMX6UL(dev);
+ DeviceState *mpcore = DEVICE(&s->a7mpcore);
int i;
char name[NAME_SIZE];
- SysBusDevice *sbd;
- DeviceState *d;
+ DeviceState *gic;
+ SysBusDevice *gicsbd;
+ DeviceState *cpu;
if (ms->smp.cpus > 1) {
error_setg(errp, "%s: Only a single CPU is supported (%d requested)",
@@ -173,19 +175,19 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
/*
* A7MPCORE
*/
- object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", 1, &error_abort);
- object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
+ object_property_set_int(OBJECT(mpcore), "num-cpu", 1, &error_abort);
+ object_property_set_int(OBJECT(mpcore), "num-irq",
FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
+ sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
- sbd = SYS_BUS_DEVICE(&s->a7mpcore);
- d = DEVICE(&s->cpu);
-
- sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
- sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
- sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ));
- sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ));
+ gic = mpcore;
+ gicsbd = SYS_BUS_DEVICE(gic);
+ cpu = DEVICE(&s->cpu);
+ sysbus_connect_irq(gicsbd, 0, qdev_get_gpio_in(cpu, ARM_CPU_IRQ));
+ sysbus_connect_irq(gicsbd, 1, qdev_get_gpio_in(cpu, ARM_CPU_FIQ));
+ sysbus_connect_irq(gicsbd, 2, qdev_get_gpio_in(cpu, ARM_CPU_VIRQ));
+ sysbus_connect_irq(gicsbd, 3, qdev_get_gpio_in(cpu, ARM_CPU_VFIQ));
/*
* A7MPCORE DAP
@@ -244,8 +246,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_GPTn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_GPTn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_GPTn_IRQ[i]));
}
/*
@@ -269,8 +270,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_EPITn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_EPITn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_EPITn_IRQ[i]));
}
/*
@@ -307,12 +307,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_GPIOn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
}
/*
@@ -366,8 +364,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_SPIn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_SPIn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_SPIn_IRQ[i]));
}
/*
@@ -392,8 +389,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_I2Cn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_I2Cn_IRQ[i]));
}
/*
@@ -430,8 +426,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_UARTn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_UARTn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_UARTn_IRQ[i]));
}
/*
@@ -480,12 +475,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_ENETn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_ENETn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_ENETn_IRQ[i]));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
}
/*
@@ -521,8 +514,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX6UL_USB02_USBn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_USBn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_USBn_IRQ[i]));
}
/*
@@ -547,8 +539,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_USDHCn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_USDHCn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_USDHCn_IRQ[i]));
}
/*
@@ -580,8 +571,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
FSL_IMX6UL_WDOGn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX6UL_WDOGn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX6UL_WDOGn_IRQ[i]));
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 07/12] hw/arm/fsl-imx7: Add local 'mpcore/gic' variables
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2025-02-10 15:49 ` [PULL 06/12] hw/arm/fsl-imx6ul: " Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 08/12] hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE Peter Maydell
` (5 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The A7MPCore forward the IRQs from its internal GIC.
To make the code clearer, add the 'mpcore' and 'gic'
variables.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250130112615.3219-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/fsl-imx7.c | 52 +++++++++++++++++++++--------------------------
1 file changed, 23 insertions(+), 29 deletions(-)
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 004bf499376..3374018cde0 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -166,7 +166,8 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
FslIMX7State *s = FSL_IMX7(dev);
- Object *o;
+ DeviceState *mpcore = DEVICE(&s->a7mpcore);
+ DeviceState *gic;
int i;
qemu_irq irq;
char name[NAME_SIZE];
@@ -182,7 +183,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
* CPUs
*/
for (i = 0; i < smp_cpus; i++) {
- o = OBJECT(&s->cpu[i]);
+ Object *o = OBJECT(&s->cpu[i]);
/* On uniprocessor, the CBAR is set to 0 */
if (smp_cpus > 1) {
@@ -205,16 +206,15 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
/*
* A7MPCORE
*/
- object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", smp_cpus,
- &error_abort);
- object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
+ object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort);
+ object_property_set_int(OBJECT(mpcore), "num-irq",
FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
- sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
-
+ gic = mpcore;
for (i = 0; i < smp_cpus; i++) {
- SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(gic);
DeviceState *d = DEVICE(qemu_get_cpu(i));
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
@@ -255,8 +255,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX7_GPTn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX7_GPTn_IRQ[i]));
}
/*
@@ -298,12 +297,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_GPIOn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX7_GPIOn_LOW_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_LOW_IRQ[i]));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX7_GPIOn_HIGH_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_HIGH_IRQ[i]));
}
/*
@@ -355,8 +352,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
FSL_IMX7_SPIn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX7_SPIn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX7_SPIn_IRQ[i]));
}
/*
@@ -381,8 +377,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX7_I2Cn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX7_I2Cn_IRQ[i]));
}
/*
@@ -416,7 +411,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]);
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_UARTn_IRQ[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
}
@@ -454,9 +449,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0));
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3));
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 3));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
}
@@ -483,7 +478,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
FSL_IMX7_USDHCn_ADDR[i]);
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]);
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_USDHCn_IRQ[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
}
@@ -522,8 +517,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
- FSL_IMX7_WDOGn_IRQ[i]));
+ qdev_get_gpio_in(gic, FSL_IMX7_WDOGn_IRQ[i]));
}
/*
@@ -606,11 +600,11 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_MSI_IRQ);
qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq);
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTA_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTB_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTC_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
@@ -643,7 +637,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX7_USBn_ADDR[i]);
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]);
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_USBn_IRQ[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
snprintf(name, NAME_SIZE, "usbmisc%d", i);
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 08/12] hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2025-02-10 15:49 ` [PULL 07/12] hw/arm/fsl-imx7: " Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 09/12] hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro Peter Maydell
` (4 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
No need to duplicate and forward the 'num-cpu' property from
TYPE_ARM11MPCORE_PRIV to TYPE_REALVIEW_MPCORE, alias it with
QOM object_property_add_alias().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20250130112615.3219-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/cpu/realview_mpcore.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c
index 4268735e3a5..7480b38d1ab 100644
--- a/hw/cpu/realview_mpcore.c
+++ b/hw/cpu/realview_mpcore.c
@@ -14,7 +14,6 @@
#include "hw/cpu/arm11mpcore.h"
#include "hw/intc/realview_gic.h"
#include "hw/irq.h"
-#include "hw/qdev-properties.h"
#include "qom/object.h"
#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
@@ -68,7 +67,6 @@ static void realview_mpcore_realize(DeviceState *dev, Error **errp)
int n;
int i;
- qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->priv), errp)) {
return;
}
@@ -100,6 +98,7 @@ static void mpcore_rirq_init(Object *obj)
int i;
object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV);
+ object_property_add_alias(obj, "num-cpu", OBJECT(&s->priv), "num-cpu");
privbusdev = SYS_BUS_DEVICE(&s->priv);
sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
@@ -108,16 +107,11 @@ static void mpcore_rirq_init(Object *obj)
}
}
-static const Property mpcore_rirq_properties[] = {
- DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
-};
-
static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = realview_mpcore_realize;
- device_class_set_props(dc, mpcore_rirq_properties);
}
static const TypeInfo mpcore_rirq_info = {
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 09/12] hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2025-02-10 15:49 ` [PULL 08/12] hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 10/12] hw/net/cadence_gem: Fix the mask/compare/disable-mask logic Peter Maydell
` (3 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20250130112615.3219-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/cpu/a15mpcore.c | 21 +++++++++------------
hw/cpu/a9mpcore.c | 21 +++++++++------------
hw/cpu/arm11mpcore.c | 21 +++++++++------------
hw/cpu/realview_mpcore.c | 21 +++++++++------------
4 files changed, 36 insertions(+), 48 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 3b0897e54ee..d24ab0a6ab2 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -164,17 +164,14 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data)
/* We currently have no saveable state */
}
-static const TypeInfo a15mp_priv_info = {
- .name = TYPE_A15MPCORE_PRIV,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(A15MPPrivState),
- .instance_init = a15mp_priv_initfn,
- .class_init = a15mp_priv_class_init,
+static const TypeInfo a15mp_types[] = {
+ {
+ .name = TYPE_A15MPCORE_PRIV,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(A15MPPrivState),
+ .instance_init = a15mp_priv_initfn,
+ .class_init = a15mp_priv_class_init,
+ },
};
-static void a15mp_register_types(void)
-{
- type_register_static(&a15mp_priv_info);
-}
-
-type_init(a15mp_register_types)
+DEFINE_TYPES(a15mp_types)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 9671585b5f9..25416c5032b 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -177,17 +177,14 @@ static void a9mp_priv_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, a9mp_priv_properties);
}
-static const TypeInfo a9mp_priv_info = {
- .name = TYPE_A9MPCORE_PRIV,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(A9MPPrivState),
- .instance_init = a9mp_priv_initfn,
- .class_init = a9mp_priv_class_init,
+static const TypeInfo a9mp_types[] = {
+ {
+ .name = TYPE_A9MPCORE_PRIV,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(A9MPPrivState),
+ .instance_init = a9mp_priv_initfn,
+ .class_init = a9mp_priv_class_init,
+ },
};
-static void a9mp_register_types(void)
-{
- type_register_static(&a9mp_priv_info);
-}
-
-type_init(a9mp_register_types)
+DEFINE_TYPES(a9mp_types)
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 94861a06d94..b56bee6d543 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -152,17 +152,14 @@ static void mpcore_priv_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, mpcore_priv_properties);
}
-static const TypeInfo mpcore_priv_info = {
- .name = TYPE_ARM11MPCORE_PRIV,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(ARM11MPCorePriveState),
- .instance_init = mpcore_priv_initfn,
- .class_init = mpcore_priv_class_init,
+static const TypeInfo arm11mp_types[] = {
+ {
+ .name = TYPE_ARM11MPCORE_PRIV,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(ARM11MPCorePriveState),
+ .instance_init = mpcore_priv_initfn,
+ .class_init = mpcore_priv_class_init,
+ },
};
-static void arm11mpcore_register_types(void)
-{
- type_register_static(&mpcore_priv_info);
-}
-
-type_init(arm11mpcore_register_types)
+DEFINE_TYPES(arm11mp_types)
diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c
index 7480b38d1ab..b1408886184 100644
--- a/hw/cpu/realview_mpcore.c
+++ b/hw/cpu/realview_mpcore.c
@@ -114,17 +114,14 @@ static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
dc->realize = realview_mpcore_realize;
}
-static const TypeInfo mpcore_rirq_info = {
- .name = TYPE_REALVIEW_MPCORE_RIRQ,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(mpcore_rirq_state),
- .instance_init = mpcore_rirq_init,
- .class_init = mpcore_rirq_class_init,
+static const TypeInfo realview_mpcore_types[] = {
+ {
+ .name = TYPE_REALVIEW_MPCORE_RIRQ,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(mpcore_rirq_state),
+ .instance_init = mpcore_rirq_init,
+ .class_init = mpcore_rirq_class_init,
+ },
};
-static void realview_mpcore_register_types(void)
-{
- type_register_static(&mpcore_rirq_info);
-}
-
-type_init(realview_mpcore_register_types)
+DEFINE_TYPES(realview_mpcore_types)
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 10/12] hw/net/cadence_gem: Fix the mask/compare/disable-mask logic
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2025-02-10 15:49 ` [PULL 09/12] hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 11/12] qemu-options: Deprecate -old-param command line option Peter Maydell
` (2 subsequent siblings)
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
From: Andrew Yuan <andrew.yuan@jaguarmicro.com>
Our current handling of the mask/compare logic in the Cadence
GEM ethernet device is wrong:
(1) we load the same byte twice from rx_buf when
creating the compare value
(2) we ignore the DISABLE_MASK flag
The "Cadence IP for Gigabit Ethernet MAC Part Number: IP7014 IP Rev:
R1p12 - Doc Rev: 1.3 User Guide" states that if the DISABLE_MASK bit
in type2_compare_x_word_1 is set, the mask_value field in
type2_compare_x_word_0 is used as an additional 2 byte Compare Value.
Correct these bugs:
* in the !disable_mask codepath, use lduw_le_p() so we
correctly load a 16-bit value for comparison
* in the disable_mask codepath, we load a full 4-byte value
from rx_buf for the comparison, set the compare value to
the whole of the cr0 register (i.e. the concatenation of
the mask and compare fields), and set mask to 0xffffffff
to force a 32-bit comparison
Signed-off-by: Andrew Yuan <andrew.yuan@jaguarmicro.com>
Message-id: 20241219061658.805-1-andrew.yuan@jaguarmicro.com
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[PMM: Expand commit message and comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/cadence_gem.c | 26 +++++++++++++++++++++-----
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index f744054a6d8..80fbbacc1e7 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -909,8 +909,8 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
/* Compare A, B, C */
for (j = 0; j < 3; j++) {
- uint32_t cr0, cr1, mask, compare;
- uint16_t rx_cmp;
+ uint32_t cr0, cr1, mask, compare, disable_mask;
+ uint32_t rx_cmp;
int offset;
int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6,
R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH);
@@ -946,9 +946,25 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
break;
}
- rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
- mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE);
- compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE);
+ disable_mask =
+ FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, DISABLE_MASK);
+ if (disable_mask) {
+ /*
+ * If disable_mask is set, mask_value is used as an
+ * additional 2 byte Compare Value; that is equivalent
+ * to using the whole cr0 register as the comparison value.
+ * Load 32 bits of data from rx_buf, and set mask to
+ * all-ones so we compare all 32 bits.
+ */
+ rx_cmp = ldl_le_p(rxbuf_ptr + offset);
+ mask = 0xFFFFFFFF;
+ compare = cr0;
+ } else {
+ rx_cmp = lduw_le_p(rxbuf_ptr + offset);
+ mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE);
+ compare =
+ FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE);
+ }
if ((rx_cmp & mask) == (compare & mask)) {
matched = true;
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 11/12] qemu-options: Deprecate -old-param command line option
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2025-02-10 15:49 ` [PULL 10/12] hw/net/cadence_gem: Fix the mask/compare/disable-mask logic Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-10 15:49 ` [PULL 12/12] linux-user: Do not define struct sched_attr if libc headers do Peter Maydell
2025-02-11 2:37 ` [PULL 00/12] target-arm queue Stefan Hajnoczi
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
The '-old-param' command line option is specific to Arm targets; it
is very briefly documented as "old param mode". What this option
actually does is change the behaviour when directly booting a guest
kernel, so that command line arguments are passed to the kernel using
the extremely old "param_struct" ABI, rather than the newer ATAGS or
even newer DTB mechanisms.
This support was added back in 2007 to support an old vendor kernel
on the akita/terrier board types:
https://mail.gnu.org/archive/html/qemu-devel/2007-07/msg00344.html
Even then, it was an out-of-date mechanism from the kernel's
point of view -- the kernel has had a comment since 2001 marking
it as deprecated. As of mid-2024, the kernel only retained
param_struct support for the RiscPC and Footbridge platforms:
https://lore.kernel.org/linux-arm-kernel/2831c5a6-cfbf-4fe0-b51c-0396e5b0aeb7@app.fastmail.com/
None of the board types QEMU supports need param_struct support;
mark this option as deprecated.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20250127123113.2947620-1-peter.maydell@linaro.org
---
docs/about/deprecated.rst | 13 +++++++++++++
system/vl.c | 1 +
2 files changed, 14 insertions(+)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 29de49351d1..a4c7d642236 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -68,6 +68,19 @@ configurations (e.g. -smp drawers=1,books=1,clusters=1 for x86 PC machine) is
marked deprecated since 9.0, users have to ensure that all the topology members
described with -smp are supported by the target machine.
+``-old-param`` option for booting Arm kernels via param_struct (since 10.0)
+'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+The ``-old-param`` command line option is specific to Arm targets:
+it is used when directly booting a guest kernel to pass it the
+command line and other information via the old ``param_struct`` ABI,
+rather than the newer ATAGS or DTB mechanisms. This option was only
+ever needed to support ancient kernels on some old board types
+like the ``akita`` or ``terrier``; it has been deprecated in the
+kernel since 2001. None of the board types QEMU supports need
+``param_struct`` support, so this option has been deprecated and will
+be removed in a future QEMU version.
+
User-mode emulator command line arguments
-----------------------------------------
diff --git a/system/vl.c b/system/vl.c
index db8e604ebab..aa91047c480 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -3469,6 +3469,7 @@ void qemu_init(int argc, char **argv)
nb_prom_envs++;
break;
case QEMU_OPTION_old_param:
+ warn_report("-old-param is deprecated");
old_param = 1;
break;
case QEMU_OPTION_rtc:
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PULL 12/12] linux-user: Do not define struct sched_attr if libc headers do
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2025-02-10 15:49 ` [PULL 11/12] qemu-options: Deprecate -old-param command line option Peter Maydell
@ 2025-02-10 15:49 ` Peter Maydell
2025-02-11 2:37 ` [PULL 00/12] target-arm queue Stefan Hajnoczi
12 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2025-02-10 15:49 UTC (permalink / raw)
To: qemu-devel
From: Khem Raj <raj.khem@gmail.com>
glibc 2.41+ has added [1] definitions for sched_setattr and
sched_getattr functions and struct sched_attr. Therefore, it needs
to be checked for here as well before defining sched_attr, to avoid
a compilation failure.
Define sched_attr conditionally only when SCHED_ATTR_SIZE_VER0 is
not defined.
[1] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=21571ca0d70302909cf72707b2a7736cf12190a0;hp=298bc488fdc047da37482f4003023cb9adef78f8
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2799
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/syscall.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 6ee02383daf..df5ed18062c 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -360,7 +360,8 @@ _syscall3(int, sys_sched_getaffinity, pid_t, pid, unsigned int, len,
#define __NR_sys_sched_setaffinity __NR_sched_setaffinity
_syscall3(int, sys_sched_setaffinity, pid_t, pid, unsigned int, len,
unsigned long *, user_mask_ptr);
-/* sched_attr is not defined in glibc */
+/* sched_attr is not defined in glibc < 2.41 */
+#ifndef SCHED_ATTR_SIZE_VER0
struct sched_attr {
uint32_t size;
uint32_t sched_policy;
@@ -373,6 +374,7 @@ struct sched_attr {
uint32_t sched_util_min;
uint32_t sched_util_max;
};
+#endif
#define __NR_sys_sched_getattr __NR_sched_getattr
_syscall4(int, sys_sched_getattr, pid_t, pid, struct sched_attr *, attr,
unsigned int, size, unsigned int, flags);
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PULL 00/12] target-arm queue
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2025-02-10 15:49 ` [PULL 12/12] linux-user: Do not define struct sched_attr if libc headers do Peter Maydell
@ 2025-02-11 2:37 ` Stefan Hajnoczi
12 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2025-02-11 2:37 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2025-02-11 2:38 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-02-10 15:49 [PULL 00/12] target-arm queue Peter Maydell
2025-02-10 15:49 ` [PULL 01/12] target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation Peter Maydell
2025-02-10 15:49 ` [PULL 02/12] tests/tcg/arm: Remove test-arm-iwmmxt test Peter Maydell
2025-02-10 15:49 ` [PULL 03/12] target/arm: Drop unused AArch64DecodeTable typedefs Peter Maydell
2025-02-10 15:49 ` [PULL 04/12] hw/arm/boot: Propagate vCPU to arm_load_dtb() Peter Maydell
2025-02-10 15:49 ` [PULL 05/12] hw/arm/fsl-imx6: Add local 'mpcore/gic' variables Peter Maydell
2025-02-10 15:49 ` [PULL 06/12] hw/arm/fsl-imx6ul: " Peter Maydell
2025-02-10 15:49 ` [PULL 07/12] hw/arm/fsl-imx7: " Peter Maydell
2025-02-10 15:49 ` [PULL 08/12] hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE Peter Maydell
2025-02-10 15:49 ` [PULL 09/12] hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro Peter Maydell
2025-02-10 15:49 ` [PULL 10/12] hw/net/cadence_gem: Fix the mask/compare/disable-mask logic Peter Maydell
2025-02-10 15:49 ` [PULL 11/12] qemu-options: Deprecate -old-param command line option Peter Maydell
2025-02-10 15:49 ` [PULL 12/12] linux-user: Do not define struct sched_attr if libc headers do Peter Maydell
2025-02-11 2:37 ` [PULL 00/12] target-arm queue Stefan Hajnoczi
-- strict thread matches above, loose matches on Subject: below --
2023-11-06 15:32 Peter Maydell
2023-11-07 3:02 ` Stefan Hajnoczi
2023-05-12 15:34 Peter Maydell
2023-05-13 8:36 ` Richard Henderson
2021-07-18 12:46 Peter Maydell
2021-07-18 16:35 ` Peter Maydell
2020-10-08 14:25 Peter Maydell
2020-07-20 12:56 Peter Maydell
2020-07-20 21:24 ` Peter Maydell
2020-04-14 16:26 Peter Maydell
2020-04-14 19:09 ` Peter Maydell
2019-12-20 14:26 Peter Maydell
2020-01-06 10:32 ` Peter Maydell
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