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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 63/68] target/arm: Remove fp_status_a64
Date: Tue, 11 Feb 2025 16:25:49 +0000	[thread overview]
Message-ID: <20250211162554.4135349-64-peter.maydell@linaro.org> (raw)
In-Reply-To: <20250211162554.4135349-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Replace with fp_status[FPST_A64].

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250129013857.135256-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h            |  1 -
 target/arm/cpu.c            |  2 +-
 target/arm/tcg/sme_helper.c |  2 +-
 target/arm/tcg/vec_helper.c | 10 +++++-----
 target/arm/vfp_helper.c     | 16 ++++++++--------
 5 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 1593cc1036a..0d8b99bd8af 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -691,7 +691,6 @@ typedef struct CPUArchState {
             float_status fp_status[FPST_COUNT];
             struct {
                 float_status fp_status_a32;
-                float_status fp_status_a64;
             };
         };
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 88bff67300c..f04f28b681a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -551,7 +551,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
     set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]);
     set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]);
     arm_set_default_fp_behaviours(&env->vfp.fp_status_a32);
-    arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
+    arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]);
     arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]);
     arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]);
     arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
index 6e336e10c6a..dcc48e43db3 100644
--- a/target/arm/tcg/sme_helper.c
+++ b/target/arm/tcg/sme_helper.c
@@ -1044,7 +1044,7 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
      * round-to-odd -- see above.
      */
     fpst_f16 = env->vfp.fp_status[FPST_A64_F16];
-    fpst_std = env->vfp.fp_status_a64;
+    fpst_std = env->vfp.fp_status[FPST_A64];
     set_default_nan_mode(true, &fpst_std);
     set_default_nan_mode(true, &fpst_f16);
     fpst_odd = fpst_std;
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 78f14503f49..215affc2711 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2172,7 +2172,7 @@ void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
             negx = 0x8000800080008000ull;
         }
     }
-    do_fmlal(vd, vn, vm, &env->vfp.fp_status_a64, negx, negf, desc,
+    do_fmlal(vd, vn, vm, &env->vfp.fp_status[FPST_A64], negx, negf, desc,
              get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]));
 }
 
@@ -2182,7 +2182,7 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
     intptr_t i, oprsz = simd_oprsz(desc);
     bool is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
     intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
-    float_status *status = &env->vfp.fp_status_a64;
+    float_status *status = &env->vfp.fp_status[FPST_A64];
     bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]);
     int negx = 0, negf = 0;
 
@@ -2253,7 +2253,7 @@ void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
             negx = 0x8000800080008000ull;
         }
     }
-    do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status_a64, negx, negf, desc,
+    do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status[FPST_A64], negx, negf, desc,
                  get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]));
 }
 
@@ -2264,7 +2264,7 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
     bool is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
     intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
     intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16);
-    float_status *status = &env->vfp.fp_status_a64;
+    float_status *status = &env->vfp.fp_status[FPST_A64];
     bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]);
     int negx = 0, negf = 0;
 
@@ -2951,7 +2951,7 @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
      */
     bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
 
-    *statusp = is_a64(env) ? env->vfp.fp_status_a64 : env->vfp.fp_status_a32;
+    *statusp = is_a64(env) ? env->vfp.fp_status[FPST_A64] : env->vfp.fp_status_a32;
     set_default_nan_mode(true, statusp);
 
     if (ebf) {
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index dae46a099a3..e6b4f63401b 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -125,7 +125,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
     a32_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_STD_F16])
           & ~float_flag_input_denormal_flushed);
 
-    a64_flags |= get_float_exception_flags(&env->vfp.fp_status_a64);
+    a64_flags |= get_float_exception_flags(&env->vfp.fp_status[FPST_A64]);
     a64_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_A64_F16])
           & ~(float_flag_input_denormal_flushed | float_flag_input_denormal_used));
     /*
@@ -156,7 +156,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState *env)
      * be the architecturally up-to-date exception flag information first.
      */
     set_float_exception_flags(0, &env->vfp.fp_status_a32);
-    set_float_exception_flags(0, &env->vfp.fp_status_a64);
+    set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64]);
     set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32_F16]);
     set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]);
     set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]);
@@ -199,7 +199,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
             break;
         }
         set_float_rounding_mode(i, &env->vfp.fp_status_a32);
-        set_float_rounding_mode(i, &env->vfp.fp_status_a64);
+        set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64]);
         set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32_F16]);
         set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]);
     }
@@ -217,7 +217,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
     if (changed & FPCR_FZ) {
         bool ftz_enabled = val & FPCR_FZ;
         set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
-        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a64);
+        set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64]);
         /* FIZ is A64 only so FZ always makes A32 code flush inputs to zero */
         set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
     }
@@ -228,12 +228,12 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
          */
         bool fitz_enabled = (val & FPCR_FIZ) ||
             (val & (FPCR_FZ | FPCR_AH)) == FPCR_FZ;
-        set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status_a64);
+        set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status[FPST_A64]);
     }
     if (changed & FPCR_DN) {
         bool dnan_enabled = val & FPCR_DN;
         set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
-        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
+        set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64]);
         set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32_F16]);
         set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F16]);
         set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]);
@@ -244,10 +244,10 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask)
 
         if (ah_enabled) {
             /* Change behaviours for A64 FP operations */
-            arm_set_ah_fp_behaviours(&env->vfp.fp_status_a64);
+            arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64]);
             arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
         } else {
-            arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
+            arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]);
             arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
         }
     }
-- 
2.34.1



  parent reply	other threads:[~2025-02-11 16:32 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-11 16:24 [PULL 00/68] target-arm queue Peter Maydell
2025-02-11 16:24 ` [PULL 01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags Peter Maydell
2025-02-11 16:24 ` [PULL 02/68] fpu: Add float_class_denormal Peter Maydell
2025-02-11 16:24 ` [PULL 03/68] fpu: Implement float_flag_input_denormal_used Peter Maydell
2025-02-11 16:24 ` [PULL 04/68] fpu: allow flushing of output denormals to be after rounding Peter Maydell
2025-02-11 16:24 ` [PULL 05/68] target/arm: Define FPCR AH, FIZ, NEP bits Peter Maydell
2025-02-11 16:24 ` [PULL 06/68] target/arm: Implement FPCR.FIZ handling Peter Maydell
2025-02-11 16:24 ` [PULL 07/68] target/arm: Adjust FP behaviour for FPCR.AH = 1 Peter Maydell
2025-02-11 16:24 ` [PULL 08/68] target/arm: Adjust exception flag handling for AH " Peter Maydell
2025-02-11 16:24 ` [PULL 09/68] target/arm: Add FPCR.AH to tbflags Peter Maydell
2025-02-11 16:24 ` [PULL 10/68] target/arm: Set up float_status to use for FPCR.AH=1 behaviour Peter Maydell
2025-02-11 16:24 ` [PULL 11/68] target/arm: Use FPST_FPCR_AH for FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS Peter Maydell
2025-02-11 16:24 ` [PULL 12/68] target/arm: Use FPST_FPCR_AH for BFCVT* insns Peter Maydell
2025-02-11 16:24 ` [PULL 13/68] target/arm: Use FPST_FPCR_AH for BFMLAL*, BFMLSL* insns Peter Maydell
2025-02-11 16:25 ` [PULL 14/68] target/arm: Add FPCR.NEP to TBFLAGS Peter Maydell
2025-02-11 16:25 ` [PULL 15/68] target/arm: Define and use new write_fp_*reg_merging() functions Peter Maydell
2025-02-11 16:25 ` [PULL 16/68] target/arm: Handle FPCR.NEP for 3-input scalar operations Peter Maydell
2025-02-11 16:25 ` [PULL 17/68] target/arm: Handle FPCR.NEP for BFCVT scalar Peter Maydell
2025-02-11 16:25 ` [PULL 18/68] target/arm: Handle FPCR.NEP for 1-input scalar operations Peter Maydell
2025-02-11 16:25 ` [PULL 19/68] target/arm: Handle FPCR.NEP in do_cvtf_scalar() Peter Maydell
2025-02-11 16:25 ` [PULL 20/68] target/arm: Handle FPCR.NEP for scalar FABS and FNEG Peter Maydell
2025-02-11 16:25 ` [PULL 21/68] target/arm: Handle FPCR.NEP for FCVTXN (scalar) Peter Maydell
2025-02-11 16:25 ` [PULL 22/68] target/arm: Handle FPCR.NEP for NEP for FMUL, FMULX scalar by element Peter Maydell
2025-02-11 16:25 ` [PULL 23/68] target/arm: Implement FPCR.AH semantics for scalar FMIN/FMAX Peter Maydell
2025-02-11 16:25 ` [PULL 24/68] target/arm: Implement FPCR.AH semantics for vector FMIN/FMAX Peter Maydell
2025-02-11 16:25 ` [PULL 25/68] target/arm: Implement FPCR.AH semantics for FMAXV and FMINV Peter Maydell
2025-02-11 16:25 ` [PULL 26/68] target/arm: Implement FPCR.AH semantics for FMINP and FMAXP Peter Maydell
2025-02-11 16:25 ` [PULL 27/68] target/arm: Implement FPCR.AH semantics for SVE FMAXV and FMINV Peter Maydell
2025-02-11 16:25 ` [PULL 28/68] target/arm: Implement FPCR.AH semantics for SVE FMIN/FMAX immediate Peter Maydell
2025-02-11 16:25 ` [PULL 29/68] target/arm: Implement FPCR.AH semantics for SVE FMIN/FMAX vector Peter Maydell
2025-02-11 16:25 ` [PULL 30/68] target/arm: Implement FPCR.AH handling of negation of NaN Peter Maydell
2025-02-11 16:25 ` [PULL 31/68] target/arm: Implement FPCR.AH handling for scalar FABS and FABD Peter Maydell
2025-02-11 16:25 ` [PULL 32/68] target/arm: Handle FPCR.AH in vector FABD Peter Maydell
2025-02-11 16:25 ` [PULL 33/68] target/arm: Handle FPCR.AH in SVE FNEG Peter Maydell
2025-02-11 16:25 ` [PULL 34/68] target/arm: Handle FPCR.AH in SVE FABS Peter Maydell
2025-02-11 16:25 ` [PULL 35/68] target/arm: Handle FPCR.AH in SVE FABD Peter Maydell
2025-02-11 16:25 ` [PULL 36/68] target/arm: Handle FPCR.AH in negation steps in SVE FCADD Peter Maydell
2025-02-11 16:25 ` [PULL 37/68] target/arm: Handle FPCR.AH in negation steps in FCADD Peter Maydell
2025-02-11 16:25 ` [PULL 38/68] target/arm: Handle FPCR.AH in FRECPS and FRSQRTS scalar insns Peter Maydell
2025-02-11 16:25 ` [PULL 39/68] target/arm: Handle FPCR.AH in FRECPS and FRSQRTS vector insns Peter Maydell
2025-02-11 16:25 ` [PULL 40/68] target/arm: Handle FPCR.AH in negation step in FMLS (indexed) Peter Maydell
2025-02-11 16:25 ` [PULL 41/68] target/arm: Handle FPCR.AH in negation in FMLS (vector) Peter Maydell
2025-02-11 16:25 ` [PULL 42/68] target/arm: Handle FPCR.AH in negation step in SVE " Peter Maydell
2025-02-11 16:25 ` [PULL 43/68] target/arm: Handle FPCR.AH in SVE FTSSEL Peter Maydell
2025-02-11 16:25 ` [PULL 44/68] target/arm: Handle FPCR.AH in SVE FTMAD Peter Maydell
2025-02-11 16:25 ` [PULL 45/68] target/arm: Handle FPCR.AH in vector FCMLA Peter Maydell
2025-02-11 16:25 ` [PULL 46/68] target/arm: Handle FPCR.AH in FCMLA by index Peter Maydell
2025-02-11 16:25 ` [PULL 47/68] target/arm: Handle FPCR.AH in SVE FCMLA Peter Maydell
2025-02-11 16:25 ` [PULL 48/68] target/arm: Handle FPCR.AH in FMLSL (by element and vector) Peter Maydell
2025-02-11 16:25 ` [PULL 49/68] target/arm: Handle FPCR.AH in SVE FMLSL (indexed) Peter Maydell
2025-02-11 16:25 ` [PULL 50/68] target/arm: Handle FPCR.AH in SVE FMLSLB, FMLSLT (vectors) Peter Maydell
2025-02-11 16:25 ` [PULL 51/68] target/arm: Enable FEAT_AFP for '-cpu max' Peter Maydell
2025-02-11 16:25 ` [PULL 52/68] target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper Peter Maydell
2025-02-11 16:25 ` [PULL 53/68] target/arm: Implement increased precision FRECPE Peter Maydell
2025-02-11 16:25 ` [PULL 54/68] target/arm: Implement increased precision FRSQRTE Peter Maydell
2025-02-11 16:25 ` [PULL 55/68] target/arm: Enable FEAT_RPRES for -cpu max Peter Maydell
2025-02-11 16:25 ` [PULL 56/68] target/arm: Introduce CPUARMState.vfp.fp_status[] Peter Maydell
2025-02-11 16:25 ` [PULL 57/68] target/arm: Remove standard_fp_status_f16 Peter Maydell
2025-02-11 16:25 ` [PULL 58/68] target/arm: Remove standard_fp_status Peter Maydell
2025-02-11 16:25 ` [PULL 59/68] target/arm: Remove ah_fp_status_f16 Peter Maydell
2025-02-11 16:25 ` [PULL 60/68] target/arm: Remove ah_fp_status Peter Maydell
2025-02-11 16:25 ` [PULL 61/68] target/arm: Remove fp_status_f16_a64 Peter Maydell
2025-02-11 16:25 ` [PULL 62/68] target/arm: Remove fp_status_f16_a32 Peter Maydell
2025-02-11 16:25 ` Peter Maydell [this message]
2025-02-11 16:25 ` [PULL 64/68] target/arm: Remove fp_status_a32 Peter Maydell
2025-02-11 16:25 ` [PULL 65/68] target/arm: Simplify fp_status indexing in mve_helper.c Peter Maydell
2025-02-11 16:25 ` [PULL 66/68] target/arm: Simplify DO_VFP_cmp in vfp_helper.c Peter Maydell
2025-02-11 16:25 ` [PULL 67/68] target/arm: Read fz16 from env->vfp.fpcr Peter Maydell
2025-02-11 16:25 ` [PULL 68/68] target/arm: Sink fp_status and fpcr access into do_fmlal* Peter Maydell
2025-02-12 17:38 ` [PULL 00/68] target-arm queue Stefan Hajnoczi

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