From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 65/68] target/arm: Simplify fp_status indexing in mve_helper.c
Date: Tue, 11 Feb 2025 16:25:51 +0000 [thread overview]
Message-ID: <20250211162554.4135349-66-peter.maydell@linaro.org> (raw)
In-Reply-To: <20250211162554.4135349-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Select on index instead of pointer.
No functional change.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250129013857.135256-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/mve_helper.c | 40 +++++++++++++------------------------
1 file changed, 14 insertions(+), 26 deletions(-)
diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c
index 3763d71e20b..274003e2e5b 100644
--- a/target/arm/tcg/mve_helper.c
+++ b/target/arm/tcg/mve_helper.c
@@ -2814,8 +2814,7 @@ DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN)
if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \
continue; \
} \
- fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
if (!(mask & 1)) { \
/* We need the result but without updating flags */ \
scratch_fpst = *fpst; \
@@ -2888,8 +2887,7 @@ DO_2OP_FP_ALL(vminnma, minnuma)
r[e] = 0; \
continue; \
} \
- fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
if (!(tm & 1)) { \
/* We need the result but without updating flags */ \
scratch_fpst = *fpst; \
@@ -2926,8 +2924,7 @@ DO_VCADD_FP(vfcadd270s, 4, float32, float32_add, float32_sub)
if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \
continue; \
} \
- fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
if (!(mask & 1)) { \
/* We need the result but without updating flags */ \
scratch_fpst = *fpst; \
@@ -2964,8 +2961,7 @@ DO_VFMA(vfmss, 4, float32, true)
if ((mask & MAKE_64BIT_MASK(0, ESIZE * 2)) == 0) { \
continue; \
} \
- fpst0 = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ fpst0 = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
fpst1 = fpst0; \
if (!(mask & 1)) { \
scratch_fpst = *fpst0; \
@@ -3049,8 +3045,7 @@ DO_VCMLA(vcmla270s, 4, float32, 3, DO_VCMLAS)
if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \
continue; \
} \
- fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
if (!(mask & 1)) { \
/* We need the result but without updating flags */ \
scratch_fpst = *fpst; \
@@ -3084,8 +3079,7 @@ DO_2OP_FP_SCALAR_ALL(vfmul_scalar, mul)
if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \
continue; \
} \
- fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
if (!(mask & 1)) { \
/* We need the result but without updating flags */ \
scratch_fpst = *fpst; \
@@ -3116,9 +3110,8 @@ DO_2OP_FP_ACC_SCALAR(vfmas_scalars, 4, float32, DO_VFMAS_SCALARS)
unsigned e; \
TYPE *m = vm; \
TYPE ra = (TYPE)ra_in; \
- float_status *fpst = (ESIZE == 2) ? \
- &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ float_status *fpst = \
+ &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
if (mask & 1) { \
TYPE v = m[H##ESIZE(e)]; \
@@ -3168,8 +3161,7 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum)
if ((mask & emask) == 0) { \
continue; \
} \
- fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
if (!(mask & (1 << (e * ESIZE)))) { \
/* We need the result but without updating flags */ \
scratch_fpst = *fpst; \
@@ -3202,8 +3194,7 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum)
if ((mask & emask) == 0) { \
continue; \
} \
- fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
if (!(mask & (1 << (e * ESIZE)))) { \
/* We need the result but without updating flags */ \
scratch_fpst = *fpst; \
@@ -3267,8 +3258,7 @@ DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32)
if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \
continue; \
} \
- fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
if (!(mask & 1)) { \
/* We need the result but without updating flags */ \
scratch_fpst = *fpst; \
@@ -3300,9 +3290,8 @@ DO_VCVT_FIXED(vcvt_fu, 4, uint32_t, helper_vfp_touls_round_to_zero)
unsigned e; \
float_status *fpst; \
float_status scratch_fpst; \
- float_status *base_fpst = (ESIZE == 2) ? \
- &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ float_status *base_fpst = \
+ &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
uint32_t prev_rmode = get_float_rounding_mode(base_fpst); \
set_float_rounding_mode(rmode, base_fpst); \
for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
@@ -3427,8 +3416,7 @@ void HELPER(mve_vcvtt_hs)(CPUARMState *env, void *vd, void *vm)
if ((mask & MAKE_64BIT_MASK(0, ESIZE)) == 0) { \
continue; \
} \
- fpst = (ESIZE == 2) ? &env->vfp.fp_status[FPST_STD_F16] : \
- &env->vfp.fp_status[FPST_STD]; \
+ fpst = &env->vfp.fp_status[ESIZE == 2 ? FPST_STD_F16 : FPST_STD]; \
if (!(mask & 1)) { \
/* We need the result but without updating flags */ \
scratch_fpst = *fpst; \
--
2.34.1
next prev parent reply other threads:[~2025-02-11 16:34 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 16:24 [PULL 00/68] target-arm queue Peter Maydell
2025-02-11 16:24 ` [PULL 01/68] target/alpha: Don't corrupt error_code with unknown softfloat flags Peter Maydell
2025-02-11 16:24 ` [PULL 02/68] fpu: Add float_class_denormal Peter Maydell
2025-02-11 16:24 ` [PULL 03/68] fpu: Implement float_flag_input_denormal_used Peter Maydell
2025-02-11 16:24 ` [PULL 04/68] fpu: allow flushing of output denormals to be after rounding Peter Maydell
2025-02-11 16:24 ` [PULL 05/68] target/arm: Define FPCR AH, FIZ, NEP bits Peter Maydell
2025-02-11 16:24 ` [PULL 06/68] target/arm: Implement FPCR.FIZ handling Peter Maydell
2025-02-11 16:24 ` [PULL 07/68] target/arm: Adjust FP behaviour for FPCR.AH = 1 Peter Maydell
2025-02-11 16:24 ` [PULL 08/68] target/arm: Adjust exception flag handling for AH " Peter Maydell
2025-02-11 16:24 ` [PULL 09/68] target/arm: Add FPCR.AH to tbflags Peter Maydell
2025-02-11 16:24 ` [PULL 10/68] target/arm: Set up float_status to use for FPCR.AH=1 behaviour Peter Maydell
2025-02-11 16:24 ` [PULL 11/68] target/arm: Use FPST_FPCR_AH for FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS Peter Maydell
2025-02-11 16:24 ` [PULL 12/68] target/arm: Use FPST_FPCR_AH for BFCVT* insns Peter Maydell
2025-02-11 16:24 ` [PULL 13/68] target/arm: Use FPST_FPCR_AH for BFMLAL*, BFMLSL* insns Peter Maydell
2025-02-11 16:25 ` [PULL 14/68] target/arm: Add FPCR.NEP to TBFLAGS Peter Maydell
2025-02-11 16:25 ` [PULL 15/68] target/arm: Define and use new write_fp_*reg_merging() functions Peter Maydell
2025-02-11 16:25 ` [PULL 16/68] target/arm: Handle FPCR.NEP for 3-input scalar operations Peter Maydell
2025-02-11 16:25 ` [PULL 17/68] target/arm: Handle FPCR.NEP for BFCVT scalar Peter Maydell
2025-02-11 16:25 ` [PULL 18/68] target/arm: Handle FPCR.NEP for 1-input scalar operations Peter Maydell
2025-02-11 16:25 ` [PULL 19/68] target/arm: Handle FPCR.NEP in do_cvtf_scalar() Peter Maydell
2025-02-11 16:25 ` [PULL 20/68] target/arm: Handle FPCR.NEP for scalar FABS and FNEG Peter Maydell
2025-02-11 16:25 ` [PULL 21/68] target/arm: Handle FPCR.NEP for FCVTXN (scalar) Peter Maydell
2025-02-11 16:25 ` [PULL 22/68] target/arm: Handle FPCR.NEP for NEP for FMUL, FMULX scalar by element Peter Maydell
2025-02-11 16:25 ` [PULL 23/68] target/arm: Implement FPCR.AH semantics for scalar FMIN/FMAX Peter Maydell
2025-02-11 16:25 ` [PULL 24/68] target/arm: Implement FPCR.AH semantics for vector FMIN/FMAX Peter Maydell
2025-02-11 16:25 ` [PULL 25/68] target/arm: Implement FPCR.AH semantics for FMAXV and FMINV Peter Maydell
2025-02-11 16:25 ` [PULL 26/68] target/arm: Implement FPCR.AH semantics for FMINP and FMAXP Peter Maydell
2025-02-11 16:25 ` [PULL 27/68] target/arm: Implement FPCR.AH semantics for SVE FMAXV and FMINV Peter Maydell
2025-02-11 16:25 ` [PULL 28/68] target/arm: Implement FPCR.AH semantics for SVE FMIN/FMAX immediate Peter Maydell
2025-02-11 16:25 ` [PULL 29/68] target/arm: Implement FPCR.AH semantics for SVE FMIN/FMAX vector Peter Maydell
2025-02-11 16:25 ` [PULL 30/68] target/arm: Implement FPCR.AH handling of negation of NaN Peter Maydell
2025-02-11 16:25 ` [PULL 31/68] target/arm: Implement FPCR.AH handling for scalar FABS and FABD Peter Maydell
2025-02-11 16:25 ` [PULL 32/68] target/arm: Handle FPCR.AH in vector FABD Peter Maydell
2025-02-11 16:25 ` [PULL 33/68] target/arm: Handle FPCR.AH in SVE FNEG Peter Maydell
2025-02-11 16:25 ` [PULL 34/68] target/arm: Handle FPCR.AH in SVE FABS Peter Maydell
2025-02-11 16:25 ` [PULL 35/68] target/arm: Handle FPCR.AH in SVE FABD Peter Maydell
2025-02-11 16:25 ` [PULL 36/68] target/arm: Handle FPCR.AH in negation steps in SVE FCADD Peter Maydell
2025-02-11 16:25 ` [PULL 37/68] target/arm: Handle FPCR.AH in negation steps in FCADD Peter Maydell
2025-02-11 16:25 ` [PULL 38/68] target/arm: Handle FPCR.AH in FRECPS and FRSQRTS scalar insns Peter Maydell
2025-02-11 16:25 ` [PULL 39/68] target/arm: Handle FPCR.AH in FRECPS and FRSQRTS vector insns Peter Maydell
2025-02-11 16:25 ` [PULL 40/68] target/arm: Handle FPCR.AH in negation step in FMLS (indexed) Peter Maydell
2025-02-11 16:25 ` [PULL 41/68] target/arm: Handle FPCR.AH in negation in FMLS (vector) Peter Maydell
2025-02-11 16:25 ` [PULL 42/68] target/arm: Handle FPCR.AH in negation step in SVE " Peter Maydell
2025-02-11 16:25 ` [PULL 43/68] target/arm: Handle FPCR.AH in SVE FTSSEL Peter Maydell
2025-02-11 16:25 ` [PULL 44/68] target/arm: Handle FPCR.AH in SVE FTMAD Peter Maydell
2025-02-11 16:25 ` [PULL 45/68] target/arm: Handle FPCR.AH in vector FCMLA Peter Maydell
2025-02-11 16:25 ` [PULL 46/68] target/arm: Handle FPCR.AH in FCMLA by index Peter Maydell
2025-02-11 16:25 ` [PULL 47/68] target/arm: Handle FPCR.AH in SVE FCMLA Peter Maydell
2025-02-11 16:25 ` [PULL 48/68] target/arm: Handle FPCR.AH in FMLSL (by element and vector) Peter Maydell
2025-02-11 16:25 ` [PULL 49/68] target/arm: Handle FPCR.AH in SVE FMLSL (indexed) Peter Maydell
2025-02-11 16:25 ` [PULL 50/68] target/arm: Handle FPCR.AH in SVE FMLSLB, FMLSLT (vectors) Peter Maydell
2025-02-11 16:25 ` [PULL 51/68] target/arm: Enable FEAT_AFP for '-cpu max' Peter Maydell
2025-02-11 16:25 ` [PULL 52/68] target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper Peter Maydell
2025-02-11 16:25 ` [PULL 53/68] target/arm: Implement increased precision FRECPE Peter Maydell
2025-02-11 16:25 ` [PULL 54/68] target/arm: Implement increased precision FRSQRTE Peter Maydell
2025-02-11 16:25 ` [PULL 55/68] target/arm: Enable FEAT_RPRES for -cpu max Peter Maydell
2025-02-11 16:25 ` [PULL 56/68] target/arm: Introduce CPUARMState.vfp.fp_status[] Peter Maydell
2025-02-11 16:25 ` [PULL 57/68] target/arm: Remove standard_fp_status_f16 Peter Maydell
2025-02-11 16:25 ` [PULL 58/68] target/arm: Remove standard_fp_status Peter Maydell
2025-02-11 16:25 ` [PULL 59/68] target/arm: Remove ah_fp_status_f16 Peter Maydell
2025-02-11 16:25 ` [PULL 60/68] target/arm: Remove ah_fp_status Peter Maydell
2025-02-11 16:25 ` [PULL 61/68] target/arm: Remove fp_status_f16_a64 Peter Maydell
2025-02-11 16:25 ` [PULL 62/68] target/arm: Remove fp_status_f16_a32 Peter Maydell
2025-02-11 16:25 ` [PULL 63/68] target/arm: Remove fp_status_a64 Peter Maydell
2025-02-11 16:25 ` [PULL 64/68] target/arm: Remove fp_status_a32 Peter Maydell
2025-02-11 16:25 ` Peter Maydell [this message]
2025-02-11 16:25 ` [PULL 66/68] target/arm: Simplify DO_VFP_cmp in vfp_helper.c Peter Maydell
2025-02-11 16:25 ` [PULL 67/68] target/arm: Read fz16 from env->vfp.fpcr Peter Maydell
2025-02-11 16:25 ` [PULL 68/68] target/arm: Sink fp_status and fpcr access into do_fmlal* Peter Maydell
2025-02-12 17:38 ` [PULL 00/68] target-arm queue Stefan Hajnoczi
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