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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 0/6] tcg: Introduce constraint for zero register
Date: Tue, 11 Feb 2025 19:46:11 -0800	[thread overview]
Message-ID: <20250212034617.1079324-1-richard.henderson@linaro.org> (raw)

Based-on: 20250205040341.2056361-1-richard.henderson@linaro.org
("[PATCH 00/11] tcg: Cleanups after disallowing 64-on-32")

Introduce a new general-purpose constraint which maps 0
to TCG_REG_ZERO, if defined.  This differs from existing
constant constraints in that const_arg[*] is recorded as
false, indicating that the value is in a register.

This doesn't make much difference to the current tree, but as a
prelude to [1], where small output functions are categorized by
register vs immediate arguments, then this provides a way to
send a constant zero as a register argument.


r~


[1] https://patchew.org/QEMU/20250107080112.1175095-1-richard.henderson@linaro.org/

Richard Henderson (6):
  tcg: Introduce the 'z' constraint for a hardware zero register
  tcg/aarch64: Use 'z' constraint
  tcg/loongarch64: Use 'z' constraint
  tcg/mips: Use 'z' constraint
  tcg/riscv: Use 'z' constraint
  tcg/sparc64: Use 'z' constraint

 include/tcg/tcg.h                    |  3 +-
 tcg/aarch64/tcg-target-con-set.h     | 12 ++++----
 tcg/aarch64/tcg-target.h             |  2 ++
 tcg/loongarch64/tcg-target-con-set.h | 15 +++++----
 tcg/loongarch64/tcg-target-con-str.h |  1 -
 tcg/loongarch64/tcg-target.h         |  2 ++
 tcg/mips/tcg-target-con-set.h        | 26 ++++++++--------
 tcg/mips/tcg-target-con-str.h        |  1 -
 tcg/mips/tcg-target.h                |  2 ++
 tcg/riscv/tcg-target-con-set.h       | 10 +++---
 tcg/riscv/tcg-target-con-str.h       |  1 -
 tcg/riscv/tcg-target.h               |  2 ++
 tcg/sparc64/tcg-target-con-set.h     | 12 ++++----
 tcg/sparc64/tcg-target-con-str.h     |  1 -
 tcg/sparc64/tcg-target.h             |  3 +-
 tcg/tcg.c                            | 29 +++++++++++++-----
 docs/devel/tcg-ops.rst               |  4 ++-
 tcg/aarch64/tcg-target.c.inc         | 46 ++++++++++++----------------
 tcg/loongarch64/tcg-target.c.inc     | 32 +++++++++----------
 tcg/mips/tcg-target.c.inc            | 44 +++++++++++---------------
 tcg/riscv/tcg-target.c.inc           | 12 ++++----
 tcg/sparc64/tcg-target.c.inc         | 12 ++++----
 22 files changed, 138 insertions(+), 134 deletions(-)

-- 
2.43.0



             reply	other threads:[~2025-02-12  3:47 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-12  3:46 Richard Henderson [this message]
2025-02-12  3:46 ` [PATCH 1/6] tcg: Introduce the 'z' constraint for a hardware zero register Richard Henderson
2025-02-13 15:45   ` Philippe Mathieu-Daudé
2025-02-13 17:15     ` Richard Henderson
2025-02-12  3:46 ` [PATCH 2/6] tcg/aarch64: Use 'z' constraint Richard Henderson
2025-02-16 13:06   ` Philippe Mathieu-Daudé
2025-02-12  3:46 ` [PATCH 3/6] tcg/loongarch64: " Richard Henderson
2025-02-13 15:47   ` Philippe Mathieu-Daudé
2025-02-12  3:46 ` [PATCH 4/6] tcg/mips: " Richard Henderson
2025-02-13 15:47   ` Philippe Mathieu-Daudé
2025-02-12  3:46 ` [PATCH 5/6] tcg/riscv: " Richard Henderson
2025-02-13 15:50   ` Philippe Mathieu-Daudé
2025-02-13 15:54     ` Philippe Mathieu-Daudé
2025-02-12  3:46 ` [PATCH 6/6] tcg/sparc64: " Richard Henderson
2025-02-13 15:53   ` Philippe Mathieu-Daudé
2025-02-15 20:06 ` [PATCH 0/6] tcg: Introduce constraint for zero register Richard Henderson

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