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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-730992eba96sm3482569b3a.126.2025.02.11.19.46.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 19:46:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 0/6] tcg: Introduce constraint for zero register Date: Tue, 11 Feb 2025 19:46:11 -0800 Message-ID: <20250212034617.1079324-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based-on: 20250205040341.2056361-1-richard.henderson@linaro.org ("[PATCH 00/11] tcg: Cleanups after disallowing 64-on-32") Introduce a new general-purpose constraint which maps 0 to TCG_REG_ZERO, if defined. This differs from existing constant constraints in that const_arg[*] is recorded as false, indicating that the value is in a register. This doesn't make much difference to the current tree, but as a prelude to [1], where small output functions are categorized by register vs immediate arguments, then this provides a way to send a constant zero as a register argument. r~ [1] https://patchew.org/QEMU/20250107080112.1175095-1-richard.henderson@linaro.org/ Richard Henderson (6): tcg: Introduce the 'z' constraint for a hardware zero register tcg/aarch64: Use 'z' constraint tcg/loongarch64: Use 'z' constraint tcg/mips: Use 'z' constraint tcg/riscv: Use 'z' constraint tcg/sparc64: Use 'z' constraint include/tcg/tcg.h | 3 +- tcg/aarch64/tcg-target-con-set.h | 12 ++++---- tcg/aarch64/tcg-target.h | 2 ++ tcg/loongarch64/tcg-target-con-set.h | 15 +++++---- tcg/loongarch64/tcg-target-con-str.h | 1 - tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target-con-set.h | 26 ++++++++-------- tcg/mips/tcg-target-con-str.h | 1 - tcg/mips/tcg-target.h | 2 ++ tcg/riscv/tcg-target-con-set.h | 10 +++--- tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.h | 2 ++ tcg/sparc64/tcg-target-con-set.h | 12 ++++---- tcg/sparc64/tcg-target-con-str.h | 1 - tcg/sparc64/tcg-target.h | 3 +- tcg/tcg.c | 29 +++++++++++++----- docs/devel/tcg-ops.rst | 4 ++- tcg/aarch64/tcg-target.c.inc | 46 ++++++++++++---------------- tcg/loongarch64/tcg-target.c.inc | 32 +++++++++---------- tcg/mips/tcg-target.c.inc | 44 +++++++++++--------------- tcg/riscv/tcg-target.c.inc | 12 ++++---- tcg/sparc64/tcg-target.c.inc | 12 ++++---- 22 files changed, 138 insertions(+), 134 deletions(-) -- 2.43.0