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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Rob Herring" <robh@kernel.org>,
	"Igor Mitsyanko" <i.mitsyanko@gmail.com>,
	qemu-arm@nongnu.org, "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v2 7/8] hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs
Date: Wed, 12 Feb 2025 16:43:32 +0100	[thread overview]
Message-ID: <20250212154333.28644-8-philmd@linaro.org> (raw)
In-Reply-To: <20250212154333.28644-1-philmd@linaro.org>

When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit  528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Caldexa Highbank board however expects a fixed set of 128
interrupts (see the fixed IRQ length when this board was added in
commit 2488514cef2 ("arm: SoC model for Calxeda Highbank"). Add the
GIC_EXT_IRQS definition (with a comment) to make that explicit.

Except explicitly setting a property value to its same implicit
value, there is no logical change intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/highbank.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 495704d9726..0f3c207d548 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -45,7 +45,7 @@
 #define MVBAR_ADDR              0x200
 #define BOARD_SETUP_ADDR        (MVBAR_ADDR + 8 * sizeof(uint32_t))
 
-#define NIRQ_GIC                160
+#define GIC_EXT_IRQS            128 /* EnergyCore ECX-1000 & ECX-2000 */
 
 /* Board init.  */
 
@@ -180,7 +180,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
 {
     DeviceState *dev = NULL;
     SysBusDevice *busdev;
-    qemu_irq pic[128];
+    qemu_irq pic[GIC_EXT_IRQS];
     int n;
     unsigned int smp_cpus = machine->smp.cpus;
     qemu_irq cpu_irq[4];
@@ -260,7 +260,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
         break;
     }
     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
-    qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
+    qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL);
     busdev = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(busdev, &error_fatal);
     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
@@ -271,7 +271,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
         sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
     }
 
-    for (n = 0; n < 128; n++) {
+    for (n = 0; n < GIC_EXT_IRQS; n++) {
         pic[n] = qdev_get_gpio_in(dev, n);
     }
 
-- 
2.47.1



  parent reply	other threads:[~2025-02-12 15:44 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-12 15:43 [PATCH v2 0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore Philippe Mathieu-Daudé
2025-02-12 15:43 ` [PATCH v2 1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Philippe Mathieu-Daudé
2025-02-12 17:57   ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 2/8] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs Philippe Mathieu-Daudé
2025-02-12 17:59   ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 3/8] hw/arm/realview: " Philippe Mathieu-Daudé
2025-02-12 18:01   ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 4/8] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Philippe Mathieu-Daudé
2025-02-12 18:02   ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 5/8] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs Philippe Mathieu-Daudé
2025-02-12 18:10   ` Richard Henderson
2025-02-12 15:43 ` [PATCH v2 6/8] hw/arm/vexpress: " Philippe Mathieu-Daudé
2025-02-12 18:12   ` Richard Henderson
2025-02-12 15:43 ` Philippe Mathieu-Daudé [this message]
2025-02-12 18:12   ` [PATCH v2 7/8] hw/arm/highbank: Specify explicitly the GIC has 128 " Richard Henderson
2025-02-12 15:43 ` [PATCH v2 8/8] hw/cpu/arm_mpcore: Remove default values for GIC " Philippe Mathieu-Daudé
2025-02-12 18:13   ` Richard Henderson
2025-02-17 15:43 ` [PATCH v2 0/8] hw/arm: Explicit number of GIC external IRQs for Cortex A9/A15 MPCore Peter Maydell

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