From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v3 06/28] hw/intc/aspeed: Support different memory region ops
Date: Thu, 13 Feb 2025 11:35:09 +0800 [thread overview]
Message-ID: <20250213033531.3367697-7-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250213033531.3367697-1-jamin_lin@aspeedtech.com>
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTCIO (IO Die) model, introduces a new "reg_ops" class
attribute. This allows setting different memory region operations to support
different INTC models.
Will introduce "aspeed_intcio_read" and "aspeed_intcio_write" callback
functions are used for INTCIO.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/intc/aspeed_intc.c | 5 ++++-
include/hw/intc/aspeed_intc.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 91d8edb261..cc2426fbac 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -340,7 +340,7 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->iomem_container);
- memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_intc_ops, s,
+ memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s,
TYPE_ASPEED_INTC ".regs", aic->reg_size);
memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);
@@ -358,11 +358,14 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
static void aspeed_intc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
dc->desc = "ASPEED INTC Controller";
dc->realize = aspeed_intc_realize;
device_class_set_legacy_reset(dc, aspeed_intc_reset);
dc->vmsd = NULL;
+
+ aic->reg_ops = &aspeed_intc_ops;
}
static const TypeInfo aspeed_intc_info = {
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index ecaeb15aea..749d7c55be 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -43,6 +43,7 @@ struct AspeedINTCClass {
uint32_t num_ints;
uint64_t mem_size;
uint64_t reg_size;
+ const MemoryRegionOps *reg_ops;
};
#endif /* ASPEED_INTC_H */
--
2.34.1
next prev parent reply other threads:[~2025-02-13 3:39 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-13 3:35 [PATCH v3 00/28] Support AST2700 A1 Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 01/28] hw/intc/aspeed: Support setting different memory and register size Jamin Lin via
2025-02-18 5:33 ` Cédric Le Goater
2025-02-20 5:45 ` Jamin Lin
2025-02-21 15:15 ` Cédric Le Goater
2025-02-26 3:40 ` Jamin Lin
2025-02-27 9:57 ` Cédric Le Goater
2025-03-03 2:52 ` Jamin Lin
2025-02-13 3:35 ` [PATCH v3 02/28] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-02-18 5:36 ` Cédric Le Goater
2025-02-20 3:24 ` Jamin Lin
2025-02-13 3:35 ` [PATCH v3 03/28] hw/intc/aspeed: Add object type name to trace events for better debugging Jamin Lin via
2025-02-18 5:43 ` Cédric Le Goater
2025-02-13 3:35 ` [PATCH v3 04/28] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
2025-02-18 5:47 ` Cédric Le Goater
2025-02-21 2:23 ` Jamin Lin
2025-02-21 14:04 ` Cédric Le Goater
2025-02-13 3:35 ` [PATCH v3 05/28] hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number Jamin Lin via
2025-02-18 5:48 ` Cédric Le Goater
2025-02-13 3:35 ` Jamin Lin via [this message]
2025-02-18 5:48 ` [PATCH v3 06/28] hw/intc/aspeed: Support different memory region ops Cédric Le Goater
2025-02-13 3:35 ` [PATCH v3 07/28] hw/intc/aspeed: Rename num_ints to num_inpins for clarity Jamin Lin via
2025-02-18 5:49 ` Cédric Le Goater
2025-02-13 3:35 ` [PATCH v3 08/28] hw/intc/aspeed: Add support for multiple output pins in INTC Jamin Lin via
2025-02-18 5:53 ` Cédric Le Goater
2025-02-21 1:31 ` Jamin Lin
2025-02-13 3:35 ` [PATCH v3 09/28] hw/intc/aspeed: Refactor INTC to support separate input and output pin indices Jamin Lin via
2025-02-18 6:20 ` Cédric Le Goater
2025-02-13 3:35 ` [PATCH v3 10/28] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 11/28] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-02-18 9:17 ` Cédric Le Goater
2025-02-20 3:14 ` Jamin Lin
2025-02-13 3:35 ` [PATCH v3 12/28] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 13/28] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller Jamin Lin via
2025-02-18 9:15 ` Cédric Le Goater
2025-02-20 5:57 ` Jamin Lin
2025-02-13 3:35 ` [PATCH v3 14/28] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-02-18 6:35 ` Cédric Le Goater
2025-02-13 3:35 ` [PATCH v3 15/28] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700 Jamin Lin via
2025-02-18 6:47 ` Cédric Le Goater
2025-02-26 6:38 ` Jamin Lin
2025-02-27 9:33 ` Cédric Le Goater
2025-03-03 2:51 ` Jamin Lin
2025-02-13 3:35 ` [PATCH v3 16/28] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 17/28] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 18/28] hw/arm/aspeed: Add SoC and Machine Support " Jamin Lin via
2025-02-18 6:49 ` Cédric Le Goater
2025-02-21 1:37 ` Jamin Lin
2025-02-13 3:35 ` [PATCH v3 19/28] hw/misc/aspeed_hace: Fix coding style Jamin Lin via
2025-02-18 6:21 ` Cédric Le Goater
2025-02-13 3:35 ` [PATCH v3 20/28] hw/misc/aspeed_hace: Add AST2700 support Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 21/28] hw/misc/aspeed_hace: Fix boot issue in the Crypto Manager Self Test Jamin Lin via
2025-02-18 6:26 ` Cédric Le Goater
2025-02-21 5:43 ` Jamin Lin
2025-02-21 6:55 ` Jamin Lin
2025-02-21 13:53 ` Cédric Le Goater
2025-02-24 5:10 ` Jamin Lin
2025-02-13 3:35 ` [PATCH v3 22/28] hw/arm/aspeed_ast27x0: Add HACE support for AST2700 Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 23/28] test/functional/aspeed: Introduce new function to fetch assets Jamin Lin via
2025-02-18 6:30 ` Cédric Le Goater
2025-02-21 1:35 ` Jamin Lin
2025-02-13 3:35 ` [PATCH v3 24/28] tests/functional/aspeed: Introduce start_ast2700_test API and update hwmon path Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 25/28] tests/functional/aspeed: Update test ASPEED SDK v09.05 Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 26/28] tests/functional/aspeed: Renamed test case and machine for AST2700 A0 Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 27/28] tests/functional/aspeed: Add test case for AST2700 A1 Jamin Lin via
2025-02-13 3:35 ` [PATCH v3 28/28] docs/specs: add aspeed-intc Jamin Lin via
2025-02-18 9:25 ` [PATCH v3 00/28] Support AST2700 A1 Cédric Le Goater
2025-02-20 5:11 ` Jamin Lin
2025-02-21 17:24 ` Cédric Le Goater
2025-02-25 8:02 ` Jamin Lin
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