From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL v2 12/27] target/loongarch: Use VADDR_PRIx for logging pc_next
Date: Mon, 17 Feb 2025 11:29:53 -0800 [thread overview]
Message-ID: <20250217193009.2873875-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250217193009.2873875-1-richard.henderson@linaro.org>
DisasContextBase.pc_next has type vaddr; use the correct log format.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/tcg/translate.c | 2 +-
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index 3480f54c71..e59e4ed25b 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -289,7 +289,7 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
if (!decode(ctx, ctx->opcode)) {
qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. "
- TARGET_FMT_lx ": 0x%x\n",
+ "0x%" VADDR_PRIx ": 0x%x\n",
ctx->base.pc_next, ctx->opcode);
generate_exception(ctx, EXCCODE_INE);
}
diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
index 974bc2a70f..3d70d75941 100644
--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
@@ -56,7 +56,7 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a,
if (a->rd != 0 && (a->rj == a->rd || a->rk == a->rd)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Warning: source register overlaps destination register"
- "in atomic insn at pc=0x" TARGET_FMT_lx "\n",
+ "in atomic insn at pc=0x%" VADDR_PRIx "\n",
ctx->base.pc_next - 4);
return false;
}
--
2.43.0
next prev parent reply other threads:[~2025-02-17 19:34 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 19:29 [PULL v2 00/27] tcg patch queue Richard Henderson
2025-02-17 19:29 ` [PULL v2 01/27] tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS Richard Henderson
2025-02-17 19:29 ` [PULL v2 02/27] tcg: Remove TCG_OVERSIZED_GUEST Richard Henderson
2025-02-17 19:29 ` [PULL v2 03/27] tcg: Drop support for two address registers in gen_ldst Richard Henderson
2025-02-17 19:29 ` [PULL v2 04/27] tcg: Merge INDEX_op_qemu_*_{a32,a64}_* Richard Henderson
2025-02-17 19:29 ` [PULL v2 05/27] tcg/arm: Drop addrhi from prepare_host_addr Richard Henderson
2025-02-17 19:29 ` [PULL v2 06/27] tcg/i386: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 07/27] tcg/mips: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 08/27] tcg/ppc: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 09/27] tcg: Replace addr{lo, hi}_reg with addr_reg in TCGLabelQemuLdst Richard Henderson
2025-02-17 19:29 ` [PULL v2 10/27] plugins: Fix qemu_plugin_read_memory_vaddr parameters Richard Henderson
2025-02-17 19:29 ` [PULL v2 11/27] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page Richard Henderson
2025-02-17 19:29 ` Richard Henderson [this message]
2025-02-17 19:29 ` [PULL v2 13/27] include/exec: Change vaddr to uintptr_t Richard Henderson
2025-02-17 19:29 ` [PULL v2 14/27] include/exec: Use uintptr_t in CPUTLBEntry Richard Henderson
2025-02-17 19:29 ` [PULL v2 15/27] tcg: Introduce the 'z' constraint for a hardware zero register Richard Henderson
2025-02-17 19:29 ` [PULL v2 16/27] tcg/aarch64: Use 'z' constraint Richard Henderson
2025-02-17 19:29 ` [PULL v2 17/27] tcg/loongarch64: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 18/27] tcg/mips: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 19/27] tcg/riscv: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 20/27] tcg/sparc64: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 21/27] elfload: Fix alignment when unmapping excess reservation Richard Henderson
2025-02-17 19:30 ` [PULL v2 22/27] linux-user: Move TARGET_SA_RESTORER out of generic/signal.h Richard Henderson
2025-02-17 19:30 ` [PULL v2 23/27] target/sparc: Fix register selection for all F*TOx and FxTO* instructions Richard Henderson
2025-02-17 19:30 ` [PULL v2 24/27] target/sparc: Fix gdbstub incorrectly handling registers f32-f62 Richard Henderson
2025-02-17 19:30 ` [PULL v2 25/27] target/sparc: fake UltraSPARC T1 PCR and PIC registers Richard Henderson
2025-02-17 19:30 ` [PULL v2 26/27] tcg/i386: Use tcg_{high, unsigned}_cond in tcg_out_brcond2 Richard Henderson
2025-02-17 19:30 ` [PULL v2 27/27] tcg: Remove TCG_TARGET_HAS_{br, set}cond2 from riscv and loongarch64 Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250217193009.2873875-13-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).