From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL v2 14/27] include/exec: Use uintptr_t in CPUTLBEntry
Date: Mon, 17 Feb 2025 11:29:55 -0800 [thread overview]
Message-ID: <20250217193009.2873875-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250217193009.2873875-1-richard.henderson@linaro.org>
Since we no longer support 64-bit guests on 32-bit hosts,
we can use a 32-bit type on a 32-bit host. This shrinks
the size of the structure to 16 bytes on a 32-bit host.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/tlb-common.h | 10 +++++-----
accel/tcg/cputlb.c | 21 ++++-----------------
tcg/arm/tcg-target.c.inc | 1 -
tcg/mips/tcg-target.c.inc | 12 +++++-------
tcg/ppc/tcg-target.c.inc | 21 +++++----------------
5 files changed, 19 insertions(+), 46 deletions(-)
diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h
index dc5a5faa0b..03b5a8ffc7 100644
--- a/include/exec/tlb-common.h
+++ b/include/exec/tlb-common.h
@@ -19,14 +19,14 @@
#ifndef EXEC_TLB_COMMON_H
#define EXEC_TLB_COMMON_H 1
-#define CPU_TLB_ENTRY_BITS 5
+#define CPU_TLB_ENTRY_BITS (HOST_LONG_BITS == 32 ? 4 : 5)
/* Minimalized TLB entry for use by TCG fast path. */
typedef union CPUTLBEntry {
struct {
- uint64_t addr_read;
- uint64_t addr_write;
- uint64_t addr_code;
+ uintptr_t addr_read;
+ uintptr_t addr_write;
+ uintptr_t addr_code;
/*
* Addend to virtual address to get host address. IO accesses
* use the corresponding iotlb value.
@@ -37,7 +37,7 @@ typedef union CPUTLBEntry {
* Padding to get a power of two size, as well as index
* access to addr_{read,write,code}.
*/
- uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)];
+ uintptr_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uintptr_t)];
} CPUTLBEntry;
QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 75d075d044..ad158050a1 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -104,22 +104,15 @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
{
/* Do not rearrange the CPUTLBEntry structure members. */
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=
- MMU_DATA_LOAD * sizeof(uint64_t));
+ MMU_DATA_LOAD * sizeof(uintptr_t));
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=
- MMU_DATA_STORE * sizeof(uint64_t));
+ MMU_DATA_STORE * sizeof(uintptr_t));
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
- MMU_INST_FETCH * sizeof(uint64_t));
+ MMU_INST_FETCH * sizeof(uintptr_t));
-#if TARGET_LONG_BITS == 32
- /* Use qatomic_read, in case of addr_write; only care about low bits. */
- const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
- ptr += HOST_BIG_ENDIAN;
- return qatomic_read(ptr);
-#else
- const uint64_t *ptr = &entry->addr_idx[access_type];
+ const uintptr_t *ptr = &entry->addr_idx[access_type];
/* ofs might correspond to .addr_write, so use qatomic_read */
return qatomic_read(ptr);
-#endif
}
static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry)
@@ -899,14 +892,8 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
addr &= TARGET_PAGE_MASK;
addr += tlb_entry->addend;
if ((addr - start) < length) {
-#if TARGET_LONG_BITS == 32
- uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
- ptr_write += HOST_BIG_ENDIAN;
- qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
-#else
qatomic_set(&tlb_entry->addr_write,
tlb_entry->addr_write | TLB_NOTDIRTY);
-#endif
}
}
}
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 83f6eb6099..cec3d761d4 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1500,7 +1500,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
* Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
* Load the tlb comparator into R2 and the fast path addend into R1.
*/
- QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
if (cmp_off == 0) {
tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
} else {
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index d744b853cd..14b3cb1eba 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1262,18 +1262,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
/* Add the tlb_table pointer, creating the CPUTLBEntry address. */
tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
- if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
- /* Load the (low half) tlb comparator. */
+ /* Load the tlb comparator. */
+ if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3,
cmp_off + HOST_BIG_ENDIAN * 4);
} else {
- tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off);
+ tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off);
}
- if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
- /* Load the tlb addend for the fast path. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
- }
+ /* Load the tlb addend for the fast path. */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
/*
* Mask the page bits, keeping the alignment bits to compare against.
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 2d16807ec7..822925a19b 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2490,27 +2490,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
/*
- * Load the (low part) TLB comparator into TMP2.
+ * Load the TLB comparator into TMP2.
* For 64-bit host, always load the entire 64-bit slot for simplicity.
* We will ignore the high bits with tcg_out_cmp(..., addr_type).
*/
- if (TCG_TARGET_REG_BITS == 64) {
- if (cmp_off == 0) {
- tcg_out32(s, LDUX | TAB(TCG_REG_TMP2,
- TCG_REG_TMP1, TCG_REG_TMP2));
- } else {
- tcg_out32(s, ADD | TAB(TCG_REG_TMP1,
- TCG_REG_TMP1, TCG_REG_TMP2));
- tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2,
- TCG_REG_TMP1, cmp_off);
- }
- } else if (cmp_off == 0 && !HOST_BIG_ENDIAN) {
- tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2,
- TCG_REG_TMP1, TCG_REG_TMP2));
+ if (cmp_off == 0) {
+ tcg_out32(s, (TCG_TARGET_REG_BITS == 64 ? LDUX : LWZUX)
+ | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2));
} else {
tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
- cmp_off + 4 * HOST_BIG_ENDIAN);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off);
}
/*
--
2.43.0
next prev parent reply other threads:[~2025-02-17 19:35 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 19:29 [PULL v2 00/27] tcg patch queue Richard Henderson
2025-02-17 19:29 ` [PULL v2 01/27] tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS Richard Henderson
2025-02-17 19:29 ` [PULL v2 02/27] tcg: Remove TCG_OVERSIZED_GUEST Richard Henderson
2025-02-17 19:29 ` [PULL v2 03/27] tcg: Drop support for two address registers in gen_ldst Richard Henderson
2025-02-17 19:29 ` [PULL v2 04/27] tcg: Merge INDEX_op_qemu_*_{a32,a64}_* Richard Henderson
2025-02-17 19:29 ` [PULL v2 05/27] tcg/arm: Drop addrhi from prepare_host_addr Richard Henderson
2025-02-17 19:29 ` [PULL v2 06/27] tcg/i386: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 07/27] tcg/mips: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 08/27] tcg/ppc: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 09/27] tcg: Replace addr{lo, hi}_reg with addr_reg in TCGLabelQemuLdst Richard Henderson
2025-02-17 19:29 ` [PULL v2 10/27] plugins: Fix qemu_plugin_read_memory_vaddr parameters Richard Henderson
2025-02-17 19:29 ` [PULL v2 11/27] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page Richard Henderson
2025-02-17 19:29 ` [PULL v2 12/27] target/loongarch: Use VADDR_PRIx for logging pc_next Richard Henderson
2025-02-17 19:29 ` [PULL v2 13/27] include/exec: Change vaddr to uintptr_t Richard Henderson
2025-02-17 19:29 ` Richard Henderson [this message]
2025-02-17 19:29 ` [PULL v2 15/27] tcg: Introduce the 'z' constraint for a hardware zero register Richard Henderson
2025-02-17 19:29 ` [PULL v2 16/27] tcg/aarch64: Use 'z' constraint Richard Henderson
2025-02-17 19:29 ` [PULL v2 17/27] tcg/loongarch64: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 18/27] tcg/mips: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 19/27] tcg/riscv: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 20/27] tcg/sparc64: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 21/27] elfload: Fix alignment when unmapping excess reservation Richard Henderson
2025-02-17 19:30 ` [PULL v2 22/27] linux-user: Move TARGET_SA_RESTORER out of generic/signal.h Richard Henderson
2025-02-17 19:30 ` [PULL v2 23/27] target/sparc: Fix register selection for all F*TOx and FxTO* instructions Richard Henderson
2025-02-17 19:30 ` [PULL v2 24/27] target/sparc: Fix gdbstub incorrectly handling registers f32-f62 Richard Henderson
2025-02-17 19:30 ` [PULL v2 25/27] target/sparc: fake UltraSPARC T1 PCR and PIC registers Richard Henderson
2025-02-17 19:30 ` [PULL v2 26/27] tcg/i386: Use tcg_{high, unsigned}_cond in tcg_out_brcond2 Richard Henderson
2025-02-17 19:30 ` [PULL v2 27/27] tcg: Remove TCG_TARGET_HAS_{br, set}cond2 from riscv and loongarch64 Richard Henderson
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