From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL v2 06/27] tcg/i386: Drop addrhi from prepare_host_addr
Date: Mon, 17 Feb 2025 11:29:47 -0800 [thread overview]
Message-ID: <20250217193009.2873875-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250217193009.2873875-1-richard.henderson@linaro.org>
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 56 ++++++++++++++-------------------------
1 file changed, 20 insertions(+), 36 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index ca6e8abc57..b33fe7fe23 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2169,8 +2169,7 @@ static inline int setup_guest_base_seg(void)
* is required and fill in @h with the host address for the fast path.
*/
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
- TCGReg addrlo, TCGReg addrhi,
- MemOpIdx oi, bool is_ld)
+ TCGReg addr, MemOpIdx oi, bool is_ld)
{
TCGLabelQemuLdst *ldst = NULL;
MemOp opc = get_memop(oi);
@@ -2184,7 +2183,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
} else {
*h = x86_guest_base;
}
- h->base = addrlo;
+ h->base = addr;
h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
a_mask = (1 << h->aa.align) - 1;
@@ -2202,8 +2201,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s);
ldst->is_ld = is_ld;
ldst->oi = oi;
- ldst->addrlo_reg = addrlo;
- ldst->addrhi_reg = addrhi;
+ ldst->addrlo_reg = addr;
if (TCG_TARGET_REG_BITS == 64) {
ttype = s->addr_type;
@@ -2217,7 +2215,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
}
}
- tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
+ tcg_out_mov(s, tlbtype, TCG_REG_L0, addr);
tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
s->page_bits - CPU_TLB_ENTRY_BITS);
@@ -2233,10 +2231,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
* check that we don't cross pages for the complete access.
*/
if (a_mask >= s_mask) {
- tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
+ tcg_out_mov(s, ttype, TCG_REG_L1, addr);
} else {
tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
- addrlo, s_mask - a_mask);
+ addr, s_mask - a_mask);
}
tlb_mask = s->page_mask | a_mask;
tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
@@ -2250,17 +2248,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst->label_ptr[0] = s->code_ptr;
s->code_ptr += 4;
- if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
- /* cmp 4(TCG_REG_L0), addrhi */
- tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi,
- TCG_REG_L0, cmp_ofs + 4);
-
- /* jne slow_path */
- tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
- ldst->label_ptr[1] = s->code_ptr;
- s->code_ptr += 4;
- }
-
/* TLB Hit. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
offsetof(CPUTLBEntry, addend));
@@ -2270,11 +2257,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s);
ldst->is_ld = is_ld;
ldst->oi = oi;
- ldst->addrlo_reg = addrlo;
- ldst->addrhi_reg = addrhi;
+ ldst->addrlo_reg = addr;
/* jne slow_path */
- jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addrlo, a_mask, true, false);
+ jcc = tcg_out_cmp(s, TCG_COND_TSTNE, addr, a_mask, true, false);
tcg_out_opc(s, OPC_JCC_long + jcc, 0, 0, 0);
ldst->label_ptr[0] = s->code_ptr;
s->code_ptr += 4;
@@ -2446,13 +2432,12 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
}
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addrhi,
- MemOpIdx oi, TCGType data_type)
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
{
TCGLabelQemuLdst *ldst;
HostAddress h;
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
+ ldst = prepare_host_addr(s, &h, addr, oi, true);
tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi));
if (ldst) {
@@ -2574,13 +2559,12 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
}
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addrhi,
- MemOpIdx oi, TCGType data_type)
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
{
TCGLabelQemuLdst *ldst;
HostAddress h;
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
+ ldst = prepare_host_addr(s, &h, addr, oi, false);
tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi));
if (ldst) {
@@ -2880,34 +2864,34 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
break;
case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
+ tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_ld_i64:
if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
+ tcg_out_qemu_ld(s, a0, -1, a1, a2, TCG_TYPE_I64);
} else {
- tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_ld_i128:
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
- tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I128);
break;
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st8_i32:
- tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32);
+ tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_i64:
if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64);
+ tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I64);
} else {
- tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64);
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_st_i128:
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
- tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128);
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I128);
break;
OP_32_64(mulu2):
--
2.43.0
next prev parent reply other threads:[~2025-02-17 19:30 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 19:29 [PULL v2 00/27] tcg patch queue Richard Henderson
2025-02-17 19:29 ` [PULL v2 01/27] tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS Richard Henderson
2025-02-17 19:29 ` [PULL v2 02/27] tcg: Remove TCG_OVERSIZED_GUEST Richard Henderson
2025-02-17 19:29 ` [PULL v2 03/27] tcg: Drop support for two address registers in gen_ldst Richard Henderson
2025-02-17 19:29 ` [PULL v2 04/27] tcg: Merge INDEX_op_qemu_*_{a32,a64}_* Richard Henderson
2025-02-17 19:29 ` [PULL v2 05/27] tcg/arm: Drop addrhi from prepare_host_addr Richard Henderson
2025-02-17 19:29 ` Richard Henderson [this message]
2025-02-17 19:29 ` [PULL v2 07/27] tcg/mips: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 08/27] tcg/ppc: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 09/27] tcg: Replace addr{lo, hi}_reg with addr_reg in TCGLabelQemuLdst Richard Henderson
2025-02-17 19:29 ` [PULL v2 10/27] plugins: Fix qemu_plugin_read_memory_vaddr parameters Richard Henderson
2025-02-17 19:29 ` [PULL v2 11/27] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page Richard Henderson
2025-02-17 19:29 ` [PULL v2 12/27] target/loongarch: Use VADDR_PRIx for logging pc_next Richard Henderson
2025-02-17 19:29 ` [PULL v2 13/27] include/exec: Change vaddr to uintptr_t Richard Henderson
2025-02-17 19:29 ` [PULL v2 14/27] include/exec: Use uintptr_t in CPUTLBEntry Richard Henderson
2025-02-17 19:29 ` [PULL v2 15/27] tcg: Introduce the 'z' constraint for a hardware zero register Richard Henderson
2025-02-17 19:29 ` [PULL v2 16/27] tcg/aarch64: Use 'z' constraint Richard Henderson
2025-02-17 19:29 ` [PULL v2 17/27] tcg/loongarch64: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 18/27] tcg/mips: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 19/27] tcg/riscv: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 20/27] tcg/sparc64: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 21/27] elfload: Fix alignment when unmapping excess reservation Richard Henderson
2025-02-17 19:30 ` [PULL v2 22/27] linux-user: Move TARGET_SA_RESTORER out of generic/signal.h Richard Henderson
2025-02-17 19:30 ` [PULL v2 23/27] target/sparc: Fix register selection for all F*TOx and FxTO* instructions Richard Henderson
2025-02-17 19:30 ` [PULL v2 24/27] target/sparc: Fix gdbstub incorrectly handling registers f32-f62 Richard Henderson
2025-02-17 19:30 ` [PULL v2 25/27] target/sparc: fake UltraSPARC T1 PCR and PIC registers Richard Henderson
2025-02-17 19:30 ` [PULL v2 26/27] tcg/i386: Use tcg_{high, unsigned}_cond in tcg_out_brcond2 Richard Henderson
2025-02-17 19:30 ` [PULL v2 27/27] tcg: Remove TCG_TARGET_HAS_{br, set}cond2 from riscv and loongarch64 Richard Henderson
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