From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL v2 07/27] tcg/mips: Drop addrhi from prepare_host_addr
Date: Mon, 17 Feb 2025 11:29:48 -0800 [thread overview]
Message-ID: <20250217193009.2873875-8-richard.henderson@linaro.org> (raw)
In-Reply-To: <20250217193009.2873875-1-richard.henderson@linaro.org>
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 62 ++++++++++++++-------------------------
1 file changed, 22 insertions(+), 40 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index b1d512ca2a..153ce1f3c3 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1217,8 +1217,7 @@ bool tcg_target_has_memory_bswap(MemOp memop)
* is required and fill in @h with the host address for the fast path.
*/
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
- TCGReg addrlo, TCGReg addrhi,
- MemOpIdx oi, bool is_ld)
+ TCGReg addr, MemOpIdx oi, bool is_ld)
{
TCGType addr_type = s->addr_type;
TCGLabelQemuLdst *ldst = NULL;
@@ -1245,8 +1244,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s);
ldst->is_ld = is_ld;
ldst->oi = oi;
- ldst->addrlo_reg = addrlo;
- ldst->addrhi_reg = addrhi;
+ ldst->addrlo_reg = addr;
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
@@ -1254,11 +1252,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
/* Extract the TLB index from the address into TMP3. */
if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo,
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr,
s->page_bits - CPU_TLB_ENTRY_BITS);
} else {
- tcg_out_dsrl(s, TCG_TMP3, addrlo,
- s->page_bits - CPU_TLB_ENTRY_BITS);
+ tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS);
}
tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
@@ -1288,48 +1285,35 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32
|| addr_type == TCG_TYPE_I32
? OPC_ADDIU : OPC_DADDIU),
- TCG_TMP2, addrlo, s_mask - a_mask);
+ TCG_TMP2, addr, s_mask - a_mask);
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
} else {
- tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
+ tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr);
}
/* Zero extend a 32-bit guest address for a 64-bit host. */
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
- tcg_out_ext32u(s, TCG_TMP2, addrlo);
- addrlo = TCG_TMP2;
+ tcg_out_ext32u(s, TCG_TMP2, addr);
+ addr = TCG_TMP2;
}
ldst->label_ptr[0] = s->code_ptr;
tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
- /* Load and test the high half tlb comparator. */
- if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
- /* delay slot */
- tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
-
- /* Load the tlb addend for the fast path. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
-
- ldst->label_ptr[1] = s->code_ptr;
- tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
- }
-
/* delay slot */
base = TCG_TMP3;
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr);
} else {
if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
ldst = new_ldst_label(s);
ldst->is_ld = is_ld;
ldst->oi = oi;
- ldst->addrlo_reg = addrlo;
- ldst->addrhi_reg = addrhi;
+ ldst->addrlo_reg = addr;
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
tcg_debug_assert(a_bits < 16);
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask);
ldst->label_ptr[0] = s->code_ptr;
if (use_mips32r6_instructions) {
@@ -1340,7 +1324,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
}
}
- base = addrlo;
+ base = addr;
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
tcg_out_ext32u(s, TCG_REG_A0, base);
base = TCG_REG_A0;
@@ -1460,14 +1444,13 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
}
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addrhi,
- MemOpIdx oi, TCGType data_type)
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
{
MemOp opc = get_memop(oi);
TCGLabelQemuLdst *ldst;
HostAddress h;
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
+ ldst = prepare_host_addr(s, &h, addr, oi, true);
if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
@@ -1547,14 +1530,13 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
}
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
- TCGReg addrlo, TCGReg addrhi,
- MemOpIdx oi, TCGType data_type)
+ TCGReg addr, MemOpIdx oi, TCGType data_type)
{
MemOp opc = get_memop(oi);
TCGLabelQemuLdst *ldst;
HostAddress h;
- ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
+ ldst = prepare_host_addr(s, &h, addr, oi, false);
if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
@@ -2096,24 +2078,24 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
break;
case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
+ tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_ld_i64:
if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
+ tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64);
} else {
- tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64);
}
break;
case INDEX_op_qemu_st_i32:
- tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
+ tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_i64:
if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
+ tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64);
} else {
- tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
+ tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64);
}
break;
--
2.43.0
next prev parent reply other threads:[~2025-02-17 19:33 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 19:29 [PULL v2 00/27] tcg patch queue Richard Henderson
2025-02-17 19:29 ` [PULL v2 01/27] tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS Richard Henderson
2025-02-17 19:29 ` [PULL v2 02/27] tcg: Remove TCG_OVERSIZED_GUEST Richard Henderson
2025-02-17 19:29 ` [PULL v2 03/27] tcg: Drop support for two address registers in gen_ldst Richard Henderson
2025-02-17 19:29 ` [PULL v2 04/27] tcg: Merge INDEX_op_qemu_*_{a32,a64}_* Richard Henderson
2025-02-17 19:29 ` [PULL v2 05/27] tcg/arm: Drop addrhi from prepare_host_addr Richard Henderson
2025-02-17 19:29 ` [PULL v2 06/27] tcg/i386: " Richard Henderson
2025-02-17 19:29 ` Richard Henderson [this message]
2025-02-17 19:29 ` [PULL v2 08/27] tcg/ppc: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 09/27] tcg: Replace addr{lo, hi}_reg with addr_reg in TCGLabelQemuLdst Richard Henderson
2025-02-17 19:29 ` [PULL v2 10/27] plugins: Fix qemu_plugin_read_memory_vaddr parameters Richard Henderson
2025-02-17 19:29 ` [PULL v2 11/27] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page Richard Henderson
2025-02-17 19:29 ` [PULL v2 12/27] target/loongarch: Use VADDR_PRIx for logging pc_next Richard Henderson
2025-02-17 19:29 ` [PULL v2 13/27] include/exec: Change vaddr to uintptr_t Richard Henderson
2025-02-17 19:29 ` [PULL v2 14/27] include/exec: Use uintptr_t in CPUTLBEntry Richard Henderson
2025-02-17 19:29 ` [PULL v2 15/27] tcg: Introduce the 'z' constraint for a hardware zero register Richard Henderson
2025-02-17 19:29 ` [PULL v2 16/27] tcg/aarch64: Use 'z' constraint Richard Henderson
2025-02-17 19:29 ` [PULL v2 17/27] tcg/loongarch64: " Richard Henderson
2025-02-17 19:29 ` [PULL v2 18/27] tcg/mips: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 19/27] tcg/riscv: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 20/27] tcg/sparc64: " Richard Henderson
2025-02-17 19:30 ` [PULL v2 21/27] elfload: Fix alignment when unmapping excess reservation Richard Henderson
2025-02-17 19:30 ` [PULL v2 22/27] linux-user: Move TARGET_SA_RESTORER out of generic/signal.h Richard Henderson
2025-02-17 19:30 ` [PULL v2 23/27] target/sparc: Fix register selection for all F*TOx and FxTO* instructions Richard Henderson
2025-02-17 19:30 ` [PULL v2 24/27] target/sparc: Fix gdbstub incorrectly handling registers f32-f62 Richard Henderson
2025-02-17 19:30 ` [PULL v2 25/27] target/sparc: fake UltraSPARC T1 PCR and PIC registers Richard Henderson
2025-02-17 19:30 ` [PULL v2 26/27] tcg/i386: Use tcg_{high, unsigned}_cond in tcg_out_brcond2 Richard Henderson
2025-02-17 19:30 ` [PULL v2 27/27] tcg: Remove TCG_TARGET_HAS_{br, set}cond2 from riscv and loongarch64 Richard Henderson
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