From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH 1/7] hw/riscv: acpi: only create RHCT MMU entry for supported types
Date: Tue, 18 Feb 2025 17:57:51 +0100 [thread overview]
Message-ID: <20250218165757.554178-2-pbonzini@redhat.com> (raw)
In-Reply-To: <20250218165757.554178-1-pbonzini@redhat.com>
Do not create the RHCT MMU type entry for RV32 CPUs, since it
only has definitions for SV39/SV48/SV57. Likewise, check that
satp_mode_max_from_map() will actually return a valid value, skipping
the MMU type entry if all MMU types were disabled on the command line.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/riscv/virt-acpi-build.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 1ad68005085..2b374ebacbf 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -262,6 +262,7 @@ static void build_rhct(GArray *table_data,
RISCVCPU *cpu = &s->soc[0].harts[0];
uint32_t mmu_offset = 0;
uint8_t satp_mode_max;
+ bool rv32 = riscv_cpu_is_32bit(cpu);
g_autofree char *isa = NULL;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -281,7 +282,8 @@ static void build_rhct(GArray *table_data,
num_rhct_nodes++;
}
- if (cpu->cfg.satp_mode.supported != 0) {
+ if (!rv32 && cpu->cfg.satp_mode.supported != 0 &&
+ (cpu->cfg.satp_mode.map & ~(1 << VM_1_10_MBARE))) {
num_rhct_nodes++;
}
@@ -341,7 +343,8 @@ static void build_rhct(GArray *table_data,
}
/* MMU node structure */
- if (cpu->cfg.satp_mode.supported != 0) {
+ if (!rv32 && cpu->cfg.satp_mode.supported != 0 &&
+ (cpu->cfg.satp_mode.map & ~(1 << VM_1_10_MBARE))) {
satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
mmu_offset = table_data->len - table.table_offset;
build_append_int_noprefix(table_data, 2, 2); /* Type */
@@ -356,7 +359,7 @@ static void build_rhct(GArray *table_data,
} else if (satp_mode_max == VM_1_10_SV39) {
build_append_int_noprefix(table_data, 0, 1); /* Sv39 */
} else {
- assert(1);
+ g_assert_not_reached();
}
}
--
2.48.1
next prev parent reply other threads:[~2025-02-18 16:59 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-18 16:57 [PATCH 0/7] target/riscv: store max SATP mode as a single integer in RISCVCPUConfig Paolo Bonzini
2025-02-18 16:57 ` Paolo Bonzini [this message]
2025-03-06 1:13 ` [PATCH 1/7] hw/riscv: acpi: only create RHCT MMU entry for supported types Alistair Francis
2025-03-06 12:11 ` Paolo Bonzini
2025-02-18 16:57 ` [PATCH 2/7] target/riscv: env->misa_mxl is a constant Paolo Bonzini
2025-03-06 1:16 ` Alistair Francis
2025-03-06 13:00 ` Paolo Bonzini
2025-03-07 0:44 ` Alistair Francis
2025-03-10 17:34 ` Paolo Bonzini
2025-03-10 22:18 ` Alistair Francis
2025-03-11 6:17 ` Paolo Bonzini
2025-03-19 1:35 ` Alistair Francis
2025-02-18 16:57 ` [PATCH 3/7] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-03-06 1:23 ` Alistair Francis
2025-02-18 16:57 ` [PATCH 4/7] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-03-06 1:30 ` Alistair Francis
2025-03-06 2:57 ` Alistair Francis
2025-02-18 16:57 ` [PATCH 5/7] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-03-06 1:41 ` Alistair Francis
2025-02-18 16:57 ` [PATCH 6/7] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-03-06 2:39 ` Alistair Francis
2025-02-18 16:57 ` [PATCH 7/7] target/riscv: move satp_mode.{map,init} out of CPUConfig Paolo Bonzini
2025-03-06 2:42 ` [PATCH 7/7] target/riscv: move satp_mode.{map, init} " Alistair Francis
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