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x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=alex.williamson@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.457, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 20 Feb 2025 08:07:23 -0700 Alex Williamson wrote: > On Thu, 20 Feb 2025 11:45:35 +0100 > Eric Auger wrote: > > > Hi Alex, > > > > On 2/20/25 11:31 AM, Eric Auger wrote: > > > > > > Hi Alex, > > > > > > On 2/19/25 10:19 PM, Alex Williamson wrote: > > >> On Wed, 19 Feb 2025 11:58:44 -0700 > > >> Alex Williamson wrote: > > >> > > >>> On Wed, 19 Feb 2025 18:58:58 +0100 > > >>> Eric Auger wrote: > > >>> > > >>>> Since kernel commit: > > >>>> 2b2c651baf1c ("vfio/pci: Invalidate mmaps and block the access > > >>>> in D3hot power state") > > >>>> any attempt to do an mmap access to a BAR when the device is in d3hot > > >>>> state will generate a fault. > > >>>> > > >>>> On system_powerdown, if the VFIO device is translated by an IOMMU, > > >>>> the device is moved to D3hot state and then the vIOMMU gets disabled > > >>>> by the guest. As a result of this later operation, the address space is > > >>>> swapped from translated to untranslated. When re-enabling the aliased > > >>>> regions, the RAM regions are dma-mapped again and this causes DMA_MAP > > >>>> faults when attempting the operation on BARs. > > >>>> > > >>>> To avoid doing the remap on those BARs, we compute whether the > > >>>> device is in D3hot state and if so, skip the DMA MAP. > > >>> Thinking on this some more, QEMU PCI code already manages the device > > >>> BARs appearing in the address space based on the memory enable bit in > > >>> the command register. Should we do the same for PM state? > > >>> > > >>> IOW, the device going into low power state should remove the BARs from > > >>> the AddressSpace and waking the device should re-add them. The BAR DMA > > >>> mapping should then always be consistent, whereas here nothing would > > >>> remap the BARs when the device is woken. > > >>> > > >>> I imagine we'd need an interface to register the PM capability with the > > >>> core QEMU PCI code, where address space updates are performed relative > > >>> to both memory enable and power status. There might be a way to > > >>> implement this just for vfio-pci devices by toggling the enable state > > >>> of the BAR mmaps relative to PM state, but doing it at the PCI core > > >>> level seems like it'd provide behavior more true to physical hardware. > > >> I took a stab at this approach here, it doesn't obviously break > > >> anything in my configs, but I haven't yet tried to reproduce this exact > > >> scenario. > > >> > > >> https://gitlab.com/alex.williamson/qemu/-/tree/pci-pm-power-state > > > > it does not totally fix the issue: I now get: > > > > qemu-system-x86_64: warning: vfio_container_dma_map(0x55cc25705680, > > 0x380000000000, 0x1000000, 0x7f8762000000) = -14 (Bad address) > > 0000:41:00.0: PCI peer-to-peer transactions on BARs are not supported. > > Hmm, I'll reproduce and debug further. The intention here is that BARs > for the device in D3hot would not be DMA mapped, effectively as if the > memory enable bit in the command register were cleared, therefore I'd > hoped the listener is not called for this range. I forgot to mark the PM state field as writable in config space, so we were always reading back D0 state. Adding the following to pci_pm_init() resolves it: --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -445,6 +445,7 @@ int pci_pm_init(PCIDevice *d, uint8_t offset, Error **errp) d->pm_cap = cap; d->cap_present |= QEMU_PCI_CAP_PM; + pci_set_word(d->wmask + cap + PCI_PM_CTRL, PCI_PM_CTRL_STATE_MASK); return cap; } Changing this might cause a problem with migration, ISTR we validate the wmask with the source. Anyway, I'll post the series and we can test further and discuss it there. Thanks, Alex