* [PULL 00/41] target-arm queue
@ 2019-10-22 13:30 Peter Maydell
0 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2019-10-22 13:30 UTC (permalink / raw)
To: qemu-devel
The big thing in here is RTH's caching-of-tb-flags patchset
which should improve TCG performance.
thanks
-- PMM
The following changes since commit 2152e740a8938b3bad73bfe1a01f8b94dab02d41:
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-10-22 12:03:03 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191022
for you to fetch changes up to 833043a060f7d0e95ded88e61e992466305c0345:
hw/arm/digic4: Inline digic4_board_setup_ram() function (2019-10-22 14:21:57 +0100)
----------------------------------------------------------------
target-arm queue:
* Fix sign-extension for SMLAL* instructions
* aspeed: Add an AST2600 eval board
* Various ptimer device conversions to new transaction API
* Cache TB flags to avoid expensively recomputing them every time
* Add a dummy Samsung SDHCI controller model to exynos4 boards
* Minor refactorings of RAM creation for some arm boards
----------------------------------------------------------------
Cédric Le Goater (1):
aspeed: Add an AST2600 eval board
Guenter Roeck (1):
hw/timer/exynos4210_mct: Initialize ptimer before starting it
Peter Maydell (7):
hw/timer/arm_mptimer.c: Undo accidental rename of arm_mptimer_init()
hw/timer/puv3_ost.c: Switch to transaction-based ptimer API
hw/timer/sh_timer: Switch to transaction-based ptimer API
hw/timer/lm32_timer: Switch to transaction-based ptimer API
hw/timer/altera_timer.c: Switch to transaction-based ptimer API
hw/watchdog/etraxfs_timer.c: Switch to transaction-based ptimer API
hw/m68k/mcf5208.c: Switch to transaction-based ptimer API
Philippe Mathieu-Daudé (9):
hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions
hw/sd/sdhci: Add dummy Samsung SDHCI controller
hw/arm/exynos4210: Use the Samsung s3c SDHCI controller
hw/arm/xilinx_zynq: Use the IEC binary prefix definitions
hw/arm/mps2: Use the IEC binary prefix definitions
hw/arm/collie: Create the RAM in the board
hw/arm/omap2: Create the RAM in the board
hw/arm/omap1: Create the RAM in the board
hw/arm/digic4: Inline digic4_board_setup_ram() function
Richard Henderson (23):
target/arm: Fix sign-extension for SMLAL*
target/arm: Split out rebuild_hflags_common
target/arm: Split out rebuild_hflags_a64
target/arm: Split out rebuild_hflags_common_32
target/arm: Split arm_cpu_data_is_big_endian
target/arm: Split out rebuild_hflags_m32
target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state
target/arm: Split out rebuild_hflags_a32
target/arm: Split out rebuild_hflags_aprofile
target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state
target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state
target/arm: Hoist computation of TBFLAG_A32.VFPEN
target/arm: Add arm_rebuild_hflags
target/arm: Split out arm_mmu_idx_el
target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state
target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32})
target/arm: Rebuild hflags at EL changes
target/arm: Rebuild hflags at MSR writes
target/arm: Rebuild hflags at CPSR writes
target/arm: Rebuild hflags at Xscale SCTLR writes
target/arm: Rebuild hflags for M-profile
target/arm: Rebuild hflags for M-profile NVIC
target/arm: Rely on hflags correct in cpu_get_tb_cpu_state
hw/arm/strongarm.h | 4 +-
include/hw/arm/aspeed.h | 1 +
include/hw/arm/omap.h | 10 +-
include/hw/sd/sdhci.h | 2 +
target/arm/cpu.h | 84 ++++++----
target/arm/helper.h | 4 +
target/arm/internals.h | 9 ++
hw/arm/aspeed.c | 23 +++
hw/arm/collie.c | 8 +-
hw/arm/digic_boards.c | 9 +-
hw/arm/exynos4210.c | 2 +-
hw/arm/mps2-tz.c | 3 +-
hw/arm/mps2.c | 3 +-
hw/arm/nseries.c | 10 +-
hw/arm/omap1.c | 12 +-
hw/arm/omap2.c | 13 +-
hw/arm/omap_sx1.c | 8 +-
hw/arm/palm.c | 8 +-
hw/arm/strongarm.c | 7 +-
hw/arm/xilinx_zynq.c | 3 +-
hw/intc/armv7m_nvic.c | 22 +--
hw/m68k/mcf5208.c | 9 +-
hw/sd/sdhci.c | 68 +++++++-
hw/timer/altera_timer.c | 13 +-
hw/timer/arm_mptimer.c | 4 +-
hw/timer/etraxfs_timer.c | 23 +--
hw/timer/exynos4210_mct.c | 2 +-
hw/timer/lm32_timer.c | 13 +-
hw/timer/puv3_ost.c | 9 +-
hw/timer/sh_timer.c | 13 +-
linux-user/syscall.c | 1 +
target/arm/cpu.c | 1 +
target/arm/helper-a64.c | 3 +
target/arm/helper.c | 393 +++++++++++++++++++++++++++++----------------
target/arm/m_helper.c | 6 +
target/arm/machine.c | 1 +
target/arm/op_helper.c | 4 +
target/arm/translate-a64.c | 13 +-
target/arm/translate.c | 37 ++++-
39 files changed, 588 insertions(+), 270 deletions(-)
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/41] target-arm queue
@ 2020-10-20 15:56 Peter Maydell
2020-10-20 16:36 ` Philippe Mathieu-Daudé
2020-10-20 16:36 ` no-reply
0 siblings, 2 replies; 55+ messages in thread
From: Peter Maydell @ 2020-10-20 15:56 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 4c41341af76cfc85b5a6c0f87de4838672ab9f89:
Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into staging (2020-10-20 11:20:36 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201020
for you to fetch changes up to 6358890cb939192f6169fdf7664d903bf9b1d338:
tests/tcg/aarch64: Add bti smoke tests (2020-10-20 16:12:02 +0100)
----------------------------------------------------------------
target-arm queue:
* Fix AArch32 SMLAD incorrect setting of Q bit
* AArch32 VCVT fixed-point to float is always round-to-nearest
* strongarm: Fix 'time to transmit a char' unit comment
* Restrict APEI tables generation to the 'virt' machine
* bcm2835: minor code cleanups
* correctly flush TLBs when TBI is enabled
* tests/qtest: Add npcm7xx timer test
* loads-stores.rst: add footnote that clarifies GETPC usage
* Fix reported EL for mte_check_fail
* Ignore HCR_EL2.ATA when {E2H,TGE} != 11
* microbit_i2c: Fix coredump when dump-vmstate
* nseries: Fix loading kernel image on n8x0 machines
* Implement v8.1M low-overhead-loops
* linux-user: Support AArch64 BTI
----------------------------------------------------------------
Emanuele Giuseppe Esposito (1):
loads-stores.rst: add footnote that clarifies GETPC usage
Havard Skinnemoen (1):
tests/qtest: Add npcm7xx timer test
Peng Liang (1):
microbit_i2c: Fix coredump when dump-vmstate
Peter Maydell (12):
target/arm: Fix SMLAD incorrect setting of Q bit
target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest
decodetree: Fix codegen for non-overlapping group inside overlapping group
target/arm: Implement v8.1M NOCP handling
target/arm: Implement v8.1M conditional-select insns
target/arm: Make the t32 insn[25:23]=111 group non-overlapping
target/arm: Don't allow BLX imm for M-profile
target/arm: Implement v8.1M branch-future insns (as NOPs)
target/arm: Implement v8.1M low-overhead-loop instructions
target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
Philippe Mathieu-Daudé (10):
hw/arm/strongarm: Fix 'time to transmit a char' unit comment
hw/arm: Restrict APEI tables generation to the 'virt' machine
hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition
hw/timer/bcm2835: Rename variable holding CTRL_STATUS register
hw/timer/bcm2835: Support the timer COMPARE registers
hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs
hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
hw/arm/nseries: Fix loading kernel image on n8x0 machines
linux-user/elfload: Avoid leaking interp_name using GLib memory API
Richard Henderson (16):
accel/tcg: Add tlb_flush_page_bits_by_mmuidx*
target/arm: Use tlb_flush_page_bits_by_mmuidx*
target/arm: Remove redundant mmu_idx lookup
target/arm: Fix reported EL for mte_check_fail
target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
linux-user/aarch64: Reset btype for signals
linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI
include/elf: Add defines related to GNU property notes for AArch64
linux-user/elfload: Fix coding style in load_elf_image
linux-user/elfload: Adjust iteration over phdr
linux-user/elfload: Move PT_INTERP detection to first loop
linux-user/elfload: Use Error for load_elf_image
linux-user/elfload: Use Error for load_elf_interp
linux-user/elfload: Parse NT_GNU_PROPERTY_TYPE_0 notes
linux-user/elfload: Parse GNU_PROPERTY_AARCH64_FEATURE_1_AND
tests/tcg/aarch64: Add bti smoke tests
docs/devel/loads-stores.rst | 8 +-
default-configs/devices/arm-softmmu.mak | 1 -
include/elf.h | 22 ++
include/exec/cpu-all.h | 2 +
include/exec/exec-all.h | 36 ++
include/hw/timer/bcm2835_systmr.h | 17 +-
linux-user/qemu.h | 4 +
linux-user/syscall_defs.h | 4 +
target/arm/cpu.h | 13 +
target/arm/helper.h | 13 +
target/arm/internals.h | 9 +-
target/arm/m-nocp.decode | 10 +-
target/arm/t32.decode | 50 ++-
accel/tcg/cputlb.c | 275 +++++++++++++++-
hw/arm/bcm2835_peripherals.c | 13 +-
hw/arm/nseries.c | 1 +
hw/arm/strongarm.c | 2 +-
hw/i2c/microbit_i2c.c | 1 +
hw/intc/bcm2835_ic.c | 4 +-
hw/intc/bcm2836_control.c | 8 +-
hw/timer/bcm2835_systmr.c | 57 ++--
linux-user/aarch64/signal.c | 10 +-
linux-user/elfload.c | 326 ++++++++++++++----
linux-user/mmap.c | 16 +
target/arm/cpu.c | 38 ++-
target/arm/helper.c | 55 +++-
target/arm/mte_helper.c | 13 +-
target/arm/translate-a64.c | 6 +-
target/arm/translate.c | 239 +++++++++++++-
target/arm/vfp_helper.c | 76 +++--
tests/qtest/npcm7xx_timer-test.c | 562 ++++++++++++++++++++++++++++++++
tests/tcg/aarch64/bti-1.c | 62 ++++
tests/tcg/aarch64/bti-2.c | 108 ++++++
tests/tcg/aarch64/bti-crt.inc.c | 51 +++
hw/arm/Kconfig | 1 +
hw/intc/trace-events | 4 +
hw/timer/trace-events | 6 +-
scripts/decodetree.py | 2 +-
target/arm/translate-vfp.c.inc | 41 ++-
tests/qtest/meson.build | 1 +
tests/tcg/aarch64/Makefile.target | 10 +
tests/tcg/configure.sh | 4 +
42 files changed, 1973 insertions(+), 208 deletions(-)
create mode 100644 tests/qtest/npcm7xx_timer-test.c
create mode 100644 tests/tcg/aarch64/bti-1.c
create mode 100644 tests/tcg/aarch64/bti-2.c
create mode 100644 tests/tcg/aarch64/bti-crt.inc.c
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/41] target-arm queue
2020-10-20 15:56 Peter Maydell
@ 2020-10-20 16:36 ` Philippe Mathieu-Daudé
2020-10-20 16:36 ` no-reply
1 sibling, 0 replies; 55+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-20 16:36 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 10/20/20 5:56 PM, Peter Maydell wrote:
> The following changes since commit 4c41341af76cfc85b5a6c0f87de4838672ab9f89:
>
> Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into staging (2020-10-20 11:20:36 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201020
>
> for you to fetch changes up to 6358890cb939192f6169fdf7664d903bf9b1d338:
>
> tests/tcg/aarch64: Add bti smoke tests (2020-10-20 16:12:02 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Fix AArch32 SMLAD incorrect setting of Q bit
> * AArch32 VCVT fixed-point to float is always round-to-nearest
> * strongarm: Fix 'time to transmit a char' unit comment
> * Restrict APEI tables generation to the 'virt' machine
> * bcm2835: minor code cleanups
Just to clarify, the main part there is a bugfix ;) Only the first
IRQ from the SYS_timer was delivered to the ARM core. It passed my
smoke test because when I wrote the model only u-boot was using this
peripheral, then Linux started to use it.
Fixes: 0e5bbd74064 ("hw/arm/bcm2835_peripherals: Use the SYS_timer")
> * correctly flush TLBs when TBI is enabled
> * tests/qtest: Add npcm7xx timer test
> * loads-stores.rst: add footnote that clarifies GETPC usage
> * Fix reported EL for mte_check_fail
> * Ignore HCR_EL2.ATA when {E2H,TGE} != 11
> * microbit_i2c: Fix coredump when dump-vmstate
> * nseries: Fix loading kernel image on n8x0 machines
> * Implement v8.1M low-overhead-loops
> * linux-user: Support AArch64 BTI
>
> ----------------------------------------------------------------
> Emanuele Giuseppe Esposito (1):
> loads-stores.rst: add footnote that clarifies GETPC usage
>
> Havard Skinnemoen (1):
> tests/qtest: Add npcm7xx timer test
>
> Peng Liang (1):
> microbit_i2c: Fix coredump when dump-vmstate
>
> Peter Maydell (12):
> target/arm: Fix SMLAD incorrect setting of Q bit
> target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest
> decodetree: Fix codegen for non-overlapping group inside overlapping group
> target/arm: Implement v8.1M NOCP handling
> target/arm: Implement v8.1M conditional-select insns
> target/arm: Make the t32 insn[25:23]=111 group non-overlapping
> target/arm: Don't allow BLX imm for M-profile
> target/arm: Implement v8.1M branch-future insns (as NOPs)
> target/arm: Implement v8.1M low-overhead-loop instructions
> target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
> target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
> target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
>
> Philippe Mathieu-Daudé (10):
> hw/arm/strongarm: Fix 'time to transmit a char' unit comment
> hw/arm: Restrict APEI tables generation to the 'virt' machine
> hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition
> hw/timer/bcm2835: Rename variable holding CTRL_STATUS register
> hw/timer/bcm2835: Support the timer COMPARE registers
> hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs
> hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
> hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
> hw/arm/nseries: Fix loading kernel image on n8x0 machines
> linux-user/elfload: Avoid leaking interp_name using GLib memory API
>
> Richard Henderson (16):
> accel/tcg: Add tlb_flush_page_bits_by_mmuidx*
> target/arm: Use tlb_flush_page_bits_by_mmuidx*
> target/arm: Remove redundant mmu_idx lookup
> target/arm: Fix reported EL for mte_check_fail
> target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
> linux-user/aarch64: Reset btype for signals
> linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI
> include/elf: Add defines related to GNU property notes for AArch64
> linux-user/elfload: Fix coding style in load_elf_image
> linux-user/elfload: Adjust iteration over phdr
> linux-user/elfload: Move PT_INTERP detection to first loop
> linux-user/elfload: Use Error for load_elf_image
> linux-user/elfload: Use Error for load_elf_interp
> linux-user/elfload: Parse NT_GNU_PROPERTY_TYPE_0 notes
> linux-user/elfload: Parse GNU_PROPERTY_AARCH64_FEATURE_1_AND
> tests/tcg/aarch64: Add bti smoke tests
>
> docs/devel/loads-stores.rst | 8 +-
> default-configs/devices/arm-softmmu.mak | 1 -
> include/elf.h | 22 ++
> include/exec/cpu-all.h | 2 +
> include/exec/exec-all.h | 36 ++
> include/hw/timer/bcm2835_systmr.h | 17 +-
> linux-user/qemu.h | 4 +
> linux-user/syscall_defs.h | 4 +
> target/arm/cpu.h | 13 +
> target/arm/helper.h | 13 +
> target/arm/internals.h | 9 +-
> target/arm/m-nocp.decode | 10 +-
> target/arm/t32.decode | 50 ++-
> accel/tcg/cputlb.c | 275 +++++++++++++++-
> hw/arm/bcm2835_peripherals.c | 13 +-
> hw/arm/nseries.c | 1 +
> hw/arm/strongarm.c | 2 +-
> hw/i2c/microbit_i2c.c | 1 +
> hw/intc/bcm2835_ic.c | 4 +-
> hw/intc/bcm2836_control.c | 8 +-
> hw/timer/bcm2835_systmr.c | 57 ++--
> linux-user/aarch64/signal.c | 10 +-
> linux-user/elfload.c | 326 ++++++++++++++----
> linux-user/mmap.c | 16 +
> target/arm/cpu.c | 38 ++-
> target/arm/helper.c | 55 +++-
> target/arm/mte_helper.c | 13 +-
> target/arm/translate-a64.c | 6 +-
> target/arm/translate.c | 239 +++++++++++++-
> target/arm/vfp_helper.c | 76 +++--
> tests/qtest/npcm7xx_timer-test.c | 562 ++++++++++++++++++++++++++++++++
> tests/tcg/aarch64/bti-1.c | 62 ++++
> tests/tcg/aarch64/bti-2.c | 108 ++++++
> tests/tcg/aarch64/bti-crt.inc.c | 51 +++
> hw/arm/Kconfig | 1 +
> hw/intc/trace-events | 4 +
> hw/timer/trace-events | 6 +-
> scripts/decodetree.py | 2 +-
> target/arm/translate-vfp.c.inc | 41 ++-
> tests/qtest/meson.build | 1 +
> tests/tcg/aarch64/Makefile.target | 10 +
> tests/tcg/configure.sh | 4 +
> 42 files changed, 1973 insertions(+), 208 deletions(-)
> create mode 100644 tests/qtest/npcm7xx_timer-test.c
> create mode 100644 tests/tcg/aarch64/bti-1.c
> create mode 100644 tests/tcg/aarch64/bti-2.c
> create mode 100644 tests/tcg/aarch64/bti-crt.inc.c
>
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/41] target-arm queue
2020-10-20 15:56 Peter Maydell
2020-10-20 16:36 ` Philippe Mathieu-Daudé
@ 2020-10-20 16:36 ` no-reply
1 sibling, 0 replies; 55+ messages in thread
From: no-reply @ 2020-10-20 16:36 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel
Patchew URL: https://patchew.org/QEMU/20201020155656.8045-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201020155656.8045-1-peter.maydell@linaro.org
Subject: [PULL 00/41] target-arm queue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20201020155656.8045-1-peter.maydell@linaro.org -> patchew/20201020155656.8045-1-peter.maydell@linaro.org
Switched to a new branch 'test'
6abc744 tests/tcg/aarch64: Add bti smoke tests
7a68af2 linux-user/elfload: Parse GNU_PROPERTY_AARCH64_FEATURE_1_AND
01490e2 linux-user/elfload: Parse NT_GNU_PROPERTY_TYPE_0 notes
acf0bee linux-user/elfload: Use Error for load_elf_interp
91b7dd8 linux-user/elfload: Use Error for load_elf_image
7049151 linux-user/elfload: Move PT_INTERP detection to first loop
a0f6f8a linux-user/elfload: Adjust iteration over phdr
f72dee2 linux-user/elfload: Fix coding style in load_elf_image
7596df6 linux-user/elfload: Avoid leaking interp_name using GLib memory API
3fe25e0 include/elf: Add defines related to GNU property notes for AArch64
13164fa linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI
c4b76c8 linux-user/aarch64: Reset btype for signals
dc528f1 target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
de2ff37 target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
f2c3512 target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
e0a512a target/arm: Implement v8.1M low-overhead-loop instructions
06a929a target/arm: Implement v8.1M branch-future insns (as NOPs)
b4a7269 target/arm: Don't allow BLX imm for M-profile
8e904bc target/arm: Make the t32 insn[25:23]=111 group non-overlapping
e3fcb8a target/arm: Implement v8.1M conditional-select insns
d166303 target/arm: Implement v8.1M NOCP handling
2ceaf26 decodetree: Fix codegen for non-overlapping group inside overlapping group
8c0c38f hw/arm/nseries: Fix loading kernel image on n8x0 machines
99b88b1 microbit_i2c: Fix coredump when dump-vmstate
e435b66 target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
c55690c target/arm: Fix reported EL for mte_check_fail
b7d98d6 target/arm: Remove redundant mmu_idx lookup
81baae0 hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
5860faf hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
76359b5 loads-stores.rst: add footnote that clarifies GETPC usage
b503f8f tests/qtest: Add npcm7xx timer test
37f9306 target/arm: Use tlb_flush_page_bits_by_mmuidx*
e4d595c accel/tcg: Add tlb_flush_page_bits_by_mmuidx*
323e682 hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs
e10bde5 hw/timer/bcm2835: Support the timer COMPARE registers
86d375e hw/timer/bcm2835: Rename variable holding CTRL_STATUS register
5ffed07 hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition
2540e23 hw/arm: Restrict APEI tables generation to the 'virt' machine
2bafeaf hw/arm/strongarm: Fix 'time to transmit a char' unit comment
8f189cc target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest
a647677 target/arm: Fix SMLAD incorrect setting of Q bit
=== OUTPUT BEGIN ===
1/41 Checking commit a6476779ea51 (target/arm: Fix SMLAD incorrect setting of Q bit)
2/41 Checking commit 8f189ccc02db (target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest)
3/41 Checking commit 2bafeaf8bf3f (hw/arm/strongarm: Fix 'time to transmit a char' unit comment)
4/41 Checking commit 2540e23a83dd (hw/arm: Restrict APEI tables generation to the 'virt' machine)
5/41 Checking commit 5ffed07b26c0 (hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition)
6/41 Checking commit 86d375e278b1 (hw/timer/bcm2835: Rename variable holding CTRL_STATUS register)
7/41 Checking commit e10bde59e2a4 (hw/timer/bcm2835: Support the timer COMPARE registers)
8/41 Checking commit 323e6827dbbc (hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs)
9/41 Checking commit e4d595cfa99f (accel/tcg: Add tlb_flush_page_bits_by_mmuidx*)
10/41 Checking commit 37f9306c03c9 (target/arm: Use tlb_flush_page_bits_by_mmuidx*)
11/41 Checking commit b503f8fa751d (tests/qtest: Add npcm7xx timer test)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#37:
new file mode 100644
total: 0 errors, 1 warnings, 569 lines checked
Patch 11/41 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/41 Checking commit 76359b58d121 (loads-stores.rst: add footnote that clarifies GETPC usage)
13/41 Checking commit 5860faf69fb1 (hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers)
14/41 Checking commit 81baae0ed94e (hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers)
15/41 Checking commit b7d98d67ee25 (target/arm: Remove redundant mmu_idx lookup)
16/41 Checking commit c55690c5edb3 (target/arm: Fix reported EL for mte_check_fail)
17/41 Checking commit e435b66cfd75 (target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11)
18/41 Checking commit 99b88b1e120a (microbit_i2c: Fix coredump when dump-vmstate)
19/41 Checking commit 8c0c38fd2031 (hw/arm/nseries: Fix loading kernel image on n8x0 machines)
20/41 Checking commit 2ceaf26e4ebc (decodetree: Fix codegen for non-overlapping group inside overlapping group)
21/41 Checking commit d166303278b8 (target/arm: Implement v8.1M NOCP handling)
22/41 Checking commit e3fcb8a10bd0 (target/arm: Implement v8.1M conditional-select insns)
23/41 Checking commit 8e904bc6d157 (target/arm: Make the t32 insn[25:23]=111 group non-overlapping)
24/41 Checking commit b4a7269fe480 (target/arm: Don't allow BLX imm for M-profile)
25/41 Checking commit 06a929a984b3 (target/arm: Implement v8.1M branch-future insns (as NOPs))
26/41 Checking commit e0a512af2aea (target/arm: Implement v8.1M low-overhead-loop instructions)
27/41 Checking commit f2c351298873 (target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile)
28/41 Checking commit de2ff3705cdc (target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16)
29/41 Checking commit dc528f1d2564 (target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension)
30/41 Checking commit c4b76c81695c (linux-user/aarch64: Reset btype for signals)
31/41 Checking commit 13164fa337d7 (linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI)
32/41 Checking commit 3fe25e0a9b47 (include/elf: Add defines related to GNU property notes for AArch64)
33/41 Checking commit 7596df60e0a7 (linux-user/elfload: Avoid leaking interp_name using GLib memory API)
34/41 Checking commit f72dee236706 (linux-user/elfload: Fix coding style in load_elf_image)
35/41 Checking commit a0f6f8a06f8b (linux-user/elfload: Adjust iteration over phdr)
36/41 Checking commit 7049151b6492 (linux-user/elfload: Move PT_INTERP detection to first loop)
37/41 Checking commit 91b7dd86b6f2 (linux-user/elfload: Use Error for load_elf_image)
38/41 Checking commit acf0beedd932 (linux-user/elfload: Use Error for load_elf_interp)
39/41 Checking commit 01490e235e98 (linux-user/elfload: Parse NT_GNU_PROPERTY_TYPE_0 notes)
40/41 Checking commit 7a68af21bbdd (linux-user/elfload: Parse GNU_PROPERTY_AARCH64_FEATURE_1_AND)
41/41 Checking commit 6abc744a59cb (tests/tcg/aarch64: Add bti smoke tests)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
ERROR: externs should be avoided in .c files
#167: FILE: tests/tcg/aarch64/bti-2.c:56:
+extern char test_begin[], test_end[];
ERROR: use qemu_real_host_page_size instead of getpagesize()
#201: FILE: tests/tcg/aarch64/bti-2.c:90:
+ void *p = mmap(0, getpagesize(),
ERROR: externs should be avoided in .c files
#238: FILE: tests/tcg/aarch64/bti-crt.inc.c:13:
+int main(void);
total: 3 errors, 1 warnings, 247 lines checked
Patch 41/41 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20201020155656.8045-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/41] target-arm queue
@ 2023-10-27 14:39 Peter Maydell
2023-10-29 23:15 ` Stefan Hajnoczi
2023-10-31 7:51 ` Stefan Hajnoczi
0 siblings, 2 replies; 55+ messages in thread
From: Peter Maydell @ 2023-10-27 14:39 UTC (permalink / raw)
To: qemu-devel
Hi; here's the latest target-arm queue. Mostly this is refactoring
and cleanup type patches.
thanks
-- PMM
The following changes since commit c60be6e3e38cb36dc66129e757ec4b34152232be:
Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging (2023-10-27 09:43:53 +0900)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027
for you to fetch changes up to df93de987f423a0ed918c425f5dbd9a25d3c6229:
hw/net/cadence_gem: enforce 32 bits variable size for CRC (2023-10-27 15:27:06 +0100)
----------------------------------------------------------------
target-arm queue:
* Correct minor errors in Cortex-A710 definition
* Implement Neoverse N2 CPU model
* Refactor feature test functions out into separate header
* Fix syndrome for FGT traps on ERET
* Remove 'hw/arm/boot.h' includes from various header files
* pxa2xx: Refactoring/cleanup
* Avoid using 'first_cpu' when first ARM CPU is reachable
* misc/led: LED state is set opposite of what is expected
* hw/net/cadence_gen: clean up to use FIELD macros
* hw/net/cadence_gem: perform PHY access on write only
* hw/net/cadence_gem: enforce 32 bits variable size for CRC
----------------------------------------------------------------
Glenn Miles (1):
misc/led: LED state is set opposite of what is expected
Luc Michel (11):
hw/net/cadence_gem: use REG32 macro for register definitions
hw/net/cadence_gem: use FIELD for screening registers
hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
hw/net/cadence_gem: use FIELD to describe NWCFG register fields
hw/net/cadence_gem: use FIELD to describe DMACFG register fields
hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
hw/net/cadence_gem: use FIELD to describe IRQ register fields
hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
hw/net/cadence_gem: perform PHY access on write only
hw/net/cadence_gem: enforce 32 bits variable size for CRC
Peter Maydell (9):
target/arm: Correct minor errors in Cortex-A710 definition
target/arm: Implement Neoverse N2 CPU model
target/arm: Move feature test functions to their own header
target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together
target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2
target/arm: Move ID_AA64ISAR* test functions together
target/arm: Move ID_AA64PFR* tests together
target/arm: Move ID_AA64DFR* feature tests together
target/arm: Fix syndrome for FGT traps on ERET
Philippe Mathieu-Daudé (20):
hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header
hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header
hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header
hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header
hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header
hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header
hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header
hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header
hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header
hw/sd/pxa2xx: Realize sysbus device before accessing it
hw/sd/pxa2xx: Do not open-code sysbus_create_simple()
hw/pcmcia/pxa2xx: Realize sysbus device before accessing it
hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()
hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()
hw/intc/pxa2xx: Convert to Resettable interface
hw/intc/pxa2xx: Pass CPU reference using QOM link property
hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()
hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it
hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable
docs/system/arm/virt.rst | 1 +
bsd-user/arm/target_arch.h | 1 +
include/hw/arm/allwinner-a10.h | 1 -
include/hw/arm/allwinner-h3.h | 1 -
include/hw/arm/allwinner-r40.h | 1 -
include/hw/arm/fsl-imx25.h | 1 -
include/hw/arm/fsl-imx31.h | 1 -
include/hw/arm/fsl-imx6.h | 1 -
include/hw/arm/fsl-imx6ul.h | 1 -
include/hw/arm/fsl-imx7.h | 1 -
include/hw/arm/pxa.h | 2 -
include/hw/arm/xlnx-versal.h | 1 -
include/hw/arm/xlnx-zynqmp.h | 1 -
linux-user/aarch64/target_prctl.h | 2 +
target/arm/cpu-features.h | 994 ++++++++++++++++++++++++++++++++++++++
target/arm/cpu.h | 971 -------------------------------------
target/arm/internals.h | 1 +
target/arm/tcg/translate.h | 2 +-
hw/arm/armv7m.c | 1 +
hw/arm/bananapi_m2u.c | 3 +-
hw/arm/cubieboard.c | 1 +
hw/arm/exynos4_boards.c | 7 +-
hw/arm/imx25_pdk.c | 1 +
hw/arm/kzm.c | 1 +
hw/arm/mcimx6ul-evk.c | 1 +
hw/arm/mcimx7d-sabre.c | 1 +
hw/arm/orangepi.c | 3 +-
hw/arm/pxa2xx.c | 17 +-
hw/arm/pxa2xx_pic.c | 38 +-
hw/arm/realview.c | 2 +-
hw/arm/sabrelite.c | 1 +
hw/arm/sbsa-ref.c | 1 +
hw/arm/virt.c | 1 +
hw/arm/xilinx_zynq.c | 2 +-
hw/arm/xlnx-versal-virt.c | 1 +
hw/arm/xlnx-zcu102.c | 1 +
hw/intc/armv7m_nvic.c | 1 +
hw/misc/led.c | 2 +-
hw/net/cadence_gem.c | 884 ++++++++++++++++++---------------
hw/pcmcia/pxa2xx.c | 15 -
hw/sd/pxa2xx_mmci.c | 7 +-
linux-user/aarch64/cpu_loop.c | 1 +
linux-user/aarch64/signal.c | 1 +
linux-user/arm/signal.c | 1 +
linux-user/elfload.c | 4 +
linux-user/mmap.c | 4 +
target/arm/arch_dump.c | 1 +
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 1 +
target/arm/debug_helper.c | 1 +
target/arm/gdbstub.c | 1 +
target/arm/helper.c | 1 +
target/arm/kvm64.c | 1 +
target/arm/machine.c | 1 +
target/arm/ptw.c | 1 +
target/arm/tcg/cpu64.c | 115 ++++-
target/arm/tcg/hflags.c | 1 +
target/arm/tcg/m_helper.c | 1 +
target/arm/tcg/op_helper.c | 1 +
target/arm/tcg/pauth_helper.c | 1 +
target/arm/tcg/tlb_helper.c | 1 +
target/arm/tcg/translate-a64.c | 4 +-
target/arm/vfp_helper.c | 1 +
63 files changed, 1702 insertions(+), 1419 deletions(-)
create mode 100644 target/arm/cpu-features.h
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/41] target-arm queue
2023-10-27 14:39 Peter Maydell
@ 2023-10-29 23:15 ` Stefan Hajnoczi
2023-10-30 10:09 ` Peter Maydell
2023-10-31 7:51 ` Stefan Hajnoczi
1 sibling, 1 reply; 55+ messages in thread
From: Stefan Hajnoczi @ 2023-10-29 23:15 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
On Fri, 27 Oct 2023 at 23:41, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Hi; here's the latest target-arm queue. Mostly this is refactoring
> and cleanup type patches.
>
> thanks
> -- PMM
Hi Peter,
I can't find this email thread on lore.kernel.org and your git repo
doesn't let me fetch the tag:
$ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20231027
fatal: couldn't find remote ref tags/pull-target-arm-20231027
cgit shows the tag though, for some reason:
https://git.linaro.org/people/pmaydell/qemu-arm.git/tag/?h=pull-target-arm-20231027
Any idea what's up with this pull request? Thanks!
Stefan
>
> The following changes since commit c60be6e3e38cb36dc66129e757ec4b34152232be:
>
> Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging (2023-10-27 09:43:53 +0900)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027
>
> for you to fetch changes up to df93de987f423a0ed918c425f5dbd9a25d3c6229:
>
> hw/net/cadence_gem: enforce 32 bits variable size for CRC (2023-10-27 15:27:06 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Correct minor errors in Cortex-A710 definition
> * Implement Neoverse N2 CPU model
> * Refactor feature test functions out into separate header
> * Fix syndrome for FGT traps on ERET
> * Remove 'hw/arm/boot.h' includes from various header files
> * pxa2xx: Refactoring/cleanup
> * Avoid using 'first_cpu' when first ARM CPU is reachable
> * misc/led: LED state is set opposite of what is expected
> * hw/net/cadence_gen: clean up to use FIELD macros
> * hw/net/cadence_gem: perform PHY access on write only
> * hw/net/cadence_gem: enforce 32 bits variable size for CRC
>
> ----------------------------------------------------------------
> Glenn Miles (1):
> misc/led: LED state is set opposite of what is expected
>
> Luc Michel (11):
> hw/net/cadence_gem: use REG32 macro for register definitions
> hw/net/cadence_gem: use FIELD for screening registers
> hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
> hw/net/cadence_gem: use FIELD to describe NWCFG register fields
> hw/net/cadence_gem: use FIELD to describe DMACFG register fields
> hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
> hw/net/cadence_gem: use FIELD to describe IRQ register fields
> hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
> hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
> hw/net/cadence_gem: perform PHY access on write only
> hw/net/cadence_gem: enforce 32 bits variable size for CRC
>
> Peter Maydell (9):
> target/arm: Correct minor errors in Cortex-A710 definition
> target/arm: Implement Neoverse N2 CPU model
> target/arm: Move feature test functions to their own header
> target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together
> target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2
> target/arm: Move ID_AA64ISAR* test functions together
> target/arm: Move ID_AA64PFR* tests together
> target/arm: Move ID_AA64DFR* feature tests together
> target/arm: Fix syndrome for FGT traps on ERET
>
> Philippe Mathieu-Daudé (20):
> hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header
> hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header
> hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header
> hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
> hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header
> hw/sd/pxa2xx: Realize sysbus device before accessing it
> hw/sd/pxa2xx: Do not open-code sysbus_create_simple()
> hw/pcmcia/pxa2xx: Realize sysbus device before accessing it
> hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()
> hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()
> hw/intc/pxa2xx: Convert to Resettable interface
> hw/intc/pxa2xx: Pass CPU reference using QOM link property
> hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()
> hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it
> hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable
>
> docs/system/arm/virt.rst | 1 +
> bsd-user/arm/target_arch.h | 1 +
> include/hw/arm/allwinner-a10.h | 1 -
> include/hw/arm/allwinner-h3.h | 1 -
> include/hw/arm/allwinner-r40.h | 1 -
> include/hw/arm/fsl-imx25.h | 1 -
> include/hw/arm/fsl-imx31.h | 1 -
> include/hw/arm/fsl-imx6.h | 1 -
> include/hw/arm/fsl-imx6ul.h | 1 -
> include/hw/arm/fsl-imx7.h | 1 -
> include/hw/arm/pxa.h | 2 -
> include/hw/arm/xlnx-versal.h | 1 -
> include/hw/arm/xlnx-zynqmp.h | 1 -
> linux-user/aarch64/target_prctl.h | 2 +
> target/arm/cpu-features.h | 994 ++++++++++++++++++++++++++++++++++++++
> target/arm/cpu.h | 971 -------------------------------------
> target/arm/internals.h | 1 +
> target/arm/tcg/translate.h | 2 +-
> hw/arm/armv7m.c | 1 +
> hw/arm/bananapi_m2u.c | 3 +-
> hw/arm/cubieboard.c | 1 +
> hw/arm/exynos4_boards.c | 7 +-
> hw/arm/imx25_pdk.c | 1 +
> hw/arm/kzm.c | 1 +
> hw/arm/mcimx6ul-evk.c | 1 +
> hw/arm/mcimx7d-sabre.c | 1 +
> hw/arm/orangepi.c | 3 +-
> hw/arm/pxa2xx.c | 17 +-
> hw/arm/pxa2xx_pic.c | 38 +-
> hw/arm/realview.c | 2 +-
> hw/arm/sabrelite.c | 1 +
> hw/arm/sbsa-ref.c | 1 +
> hw/arm/virt.c | 1 +
> hw/arm/xilinx_zynq.c | 2 +-
> hw/arm/xlnx-versal-virt.c | 1 +
> hw/arm/xlnx-zcu102.c | 1 +
> hw/intc/armv7m_nvic.c | 1 +
> hw/misc/led.c | 2 +-
> hw/net/cadence_gem.c | 884 ++++++++++++++++++---------------
> hw/pcmcia/pxa2xx.c | 15 -
> hw/sd/pxa2xx_mmci.c | 7 +-
> linux-user/aarch64/cpu_loop.c | 1 +
> linux-user/aarch64/signal.c | 1 +
> linux-user/arm/signal.c | 1 +
> linux-user/elfload.c | 4 +
> linux-user/mmap.c | 4 +
> target/arm/arch_dump.c | 1 +
> target/arm/cpu.c | 1 +
> target/arm/cpu64.c | 1 +
> target/arm/debug_helper.c | 1 +
> target/arm/gdbstub.c | 1 +
> target/arm/helper.c | 1 +
> target/arm/kvm64.c | 1 +
> target/arm/machine.c | 1 +
> target/arm/ptw.c | 1 +
> target/arm/tcg/cpu64.c | 115 ++++-
> target/arm/tcg/hflags.c | 1 +
> target/arm/tcg/m_helper.c | 1 +
> target/arm/tcg/op_helper.c | 1 +
> target/arm/tcg/pauth_helper.c | 1 +
> target/arm/tcg/tlb_helper.c | 1 +
> target/arm/tcg/translate-a64.c | 4 +-
> target/arm/vfp_helper.c | 1 +
> 63 files changed, 1702 insertions(+), 1419 deletions(-)
> create mode 100644 target/arm/cpu-features.h
>
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/41] target-arm queue
2023-10-29 23:15 ` Stefan Hajnoczi
@ 2023-10-30 10:09 ` Peter Maydell
2023-10-30 22:09 ` Stefan Hajnoczi
0 siblings, 1 reply; 55+ messages in thread
From: Peter Maydell @ 2023-10-30 10:09 UTC (permalink / raw)
To: Stefan Hajnoczi; +Cc: qemu-devel
On Sun, 29 Oct 2023 at 23:15, Stefan Hajnoczi <stefanha@gmail.com> wrote:
>
> On Fri, 27 Oct 2023 at 23:41, Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> > Hi; here's the latest target-arm queue. Mostly this is refactoring
> > and cleanup type patches.
> Hi Peter,
> I can't find this email thread on lore.kernel.org and your git repo
> doesn't let me fetch the tag:
>
> $ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20231027
> fatal: couldn't find remote ref tags/pull-target-arm-20231027
This works for me:
$ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20231027
remote: Enumerating objects: 16753, done.
remote: Counting objects: 100% (16753/16753), done.
remote: Compressing objects: 100% (3181/3181), done.
remote: Total 17529 (delta 14031), reused 16255 (delta 13541), pack-reused 776
Receiving objects: 100% (17529/17529), 22.87 MiB | 10.44 MiB/s, done.
Resolving deltas: 100% (14498/14498), completed with 1672 local objects.
From https://git.linaro.org/people/pmaydell/qemu-arm
* tag pull-target-arm-20231027 -> FETCH_HEAD
> cgit shows the tag though, for some reason:
> https://git.linaro.org/people/pmaydell/qemu-arm.git/tag/?h=pull-target-arm-20231027
>
> Any idea what's up with this pull request? Thanks!
'git.linaro.org' has several geolocated servers and pushes to
it should get mirrored across to all of them. Maybe the
syncing between them went wrong? You could try using one
specific one:
https://git-us.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20231027
git-ie.linaro.org also seems to have the tag.
If you let me know what 'git.linaro.org' resolves to for you
I can check with our IT whether the syncing has broken.
I don't know why the email hasn't hit lore.kernel.org, but
that seems likely to be a problem with lore, because the
series did reach patchew, the lists.gnu.org archive, and you:
https://patchew.org/QEMU/20231027143942.3413881-1-peter.maydell@linaro.org/
https://lists.gnu.org/archive/html/qemu-devel/2023-10/msg09548.html
thanks
-- PMM
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/41] target-arm queue
2023-10-30 10:09 ` Peter Maydell
@ 2023-10-30 22:09 ` Stefan Hajnoczi
2023-11-02 11:08 ` Peter Maydell
0 siblings, 1 reply; 55+ messages in thread
From: Stefan Hajnoczi @ 2023-10-30 22:09 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
On Mon, 30 Oct 2023 at 19:09, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Sun, 29 Oct 2023 at 23:15, Stefan Hajnoczi <stefanha@gmail.com> wrote:
> >
> > On Fri, 27 Oct 2023 at 23:41, Peter Maydell <peter.maydell@linaro.org> wrote:
> > >
> > > Hi; here's the latest target-arm queue. Mostly this is refactoring
> > > and cleanup type patches.
>
> > Hi Peter,
> > I can't find this email thread on lore.kernel.org and your git repo
> > doesn't let me fetch the tag:
> >
> > $ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git
> > tags/pull-target-arm-20231027
> > fatal: couldn't find remote ref tags/pull-target-arm-20231027
>
> This works for me:
>
> $ git fetch https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20231027
> remote: Enumerating objects: 16753, done.
> remote: Counting objects: 100% (16753/16753), done.
> remote: Compressing objects: 100% (3181/3181), done.
> remote: Total 17529 (delta 14031), reused 16255 (delta 13541), pack-reused 776
> Receiving objects: 100% (17529/17529), 22.87 MiB | 10.44 MiB/s, done.
> Resolving deltas: 100% (14498/14498), completed with 1672 local objects.
> From https://git.linaro.org/people/pmaydell/qemu-arm
> * tag pull-target-arm-20231027 -> FETCH_HEAD
>
> > cgit shows the tag though, for some reason:
> > https://git.linaro.org/people/pmaydell/qemu-arm.git/tag/?h=pull-target-arm-20231027
> >
> > Any idea what's up with this pull request? Thanks!
>
> 'git.linaro.org' has several geolocated servers and pushes to
> it should get mirrored across to all of them. Maybe the
> syncing between them went wrong? You could try using one
> specific one:
> https://git-us.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20231027
>
> git-ie.linaro.org also seems to have the tag.
Yes, that solves the problem. DNS was resolving to git-ap.linaro.org
for me and it doesn't have the tag.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/41] target-arm queue
2023-10-27 14:39 Peter Maydell
2023-10-29 23:15 ` Stefan Hajnoczi
@ 2023-10-31 7:51 ` Stefan Hajnoczi
1 sibling, 0 replies; 55+ messages in thread
From: Stefan Hajnoczi @ 2023-10-31 7:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
On Fri, 27 Oct 2023 at 23:41, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Hi; here's the latest target-arm queue. Mostly this is refactoring
> and cleanup type patches.
Applied, thanks!
Stefan
>
> thanks
> -- PMM
>
> The following changes since commit c60be6e3e38cb36dc66129e757ec4b34152232be:
>
> Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging (2023-10-27 09:43:53 +0900)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027
>
> for you to fetch changes up to df93de987f423a0ed918c425f5dbd9a25d3c6229:
>
> hw/net/cadence_gem: enforce 32 bits variable size for CRC (2023-10-27 15:27:06 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Correct minor errors in Cortex-A710 definition
> * Implement Neoverse N2 CPU model
> * Refactor feature test functions out into separate header
> * Fix syndrome for FGT traps on ERET
> * Remove 'hw/arm/boot.h' includes from various header files
> * pxa2xx: Refactoring/cleanup
> * Avoid using 'first_cpu' when first ARM CPU is reachable
> * misc/led: LED state is set opposite of what is expected
> * hw/net/cadence_gen: clean up to use FIELD macros
> * hw/net/cadence_gem: perform PHY access on write only
> * hw/net/cadence_gem: enforce 32 bits variable size for CRC
>
> ----------------------------------------------------------------
> Glenn Miles (1):
> misc/led: LED state is set opposite of what is expected
>
> Luc Michel (11):
> hw/net/cadence_gem: use REG32 macro for register definitions
> hw/net/cadence_gem: use FIELD for screening registers
> hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
> hw/net/cadence_gem: use FIELD to describe NWCFG register fields
> hw/net/cadence_gem: use FIELD to describe DMACFG register fields
> hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
> hw/net/cadence_gem: use FIELD to describe IRQ register fields
> hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
> hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
> hw/net/cadence_gem: perform PHY access on write only
> hw/net/cadence_gem: enforce 32 bits variable size for CRC
>
> Peter Maydell (9):
> target/arm: Correct minor errors in Cortex-A710 definition
> target/arm: Implement Neoverse N2 CPU model
> target/arm: Move feature test functions to their own header
> target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together
> target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2
> target/arm: Move ID_AA64ISAR* test functions together
> target/arm: Move ID_AA64PFR* tests together
> target/arm: Move ID_AA64DFR* feature tests together
> target/arm: Fix syndrome for FGT traps on ERET
>
> Philippe Mathieu-Daudé (20):
> hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header
> hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header
> hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header
> hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
> hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header
> hw/sd/pxa2xx: Realize sysbus device before accessing it
> hw/sd/pxa2xx: Do not open-code sysbus_create_simple()
> hw/pcmcia/pxa2xx: Realize sysbus device before accessing it
> hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()
> hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()
> hw/intc/pxa2xx: Convert to Resettable interface
> hw/intc/pxa2xx: Pass CPU reference using QOM link property
> hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()
> hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it
> hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable
>
> docs/system/arm/virt.rst | 1 +
> bsd-user/arm/target_arch.h | 1 +
> include/hw/arm/allwinner-a10.h | 1 -
> include/hw/arm/allwinner-h3.h | 1 -
> include/hw/arm/allwinner-r40.h | 1 -
> include/hw/arm/fsl-imx25.h | 1 -
> include/hw/arm/fsl-imx31.h | 1 -
> include/hw/arm/fsl-imx6.h | 1 -
> include/hw/arm/fsl-imx6ul.h | 1 -
> include/hw/arm/fsl-imx7.h | 1 -
> include/hw/arm/pxa.h | 2 -
> include/hw/arm/xlnx-versal.h | 1 -
> include/hw/arm/xlnx-zynqmp.h | 1 -
> linux-user/aarch64/target_prctl.h | 2 +
> target/arm/cpu-features.h | 994 ++++++++++++++++++++++++++++++++++++++
> target/arm/cpu.h | 971 -------------------------------------
> target/arm/internals.h | 1 +
> target/arm/tcg/translate.h | 2 +-
> hw/arm/armv7m.c | 1 +
> hw/arm/bananapi_m2u.c | 3 +-
> hw/arm/cubieboard.c | 1 +
> hw/arm/exynos4_boards.c | 7 +-
> hw/arm/imx25_pdk.c | 1 +
> hw/arm/kzm.c | 1 +
> hw/arm/mcimx6ul-evk.c | 1 +
> hw/arm/mcimx7d-sabre.c | 1 +
> hw/arm/orangepi.c | 3 +-
> hw/arm/pxa2xx.c | 17 +-
> hw/arm/pxa2xx_pic.c | 38 +-
> hw/arm/realview.c | 2 +-
> hw/arm/sabrelite.c | 1 +
> hw/arm/sbsa-ref.c | 1 +
> hw/arm/virt.c | 1 +
> hw/arm/xilinx_zynq.c | 2 +-
> hw/arm/xlnx-versal-virt.c | 1 +
> hw/arm/xlnx-zcu102.c | 1 +
> hw/intc/armv7m_nvic.c | 1 +
> hw/misc/led.c | 2 +-
> hw/net/cadence_gem.c | 884 ++++++++++++++++++---------------
> hw/pcmcia/pxa2xx.c | 15 -
> hw/sd/pxa2xx_mmci.c | 7 +-
> linux-user/aarch64/cpu_loop.c | 1 +
> linux-user/aarch64/signal.c | 1 +
> linux-user/arm/signal.c | 1 +
> linux-user/elfload.c | 4 +
> linux-user/mmap.c | 4 +
> target/arm/arch_dump.c | 1 +
> target/arm/cpu.c | 1 +
> target/arm/cpu64.c | 1 +
> target/arm/debug_helper.c | 1 +
> target/arm/gdbstub.c | 1 +
> target/arm/helper.c | 1 +
> target/arm/kvm64.c | 1 +
> target/arm/machine.c | 1 +
> target/arm/ptw.c | 1 +
> target/arm/tcg/cpu64.c | 115 ++++-
> target/arm/tcg/hflags.c | 1 +
> target/arm/tcg/m_helper.c | 1 +
> target/arm/tcg/op_helper.c | 1 +
> target/arm/tcg/pauth_helper.c | 1 +
> target/arm/tcg/tlb_helper.c | 1 +
> target/arm/tcg/translate-a64.c | 4 +-
> target/arm/vfp_helper.c | 1 +
> 63 files changed, 1702 insertions(+), 1419 deletions(-)
> create mode 100644 target/arm/cpu-features.h
>
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/41] target-arm queue
2023-10-30 22:09 ` Stefan Hajnoczi
@ 2023-11-02 11:08 ` Peter Maydell
0 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2023-11-02 11:08 UTC (permalink / raw)
To: Stefan Hajnoczi; +Cc: qemu-devel
On Mon, 30 Oct 2023 at 22:09, Stefan Hajnoczi <stefanha@gmail.com> wrote:
>
> On Mon, 30 Oct 2023 at 19:09, Peter Maydell <peter.maydell@linaro.org> wrote:
> > 'git.linaro.org' has several geolocated servers and pushes to
> > it should get mirrored across to all of them. Maybe the
> > syncing between them went wrong? You could try using one
> > specific one:
> > https://git-us.linaro.org/people/pmaydell/qemu-arm.git
> > tags/pull-target-arm-20231027
> >
> > git-ie.linaro.org also seems to have the tag.
>
> Yes, that solves the problem. DNS was resolving to git-ap.linaro.org
> for me and it doesn't have the tag.
This was a problem with that specific mirror server;
it has been resolved, and future pulls with 'git.linaro.org'
should work as usual.
thanks
-- PMM
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/41] target-arm queue
@ 2024-01-11 11:04 Peter Maydell
2024-01-11 15:16 ` Peter Maydell
0 siblings, 1 reply; 55+ messages in thread
From: Peter Maydell @ 2024-01-11 11:04 UTC (permalink / raw)
To: qemu-devel
Mostly my FEAT_NV/NV2 stuff, but some other smaller series too.
-- PMM
The following changes since commit 9468484fe904ab4691de6d9c34616667f377ceac:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2024-01-09 10:32:23 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240111
for you to fetch changes up to e2862554c257e908a3833265e38365e794abd362:
target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs (2024-01-09 14:44:45 +0000)
----------------------------------------------------------------
target-arm queue:
* Emulate FEAT_NV, FEAT_NV2
* add cache controller for Freescale i.MX6
* Add minimal support for the B-L475E-IOT01A board
* Allow SoC models to configure M-profile CPUs with correct number
of NVIC priority bits
* Add missing QOM parent for v7-M SoCs
* Set CTR_EL0.{IDC,DIC} for the 'max' CPU
* hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers
----------------------------------------------------------------
Inès Varhol (2):
hw/arm: Add minimal support for the STM32L4x5 SoC
hw/arm: Add minimal support for the B-L475E-IOT01A board
Nikita Ostrenkov (1):
hw/arm: add cache controller for Freescale i.MX6
Peter Maydell (34):
target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU
hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers
target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV
target/arm: Implement HCR_EL2.AT handling
target/arm: Enable trapping of ERET for FEAT_NV
target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set
target/arm: Allow use of upper 32 bits of TBFLAG_A64
target/arm: Record correct opcode fields in cpreg for E2H aliases
target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0
target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses
target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check
target/arm: Trap sysreg accesses for FEAT_NV
target/arm: Make NV reads of CurrentEL return EL2
target/arm: Set SPSR_EL1.M correctly when nested virt is enabled
target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1}
target/arm: Always use arm_pan_enabled() when checking if PAN is enabled
target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1}
target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1
target/arm: Handle FEAT_NV page table attribute changes
target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs
target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits
target/arm: Implement VNCR_EL2 register
target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2
target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2
target/arm: Implement FEAT_NV2 redirection of sysregs to RAM
target/arm: Report VNCR_EL2 based faults correctly
target/arm: Mark up VNCR offsets (offsets 0x0..0xff)
target/arm: Mark up VNCR offsets (offsets 0x100..0x160)
target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8)
target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC)
hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers
target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps
target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry
target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs
Philippe Mathieu-Daudé (1):
hw/arm: Add missing QOM parent for v7-M SoCs
Samuel Tardieu (3):
hw/intc/armv7m_nvic: add "num-prio-bits" property
hw/arm/armv7m: alias the NVIC "num-prio-bits" property
hw/arm/socs: configure priority bits for existing SOCs
MAINTAINERS | 15 ++
docs/system/arm/b-l475e-iot01a.rst | 46 +++++
docs/system/arm/emulation.rst | 2 +
docs/system/arm/stm32.rst | 6 +-
docs/system/target-arm.rst | 1 +
configs/devices/arm-softmmu/default.mak | 1 +
include/hw/arm/armv7m.h | 1 +
include/hw/arm/stm32l4x5_soc.h | 57 ++++++
target/arm/cpregs.h | 54 +++++-
target/arm/cpu-features.h | 10 +
target/arm/cpu.h | 24 ++-
target/arm/syndrome.h | 20 +-
target/arm/tcg/translate.h | 16 +-
hw/arm/armv7m.c | 2 +
hw/arm/b-l475e-iot01a.c | 72 +++++++
hw/arm/fsl-imx6.c | 3 +
hw/arm/msf2-som.c | 1 +
hw/arm/netduino2.c | 1 +
hw/arm/netduinoplus2.c | 1 +
hw/arm/olimex-stm32-h405.c | 1 +
hw/arm/stellaris.c | 2 +
hw/arm/stm32f100_soc.c | 1 +
hw/arm/stm32f205_soc.c | 1 +
hw/arm/stm32f405_soc.c | 1 +
hw/arm/stm32l4x5_soc.c | 266 ++++++++++++++++++++++++++
hw/arm/stm32vldiscovery.c | 1 +
hw/intc/arm_gicv3_cpuif.c | 28 ++-
hw/intc/armv7m_nvic.c | 23 ++-
target/arm/cpu.c | 8 +-
target/arm/debug_helper.c | 13 +-
target/arm/helper.c | 326 +++++++++++++++++++++++++++++---
target/arm/ptw.c | 21 ++
target/arm/tcg/cpu64.c | 11 ++
target/arm/tcg/hflags.c | 30 ++-
target/arm/tcg/op_helper.c | 16 +-
target/arm/tcg/tlb_helper.c | 27 ++-
target/arm/tcg/translate-a64.c | 160 ++++++++++++++--
hw/arm/Kconfig | 12 ++
hw/arm/meson.build | 2 +
39 files changed, 1203 insertions(+), 80 deletions(-)
create mode 100644 docs/system/arm/b-l475e-iot01a.rst
create mode 100644 include/hw/arm/stm32l4x5_soc.h
create mode 100644 hw/arm/b-l475e-iot01a.c
create mode 100644 hw/arm/stm32l4x5_soc.c
^ permalink raw reply [flat|nested] 55+ messages in thread
* Re: [PULL 00/41] target-arm queue
2024-01-11 11:04 Peter Maydell
@ 2024-01-11 15:16 ` Peter Maydell
0 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2024-01-11 15:16 UTC (permalink / raw)
To: qemu-devel
On Thu, 11 Jan 2024 at 11:05, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Mostly my FEAT_NV/NV2 stuff, but some other smaller series too.
>
> -- PMM
>
> The following changes since commit 9468484fe904ab4691de6d9c34616667f377ceac:
>
> Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2024-01-09 10:32:23 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240111
>
> for you to fetch changes up to e2862554c257e908a3833265e38365e794abd362:
>
> target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs (2024-01-09 14:44:45 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Emulate FEAT_NV, FEAT_NV2
> * add cache controller for Freescale i.MX6
> * Add minimal support for the B-L475E-IOT01A board
> * Allow SoC models to configure M-profile CPUs with correct number
> of NVIC priority bits
> * Add missing QOM parent for v7-M SoCs
> * Set CTR_EL0.{IDC,DIC} for the 'max' CPU
> * hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 00/41] target-arm queue
@ 2025-02-20 16:20 Peter Maydell
2025-02-20 16:20 ` [PULL 01/41] target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1 Peter Maydell
` (41 more replies)
0 siblings, 42 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
Hi; this pullreq contains a new board model npcm845-evb, plus some
more minor cleanups, refactorings and a few bugfixes.
thanks
-- PMM
The following changes since commit 40efe733e10cc00e4fb4f9f5790a28e744e63c62:
Merge tag 'pull-tcg-20250215-3' of https://gitlab.com/rth7680/qemu into staging (2025-02-19 08:36:45 +0800)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250220
for you to fetch changes up to 1c3169179b8242866316108386800379c4e22974:
docs/system/arm: Add Description for NPCM8XX SoC (2025-02-20 15:22:22 +0000)
----------------------------------------------------------------
target-arm queue:
* Fix some incorrect syndrome values in various sysreg traps
* Clean up sysreg trap code to avoid similar future bugs
* Make boards/SoCs using a9mpcore and a15mpcore objects specify
number of GIC interrupts explicitly
* Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX
* target/arm: Use uint32_t in t32_expandimm_imm()
* New board model: NPCM845 Evaluation board "npcm845-evb"
----------------------------------------------------------------
Bernhard Beschow (1):
Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX
Hao Wu (17):
roms: Update vbootrom to 1287b6e
pc-bios: Add NPCM8XX vBootrom
hw/ssi: Make flash size a property in NPCM7XX FIU
hw/misc: Rename npcm7xx_gcr to npcm_gcr
hw/misc: Move NPCM7XX GCR to NPCM GCR
hw/misc: Add nr_regs and cold_reset_values to NPCM GCR
hw/misc: Add support for NPCM8XX GCR
hw/misc: Store DRAM size in NPCM8XX GCR Module
hw/misc: Support 8-bytes memop in NPCM GCR module
hw/misc: Rename npcm7xx_clk to npcm_clk
hw/misc: Move NPCM7XX CLK to NPCM CLK
hw/misc: Add nr_regs and cold_reset_values to NPCM CLK
hw/misc: Support NPCM8XX CLK Module Registers
hw/net: Add NPCM8XX PCS Module
hw/arm: Add NPCM8XX SoC
hw/arm: Add NPCM845 Evaluation board
docs/system/arm: Add Description for NPCM8XX SoC
Peter Maydell (14):
target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1
target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS
target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3
target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0
target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps
hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3
target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes
hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64()
target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult
target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1
target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps
target/arm: Remove CP_ACCESS_TRAP handling
target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED
target/arm: Correct errors in WFI/WFE trapping
Philippe Mathieu-Daudé (8):
hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition
hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs
hw/arm/realview: Specify explicitly the GIC has 64 external IRQs
hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL
hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs
hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs
hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs
hw/cpu/arm_mpcore: Remove default values for GIC external IRQs
Stephen Longfield (1):
target/arm: Use uint32_t in t32_expandimm_imm()
MAINTAINERS | 1 +
docs/system/arm/nuvoton.rst | 27 +-
configs/devices/aarch64-softmmu/default.mak | 1 +
include/hw/arm/npcm7xx.h | 8 +-
include/hw/arm/npcm8xx.h | 127 ++++
include/hw/misc/{npcm7xx_clk.h => npcm_clk.h} | 47 +-
include/hw/misc/{npcm7xx_gcr.h => npcm_gcr.h} | 29 +-
include/hw/net/npcm_pcs.h | 42 ++
include/hw/ssi/npcm7xx_fiu.h | 1 +
target/arm/cpregs.h | 15 +-
target/arm/cpu.h | 6 +
hw/arm/exynos4210.c | 10 +-
hw/arm/highbank.c | 8 +-
hw/arm/npcm7xx.c | 6 +
hw/arm/npcm8xx.c | 805 ++++++++++++++++++++++++++
hw/arm/npcm8xx_boards.c | 254 ++++++++
hw/arm/realview.c | 11 +-
hw/arm/vexpress.c | 7 +-
hw/arm/xilinx_zynq.c | 43 +-
hw/cpu/a15mpcore.c | 18 +-
hw/cpu/a9mpcore.c | 18 +-
hw/intc/arm_gicv3_cpuif.c | 15 +-
hw/misc/npcm7xx_gcr.c | 264 ---------
hw/misc/{npcm7xx_clk.c => npcm_clk.c} | 235 ++++++--
hw/misc/npcm_gcr.c | 482 +++++++++++++++
hw/net/npcm_pcs.c | 410 +++++++++++++
hw/ssi/npcm7xx_fiu.c | 16 +-
target/arm/debug_helper.c | 5 +-
target/arm/helper.c | 75 ++-
target/arm/tcg/op_helper.c | 71 ++-
target/arm/tcg/translate.c | 2 +-
hw/arm/Kconfig | 19 +-
hw/arm/meson.build | 1 +
hw/misc/meson.build | 4 +-
hw/misc/trace-events | 12 +-
hw/net/meson.build | 1 +
hw/net/trace-events | 4 +-
hw/usb/Kconfig | 4 +
hw/usb/meson.build | 2 +-
pc-bios/README | 8 +-
pc-bios/meson.build | 1 +
pc-bios/npcm7xx_bootrom.bin | Bin 768 -> 768 bytes
pc-bios/npcm8xx_bootrom.bin | Bin 0 -> 608 bytes
roms/Makefile | 6 +
roms/vbootrom | 2 +-
45 files changed, 2626 insertions(+), 497 deletions(-)
create mode 100644 include/hw/arm/npcm8xx.h
rename include/hw/misc/{npcm7xx_clk.h => npcm_clk.h} (83%)
rename include/hw/misc/{npcm7xx_gcr.h => npcm_gcr.h} (76%)
create mode 100644 include/hw/net/npcm_pcs.h
create mode 100644 hw/arm/npcm8xx.c
create mode 100644 hw/arm/npcm8xx_boards.c
delete mode 100644 hw/misc/npcm7xx_gcr.c
rename hw/misc/{npcm7xx_clk.c => npcm_clk.c} (82%)
create mode 100644 hw/misc/npcm_gcr.c
create mode 100644 hw/net/npcm_pcs.c
create mode 100644 pc-bios/npcm8xx_bootrom.bin
^ permalink raw reply [flat|nested] 55+ messages in thread
* [PULL 01/41] target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 02/41] target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS Peter Maydell
` (40 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
The access pseudocode for the CNTPS_TVAL_EL1, CNTPS_CTL_EL1 and
CNTPS_CVAL_EL1 secure timer registers says that they are UNDEFINED
from EL2 or NS EL1. We incorrectly return CP_ACCESS_TRAP from the
access function in these cases, which means that we report the wrong
syndrome value to the target EL.
Use CP_ACCESS_TRAP_UNCATEGORIZED, which reports the correct syndrome
value for an UNDEFINED instruction.
Cc: qemu-stable@nongnu.org
Fixes: b4d3978c2fd ("target-arm: Add the AArch64 view of the Secure physical timer")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-2-peter.maydell@linaro.org
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7d95eae9971..b7d6afe0a1a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2385,7 +2385,7 @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
switch (arm_current_el(env)) {
case 1:
if (!arm_is_secure(env)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
}
if (!(env->cp15.scr_el3 & SCR_ST)) {
return CP_ACCESS_TRAP_EL3;
@@ -2393,7 +2393,7 @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
return CP_ACCESS_OK;
case 0:
case 2:
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
case 3:
return CP_ACCESS_OK;
default:
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 02/41] target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
2025-02-20 16:20 ` [PULL 01/41] target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1 Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 03/41] target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3 Peter Maydell
` (39 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
R_NYXTL says that these AT insns should be UNDEFINED if they
would operate on an EL lower than EL3 and SCR_EL3.{NSE,NS} is
set to the Reserved {1, 0}. We were incorrectly reporting
them with the wrong syndrome; use CP_ACCESS_TRAP_UNCATEGORIZED
so they are reported as UNDEFINED.
Cc: qemu-stable@nongnu.org
Fixes: 1acd00ef1410 ("target/arm/helper: Check SCR_EL3.{NSE, NS} encoding for AT instructions")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-3-peter.maydell@linaro.org
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b7d6afe0a1a..9ed1a67b767 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3601,7 +3601,7 @@ static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri,
* scr_write() ensures that the NSE bit is not set otherwise.
*/
if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
}
return CP_ACCESS_OK;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 03/41] target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
2025-02-20 16:20 ` [PULL 01/41] target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1 Peter Maydell
2025-02-20 16:20 ` [PULL 02/41] target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 04/41] target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0 Peter Maydell
` (38 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
The pseudocode for AT S1E2R and AT S1E2W says that they should be
UNDEFINED if executed at EL3 when EL2 is not enabled. We were
incorrectly using CP_ACCESS_TRAP and reporting the wrong exception
syndrome as a result. Use CP_ACCESS_TRAP_UNCATEGORIZED.
Cc: qemu-stable@nongnu.org
Fixes: 2a47df953202e1 ("target-arm: Wire up AArch64 EL2 and EL3 address translation ops")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-4-peter.maydell@linaro.org
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9ed1a67b767..f4af2d2de54 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3611,7 +3611,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
{
if (arm_current_el(env) == 3 &&
!(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
}
return at_e012_access(env, ri, isread);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 04/41] target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2025-02-20 16:20 ` [PULL 03/41] target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3 Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 05/41] target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps Peter Maydell
` (37 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
The pseudocode for the accessors for the LOR sysregs says they
are UNDEFINED if SCR_EL3.NS is 0. We were reporting the wrong
syndrome value here; use CP_ACCESS_TRAP_UNCATEGORIZED.
Cc: qemu-stable@nongnu.org
Fixes: 2d7137c10faf ("target/arm: Implement the ARMv8.1-LOR extension")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-5-peter.maydell@linaro.org
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f4af2d2de54..4a0db087dd0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6750,8 +6750,8 @@ static CPAccessResult access_lor_other(CPUARMState *env,
const ARMCPRegInfo *ri, bool isread)
{
if (arm_is_secure_below_el3(env)) {
- /* Access denied in secure mode. */
- return CP_ACCESS_TRAP;
+ /* UNDEF if SCR_EL3.NS == 0 */
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
}
return access_lor_ns(env, ri, isread);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 05/41] target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2025-02-20 16:20 ` [PULL 04/41] target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0 Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 06/41] hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3 Peter Maydell
` (36 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
In system register access pseudocode the common pattern for
AArch32 registers with access traps to EL3 is:
at EL1 and EL2:
if HaveEL(EL3) && !ELUsingAArch32(EL3) && (SCR_EL3.TERR == 1) then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && (SCR.TERR == 1) then
AArch32.TakeMonitorTrapException();
at EL3:
if (PSTATE.M != M32_Monitor) && (SCR.TERR == 1) then
AArch32.TakeMonitorTrapException();
(taking as an example the ERRIDR access pseudocode).
This implements the behaviour of (in this case) SCR.TERR that
"Accesses to the specified registers from modes other than Monitor
mode generate a Monitor Trap exception" and of SCR_EL3.TERR that
"Accesses of the specified Error Record registers at EL2 and EL1
are trapped to EL3, unless the instruction generates a higher
priority exception".
In QEMU we don't implement this pattern correctly in two ways:
* in access_check_cp_reg() we turn the CP_ACCESS_TRAP_EL3 into
an UNDEF, not a trap to Monitor mode
* in the access functions, we check trap bits like SCR.TERR
only when arm_current_el(env) < 3 -- this is correct for
AArch64 EL3, but misses the "trap non-Monitor-mode execution
at EL3 into Monitor mode" case for AArch32 EL3
In this commit we fix the first of these two issues, by
making access_check_cp_reg() handle CP_ACCESS_TRAP_EL3
as a Monitor trap. This is a kind of exception that we haven't
yet implemented(!), so we need a new EXCP_MON_TRAP for it.
This diverges from the pseudocode approach, where every access check
function explicitly checks for "if EL3 is AArch32" and takes a
monitor trap; if we wanted to be closer to the pseudocode we could
add a new CP_ACCESS_TRAP_MONITOR and make all the accessfns use it
when appropriate. But because there are no non-standard cases in the
pseudocode (i.e. where either it raises a Monitor trap that doesn't
correspond to an AArch64 SystemAccessTrap or where it raises a
SystemAccessTrap that doesn't correspond to a Monitor trap), handling
this all in one place seems less likely to result in future bugs
where we forgot again about this special case when writing an
accessor.
(The cc of stable here is because "hw/intc/arm_gicv3_cpuif: Don't
downgrade monitor traps for AArch32 EL3" which is also cc:stable
will implicitly use the new EXCP_MON_TRAP code path.)
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-6-peter.maydell@linaro.org
---
target/arm/cpu.h | 1 +
target/arm/helper.c | 11 +++++++++++
target/arm/tcg/op_helper.c | 13 ++++++++++++-
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 6f6cf5c888b..83ceaa58c2c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -62,6 +62,7 @@
#define EXCP_NMI 26
#define EXCP_VINMI 27
#define EXCP_VFNMI 28
+#define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */
/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
#define ARMV7M_EXCP_RESET 1
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4a0db087dd0..2bf39a2051d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9684,6 +9684,7 @@ void arm_log_exception(CPUState *cs)
[EXCP_NMI] = "NMI",
[EXCP_VINMI] = "Virtual IRQ NMI",
[EXCP_VFNMI] = "Virtual FIQ NMI",
+ [EXCP_MON_TRAP] = "Monitor Trap",
};
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
@@ -10250,6 +10251,16 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
mask = CPSR_A | CPSR_I | CPSR_F;
offset = 0;
break;
+ case EXCP_MON_TRAP:
+ new_mode = ARM_CPU_MODE_MON;
+ addr = 0x04;
+ mask = CPSR_A | CPSR_I | CPSR_F;
+ if (env->thumb) {
+ offset = 2;
+ } else {
+ offset = 4;
+ }
+ break;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 1161d301b71..1ba727e8e9f 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -758,6 +758,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key);
CPAccessResult res = CP_ACCESS_OK;
int target_el;
+ uint32_t excp;
assert(ri != NULL);
@@ -851,8 +852,18 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
}
fail:
+ excp = EXCP_UDEF;
switch (res & ~CP_ACCESS_EL_MASK) {
case CP_ACCESS_TRAP:
+ /*
+ * If EL3 is AArch32 then there's no syndrome register; the cases
+ * where we would raise a SystemAccessTrap to AArch64 EL3 all become
+ * raising a Monitor trap exception. (Because there's no visible
+ * syndrome it doesn't matter what we pass to raise_exception().)
+ */
+ if ((res & CP_ACCESS_EL_MASK) == 3 && !arm_el_is_aa64(env, 3)) {
+ excp = EXCP_MON_TRAP;
+ }
break;
case CP_ACCESS_TRAP_UNCATEGORIZED:
/* Only CP_ACCESS_TRAP traps are direct to a specified EL */
@@ -888,7 +899,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
g_assert_not_reached();
}
- raise_exception(env, EXCP_UDEF, syndrome, target_el);
+ raise_exception(env, excp, syndrome, target_el);
}
const void *HELPER(lookup_cp_reg)(CPUARMState *env, uint32_t key)
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 06/41] hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2025-02-20 16:20 ` [PULL 05/41] target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 07/41] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes Peter Maydell
` (35 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
In the gicv3_{irq,fiq,irqfiq}_access() functions, there is a check
which downgrades a CP_ACCESS_TRAP_EL3 to CP_ACCESS_TRAP if EL3 is not
AArch64. This has been there since the GIC was first implemented,
but it isn't right: if we are trapping because of SCR.IRQ or SCR.FIQ
then we definitely want to be going to EL3 (doing
AArch32.TakeMonitorTrapException() in pseudocode terms). We might
want to not take a trap at all, but we don't ever want to go to the
default target EL, because that would mean, for instance, taking a
trap to Hyp mode if the trapped access was made from Hyp mode.
(This might have been an attempt to work around our failure to
properly implement Monitor Traps.)
Remove the bogus check.
Cc: qemu-stable@nongnu.org
Fixes: 359fbe65e01e ("hw/intc/arm_gicv3: Implement GICv3 CPU interface registers")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-7-peter.maydell@linaro.org
---
hw/intc/arm_gicv3_cpuif.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 9cad8313a3a..8a715b3510b 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -2300,9 +2300,6 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env,
}
}
- if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) {
- r = CP_ACCESS_TRAP;
- }
return r;
}
@@ -2365,9 +2362,6 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env,
}
}
- if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) {
- r = CP_ACCESS_TRAP;
- }
return r;
}
@@ -2404,9 +2398,6 @@ static CPAccessResult gicv3_irq_access(CPUARMState *env,
}
}
- if (r == CP_ACCESS_TRAP_EL3 && !arm_el_is_aa64(env, 3)) {
- r = CP_ACCESS_TRAP;
- }
return r;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 07/41] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2025-02-20 16:20 ` [PULL 06/41] hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3 Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 08/41] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64() Peter Maydell
` (34 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
There are not many traps in AArch32 which should trap to Monitor
mode, but these trap bits should trap not just lower ELs to Monitor
mode but also the non-Monitor modes running at EL3 (i.e. Secure
System, Secure Undef, etc).
We get this wrong because the relevant access functions implement the
AArch64-style logic of
if (el < 3 && trap_bit_set) {
return CP_ACCESS_TRAP_EL3;
}
which won't trap the non-Monitor modes at EL3.
Correct this error by using arm_is_el3_or_mon() instead, which
returns true when the CPU is at AArch64 EL3 or AArch32 Monitor mode.
(Since the new callsites are compiled also for the linux-user mode,
we need to provide a dummy implementation for CONFIG_USER_ONLY.)
This affects only:
* trapping of ERRIDR via SCR.TERR
* trapping of the debug channel registers via SDCR.TDCC
* trapping of GICv3 registers via SCR.IRQ and SCR.FIQ
(which we already used arm_is_el3_or_mon() for)
This patch changes the handling of SCR.TERR and SDCR.TDCC. This
patch only changes guest-visible behaviour for "-cpu max" on
the qemu-system-arm binary, because SCR.TERR
and SDCR.TDCC (and indeed the entire SDCR register) only arrived
in Armv8, and the only guest CPU we support which has any v8
features and also starts in AArch32 EL3 is the 32-bit 'max'.
Other uses of CP_ACCESS_TRAP_EL3 don't need changing:
* uses in code paths that can't happen when EL3 is AArch32:
access_trap_aa32s_el1, cpacr_access, cptr_access, nsacr_access
* uses which are in accessfns for AArch64-only registers:
gt_stimer_access, gt_cntpoff_access, access_hxen, access_tpidr2,
access_smpri, access_smprimap, access_lor_ns, access_pauth,
access_mte, access_tfsr_el2, access_scxtnum, access_fgt
* trap bits which exist only in the AArch64 version of the
trap register, not the AArch32 one:
access_tpm, pmreg_access, access_dbgvcr32, access_tdra,
access_tda, access_tdosa (TPM, TDA and TDOSA exist only in
MDCR_EL3, not in SDCR, and we enforce this in sdcr_write())
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-8-peter.maydell@linaro.org
---
target/arm/cpu.h | 5 +++++
target/arm/debug_helper.c | 3 ++-
target/arm/helper.c | 2 +-
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 83ceaa58c2c..215845c7e25 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2596,6 +2596,11 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
return false;
}
+static inline bool arm_is_el3_or_mon(CPUARMState *env)
+{
+ return false;
+}
+
static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
{
return ARMSS_NonSecure;
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 2212ef4a3b9..c3c1eb5f628 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -880,7 +880,8 @@ static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
return CP_ACCESS_TRAP_EL2;
}
- if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
+ if (!arm_is_el3_or_mon(env) &&
+ ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_OK;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2bf39a2051d..535870f69a6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6103,7 +6103,7 @@ static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
return CP_ACCESS_TRAP_EL2;
}
- if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
+ if (!arm_is_el3_or_mon(env) && (env->cp15.scr_el3 & SCR_TERR)) {
return CP_ACCESS_TRAP_EL3;
}
return CP_ACCESS_OK;
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 08/41] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64()
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2025-02-20 16:20 ` [PULL 07/41] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 09/41] target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult Peter Maydell
` (33 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
In the gicv3_{irq,fiq,irqfiq}_access() functions, in the
arm_current_el(env) == 3 case we do the following test:
if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
r = CP_ACCESS_TRAP_EL3;
}
In this check, the "!is_a64(env)" is redundant, because if
we are at EL3 and in AArch64 then arm_is_el3_or_mon() will
return true and we will skip the if() body anyway.
Remove the unnecessary tests.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-9-peter.maydell@linaro.org
---
hw/intc/arm_gicv3_cpuif.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 8a715b3510b..7f1d071c198 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -2291,7 +2291,7 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env,
r = CP_ACCESS_TRAP_EL3;
break;
case 3:
- if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
+ if (!arm_is_el3_or_mon(env)) {
r = CP_ACCESS_TRAP_EL3;
}
break;
@@ -2353,7 +2353,7 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env,
r = CP_ACCESS_TRAP_EL3;
break;
case 3:
- if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
+ if (!arm_is_el3_or_mon(env)) {
r = CP_ACCESS_TRAP_EL3;
}
break;
@@ -2389,7 +2389,7 @@ static CPAccessResult gicv3_irq_access(CPUARMState *env,
r = CP_ACCESS_TRAP_EL3;
break;
case 3:
- if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
+ if (!arm_is_el3_or_mon(env)) {
r = CP_ACCESS_TRAP_EL3;
}
break;
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 09/41] target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2025-02-20 16:20 ` [PULL 08/41] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64() Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 10/41] target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1 Peter Maydell
` (32 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
In the CPAccessResult enum, the CP_ACCESS_TRAP* values indicate the
equivalent of the pseudocode AArch64.SystemAccessTrap(..., 0x18),
causing a trap to a specified exception level with a syndrome value
giving information about the failing instructions. In the
pseudocode, such traps are always taken to a specified target EL. We
support that for target EL of 2 or 3 via CP_ACCESS_TRAP_EL2 and
CP_ACCESS_TRAP_EL3, but the only way to take the access trap to EL1
currently is to use CP_ACCESS_TRAP, which takes the trap to the
"usual target EL" (EL1 if in EL0, otherwise to the current EL).
Add CP_ACCESS_TRAP_EL1 so that access functions can follow the
pseudocode more closely.
(Note that for the common case in the pseudocode of "trap to
EL2 if HCR_EL2.TGE is set, otherwise trap to EL1", we handle
this in raise_exception(), so access functions don't need to
special case it and can use CP_ACCESS_TRAP_EL1.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-10-peter.maydell@linaro.org
---
target/arm/cpregs.h | 1 +
target/arm/tcg/op_helper.c | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 1759d9defbe..fbf5798069d 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -331,6 +331,7 @@ typedef enum CPAccessResult {
* 0xc or 0x18).
*/
CP_ACCESS_TRAP = (1 << 2),
+ CP_ACCESS_TRAP_EL1 = CP_ACCESS_TRAP | 1,
CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 1ba727e8e9f..c427118655d 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -781,7 +781,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
* the other trap takes priority. So we take the "check HSTR_EL2" path
* for all of those cases.)
*/
- if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) == 0) &&
+ if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) < 2) &&
arm_current_el(env) == 0) {
goto fail;
}
@@ -887,6 +887,9 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
case 0:
target_el = exception_target_el(env);
break;
+ case 1:
+ assert(arm_current_el(env) < 2);
+ break;
case 2:
assert(arm_current_el(env) != 3);
assert(arm_is_el2_enabled(env));
@@ -895,7 +898,6 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
assert(arm_feature(env, ARM_FEATURE_EL3));
break;
default:
- /* No "direct" traps to EL1 */
g_assert_not_reached();
}
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 10/41] target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2025-02-20 16:20 ` [PULL 09/41] target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 11/41] target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps Peter Maydell
` (31 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
We currently use CP_ACCESS_TRAP in a number of access functions where
we know we're currently at EL0; in this case the "usual target EL"
is EL1, so CP_ACCESS_TRAP and CP_ACCESS_TRAP_EL1 behave the same.
Use CP_ACCESS_TRAP_EL1 to more closely match the pseudocode for
this sort of check.
Note that in the case of the access functions foc cacheop to
PoC or PoU, the code was correct but the comment was wrong:
SCTLR_EL1.UCI traps for DC CVAC, DC CIVAC, DC CVAP, DC CVADP,
DC CVAU and IC IVAU should be system access traps, not UNDEFs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-11-peter.maydell@linaro.org
---
target/arm/debug_helper.c | 2 +-
target/arm/helper.c | 30 +++++++++++++++---------------
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index c3c1eb5f628..36bffde74e9 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -875,7 +875,7 @@ static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
(env->cp15.mdcr_el3 & MDCR_TDCC);
if (el < 1 && mdscr_el1_tdcc) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
return CP_ACCESS_TRAP_EL2;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 535870f69a6..aacb53d31a2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -881,7 +881,7 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
if (el < 2 && (mdcr_el2 & MDCR_TPM)) {
return CP_ACCESS_TRAP_EL2;
@@ -2159,7 +2159,7 @@ static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_current_el(env) == 0 && (env->teecr & 1)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
return teecr_access(env, ri, isread);
}
@@ -2239,7 +2239,7 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
cntkctl = env->cp15.c14_cntkctl;
}
if (!extract32(cntkctl, 0, 2)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
break;
case 1:
@@ -2278,7 +2278,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
/* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
/* fall through */
case 1:
@@ -2319,7 +2319,7 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
* EL0 if EL0[PV]TEN is zero.
*/
if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
/* fall through */
@@ -4499,7 +4499,7 @@ static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
return CP_ACCESS_OK;
}
@@ -4589,9 +4589,9 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
/* Cache invalidate/clean to Point of Coherency or Persistence... */
switch (arm_current_el(env)) {
case 0:
- /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
+ /* ... EL0 must trap to EL1 unless SCTLR_EL1.UCI is set. */
if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
/* fall through */
case 1:
@@ -4609,9 +4609,9 @@ static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags)
/* Cache invalidate/clean to Point of Unification... */
switch (arm_current_el(env)) {
case 0:
- /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
+ /* ... EL0 must trap to EL1 unless SCTLR_EL1.UCI is set. */
if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
/* fall through */
case 1:
@@ -4651,7 +4651,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
}
} else {
if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
if (hcr & HCR_TDZ) {
return CP_ACCESS_TRAP_EL2;
@@ -6073,7 +6073,7 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
}
} else {
if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
if (hcr & HCR_TID2) {
return CP_ACCESS_TRAP_EL2;
@@ -6372,7 +6372,7 @@ static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri,
if (el == 0) {
uint64_t sctlr = arm_sctlr(env, el);
if (!(sctlr & SCTLR_EnTP2)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
}
/* TODO: FEAT_FGT */
@@ -7172,7 +7172,7 @@ static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
if (hcr & HCR_TGE) {
return CP_ACCESS_TRAP_EL2;
}
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
} else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
return CP_ACCESS_TRAP_EL2;
@@ -7292,7 +7292,7 @@ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
if (el == 0) {
uint64_t sctlr = arm_sctlr(env, el);
if (!(sctlr & SCTLR_EnRCTX)) {
- return CP_ACCESS_TRAP;
+ return CP_ACCESS_TRAP_EL1;
}
} else if (el == 1) {
uint64_t hcr = arm_hcr_el2_eff(env);
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 11/41] target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2025-02-20 16:20 ` [PULL 10/41] target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1 Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 12/41] target/arm: Remove CP_ACCESS_TRAP handling Peter Maydell
` (30 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
On XScale CPUs, there is no EL2 or AArch64, so no syndrome register.
These traps are just UNDEFs in the traditional AArch32 sense, so
CP_ACCESS_TRAP_UNCATEGORIZED is more accurate than CP_ACCESS_TRAP.
This has no visible behavioural change, because the guest doesn't
have a way to see the syndrome value we generate.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-12-peter.maydell@linaro.org
---
target/arm/tcg/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index c427118655d..c69d2ac643f 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -764,7 +764,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
&& extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
- res = CP_ACCESS_TRAP;
+ res = CP_ACCESS_TRAP_UNCATEGORIZED;
goto fail;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 12/41] target/arm: Remove CP_ACCESS_TRAP handling
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2025-02-20 16:20 ` [PULL 11/41] target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED Peter Maydell
` (29 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
There are no longer any uses of CP_ACCESS_TRAP in access functions,
because we have converted them all to use either CP_ACCESS_TRAP_EL1
or CP_ACCESS_TRAP_UNCATEGORIZED, as appropriate. Remove the handling
of bare CP_ACCESS_TRAP from the access_check_cp_reg() helper, so that
it now asserts if an access function returns a value requesting a
trap without a target EL.
Rename CP_ACCESS_TRAP to CP_ACCESS_TRAP_BIT, to make it clearer
that this is an internal-only definition, not something that
it makes sense to return from an access function. This should
help to avoid future bugs where we return the wrong syndrome
value by mistake.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-13-peter.maydell@linaro.org
---
target/arm/cpregs.h | 11 ++++++-----
target/arm/tcg/op_helper.c | 13 ++++++++-----
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index fbf5798069d..fb3b84baa1e 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -328,12 +328,13 @@ typedef enum CPAccessResult {
* Access fails due to a configurable trap or enable which would
* result in a categorized exception syndrome giving information about
* the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
- * 0xc or 0x18).
+ * 0xc or 0x18). These traps are always to a specified target EL,
+ * never to the usual target EL.
*/
- CP_ACCESS_TRAP = (1 << 2),
- CP_ACCESS_TRAP_EL1 = CP_ACCESS_TRAP | 1,
- CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
- CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
+ CP_ACCESS_TRAP_BIT = (1 << 2),
+ CP_ACCESS_TRAP_EL1 = CP_ACCESS_TRAP_BIT | 1,
+ CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP_BIT | 2,
+ CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP_BIT | 3,
/*
* Access fails and results in an exception syndrome 0x0 ("uncategorized").
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index c69d2ac643f..fcee11e29ad 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -853,21 +853,24 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
fail:
excp = EXCP_UDEF;
- switch (res & ~CP_ACCESS_EL_MASK) {
- case CP_ACCESS_TRAP:
+ switch (res) {
+ /* CP_ACCESS_TRAP* traps are always direct to a specified EL */
+ case CP_ACCESS_TRAP_EL3:
/*
* If EL3 is AArch32 then there's no syndrome register; the cases
* where we would raise a SystemAccessTrap to AArch64 EL3 all become
* raising a Monitor trap exception. (Because there's no visible
* syndrome it doesn't matter what we pass to raise_exception().)
*/
- if ((res & CP_ACCESS_EL_MASK) == 3 && !arm_el_is_aa64(env, 3)) {
+ if (!arm_el_is_aa64(env, 3)) {
excp = EXCP_MON_TRAP;
}
break;
+ case CP_ACCESS_TRAP_EL2:
+ case CP_ACCESS_TRAP_EL1:
+ break;
case CP_ACCESS_TRAP_UNCATEGORIZED:
- /* Only CP_ACCESS_TRAP traps are direct to a specified EL */
- assert((res & CP_ACCESS_EL_MASK) == 0);
+ /* CP_ACCESS_TRAP_UNCATEGORIZED is never direct to a specified EL */
if (cpu_isar_feature(aa64_ids, cpu) && isread &&
arm_cpreg_in_idspace(ri)) {
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2025-02-20 16:20 ` [PULL 12/41] target/arm: Remove CP_ACCESS_TRAP handling Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 14/41] target/arm: Correct errors in WFI/WFE trapping Peter Maydell
` (28 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
CP_ACCESS_TRAP_UNCATEGORIZED is technically an accurate description
of what this return value from a cpreg accessfn does, but it's liable
to confusion because it doesn't match how the Arm ARM pseudocode
indicates this case. What it does is an EXCP_UDEF with a zero
("uncategorized") syndrome value, which is what an UNDEFINED instruction
does. The pseudocode uses "UNDEFINED" to show this; rename our
constant to CP_ACCESS_UNDEFINED to make the parallel clearer.
Commit created with
sed -i -e 's/CP_ACCESS_TRAP_UNCATEGORIZED/CP_ACCESS_UNDEFINED/' $(git grep -l CP_ACCESS_TRAP_UNCATEGORIZED)
plus manual editing of the comment.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-14-peter.maydell@linaro.org
---
target/arm/cpregs.h | 5 +++--
target/arm/helper.c | 30 +++++++++++++++---------------
target/arm/tcg/op_helper.c | 6 +++---
3 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index fb3b84baa1e..52377c6eb50 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -337,13 +337,14 @@ typedef enum CPAccessResult {
CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP_BIT | 3,
/*
- * Access fails and results in an exception syndrome 0x0 ("uncategorized").
+ * Access fails with UNDEFINED, i.e. an exception syndrome 0x0
+ * ("uncategorized"), which is what an undefined insn produces.
* Note that this is not a catch-all case -- the set of cases which may
* result in this failure is specifically defined by the architecture.
* This trap is always to the usual target EL, never directly to a
* specified target EL.
*/
- CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
+ CP_ACCESS_UNDEFINED = (2 << 2),
} CPAccessResult;
/* Indexes into fgt_read[] */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index aacb53d31a2..71dead7241b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -285,7 +285,7 @@ static CPAccessResult access_el3_aa32ns(CPUARMState *env,
{
if (!is_a64(env) && arm_current_el(env) == 3 &&
arm_is_secure_below_el3(env)) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return CP_ACCESS_OK;
}
@@ -310,7 +310,7 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
return CP_ACCESS_TRAP_EL3;
}
/* This will be EL1 NS and EL2 NS, which just UNDEF */
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
/*
@@ -2246,7 +2246,7 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
if (!isread && ri->state == ARM_CP_STATE_AA32 &&
arm_is_secure_below_el3(env)) {
/* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
break;
case 2:
@@ -2255,7 +2255,7 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
}
if (!isread && el < arm_highest_el(env)) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return CP_ACCESS_OK;
@@ -2385,7 +2385,7 @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
switch (arm_current_el(env)) {
case 1:
if (!arm_is_secure(env)) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
if (!(env->cp15.scr_el3 & SCR_ST)) {
return CP_ACCESS_TRAP_EL3;
@@ -2393,7 +2393,7 @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
return CP_ACCESS_OK;
case 0:
case 2:
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
case 3:
return CP_ACCESS_OK;
default:
@@ -3304,7 +3304,7 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
}
return CP_ACCESS_TRAP_EL3;
}
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
}
return CP_ACCESS_OK;
@@ -3601,7 +3601,7 @@ static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri,
* scr_write() ensures that the NSE bit is not set otherwise.
*/
if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return CP_ACCESS_OK;
}
@@ -3611,7 +3611,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
{
if (arm_current_el(env) == 3 &&
!(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return at_e012_access(env, ri, isread);
}
@@ -4684,7 +4684,7 @@ static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
* Access to SP_EL0 is undefined if it's being used as
* the stack pointer.
*/
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return CP_ACCESS_OK;
}
@@ -5674,7 +5674,7 @@ static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri,
if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) {
return CP_ACCESS_OK;
}
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
@@ -5710,7 +5710,7 @@ static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
if (isread) {
return CP_ACCESS_OK;
}
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
static const ARMCPRegInfo el3_cp_reginfo[] = {
@@ -5798,7 +5798,7 @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return CP_ACCESS_OK;
}
@@ -5896,7 +5896,7 @@ static CPAccessResult el2_e2h_e12_access(CPUARMState *env,
}
/* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
if (ri->orig_accessfn) {
return ri->orig_accessfn(env, ri->opaque, isread);
@@ -6751,7 +6751,7 @@ static CPAccessResult access_lor_other(CPUARMState *env,
{
if (arm_is_secure_below_el3(env)) {
/* UNDEF if SCR_EL3.NS == 0 */
- return CP_ACCESS_TRAP_UNCATEGORIZED;
+ return CP_ACCESS_UNDEFINED;
}
return access_lor_ns(env, ri, isread);
}
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index fcee11e29ad..2230351a8f4 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -764,7 +764,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
&& extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
- res = CP_ACCESS_TRAP_UNCATEGORIZED;
+ res = CP_ACCESS_UNDEFINED;
goto fail;
}
@@ -869,8 +869,8 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
case CP_ACCESS_TRAP_EL2:
case CP_ACCESS_TRAP_EL1:
break;
- case CP_ACCESS_TRAP_UNCATEGORIZED:
- /* CP_ACCESS_TRAP_UNCATEGORIZED is never direct to a specified EL */
+ case CP_ACCESS_UNDEFINED:
+ /* CP_ACCESS_UNDEFINED is never direct to a specified EL */
if (cpu_isar_feature(aa64_ids, cpu) && isread &&
arm_cpreg_in_idspace(ri)) {
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 14/41] target/arm: Correct errors in WFI/WFE trapping
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2025-02-20 16:20 ` [PULL 13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 15/41] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Peter Maydell
` (27 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
The code for WFI/WFE trapping has several errors:
* it wasn't using arm_sctlr(), so it would look at SCTLR_EL1
even if the CPU was in the EL2&0 translation regime
* it was raising UNDEF, not Monitor Trap, for traps to
AArch32 EL3 because of SCR.{TWE,TWI}
* it was not honouring SCR.{TWE,TWI} when running in
AArch32 at EL3 not in Monitor mode
* it checked SCR.{TWE,TWI} even on v7 CPUs which don't have
those bits
Fix these bugs.
Cc: qemu-stable@nongnu.org
Fixes: b1eced713d99 ("target-arm: Add WFx instruction trap support")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-15-peter.maydell@linaro.org
---
target/arm/tcg/op_helper.c | 37 ++++++++++++++++++-------------------
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 2230351a8f4..02c375d196d 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -313,15 +313,19 @@ void HELPER(check_bxj_trap)(CPUARMState *env, uint32_t rm)
}
#ifndef CONFIG_USER_ONLY
-/* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
+/*
+ * Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
* The function returns the target EL (1-3) if the instruction is to be trapped;
* otherwise it returns 0 indicating it is not trapped.
+ * For a trap, *excp is updated with the EXCP_* trap type to use.
*/
-static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
+static inline int check_wfx_trap(CPUARMState *env, bool is_wfe, uint32_t *excp)
{
int cur_el = arm_current_el(env);
uint64_t mask;
+ *excp = EXCP_UDEF;
+
if (arm_feature(env, ARM_FEATURE_M)) {
/* M profile cores can never trap WFI/WFE. */
return 0;
@@ -331,18 +335,9 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
* WFx instructions being trapped to EL1. These trap bits don't exist in v7.
*/
if (cur_el < 1 && arm_feature(env, ARM_FEATURE_V8)) {
- int target_el;
-
mask = is_wfe ? SCTLR_nTWE : SCTLR_nTWI;
- if (arm_is_secure_below_el3(env) && !arm_el_is_aa64(env, 3)) {
- /* Secure EL0 and Secure PL1 is at EL3 */
- target_el = 3;
- } else {
- target_el = 1;
- }
-
- if (!(env->cp15.sctlr_el[target_el] & mask)) {
- return target_el;
+ if (!(arm_sctlr(env, cur_el) & mask)) {
+ return exception_target_el(env);
}
}
@@ -358,9 +353,12 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
}
/* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
- if (cur_el < 3) {
+ if (arm_feature(env, ARM_FEATURE_V8) && !arm_is_el3_or_mon(env)) {
mask = (is_wfe) ? SCR_TWE : SCR_TWI;
if (env->cp15.scr_el3 & mask) {
+ if (!arm_el_is_aa64(env, 3)) {
+ *excp = EXCP_MON_TRAP;
+ }
return 3;
}
}
@@ -383,7 +381,8 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
return;
#else
CPUState *cs = env_cpu(env);
- int target_el = check_wfx_trap(env, false);
+ uint32_t excp;
+ int target_el = check_wfx_trap(env, false, &excp);
if (cpu_has_work(cs)) {
/* Don't bother to go into our "low power state" if
@@ -399,7 +398,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len)
env->regs[15] -= insn_len;
}
- raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2),
+ raise_exception(env, excp, syn_wfx(1, 0xe, 0, insn_len == 2),
target_el);
}
@@ -424,7 +423,8 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout)
#else
ARMCPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
- int target_el = check_wfx_trap(env, false);
+ uint32_t excp;
+ int target_el = check_wfx_trap(env, false, &excp);
/* The WFIT should time out when CNTVCT_EL0 >= the specified value. */
uint64_t cntval = gt_get_countervalue(env);
uint64_t offset = gt_virt_cnt_offset(env);
@@ -441,8 +441,7 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout)
if (target_el) {
env->pc -= 4;
- raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, false),
- target_el);
+ raise_exception(env, excp, syn_wfx(1, 0xe, 0, false), target_el);
}
if (uadd64_overflow(timeout, offset, &nexttick)) {
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 15/41] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2025-02-20 16:20 ` [PULL 14/41] target/arm: Correct errors in WFI/WFE trapping Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 16/41] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs Peter Maydell
` (26 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
The 32 IRQ lines skipped are the GIC internal ones.
Use the GIC_INTERNAL definition for clarity.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/exynos4210.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index dd0edc81d5c..b6537a2d64a 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -394,7 +394,8 @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
}
if (irq_id) {
qdev_connect_gpio_out(splitter, splitin,
- qdev_get_gpio_in(extgicdev, irq_id - 32));
+ qdev_get_gpio_in(extgicdev,
+ irq_id - GIC_INTERNAL));
}
}
for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
@@ -421,7 +422,8 @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n));
qdev_connect_gpio_out(splitter, 1,
- qdev_get_gpio_in(extgicdev, irq_id - 32));
+ qdev_get_gpio_in(extgicdev,
+ irq_id - GIC_INTERNAL));
} else {
s->irq_table[n] = qdev_get_gpio_in(intcdev, n);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 16/41] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2025-02-20 16:20 ` [PULL 15/41] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 17/41] hw/arm/realview: " Peter Maydell
` (25 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"). Add the GIC_EXT_IRQS definition (with a comment)
to make that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/exynos4210.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index b6537a2d64a..b452470598b 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -103,6 +103,8 @@
#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
+#define GIC_EXT_IRQS 64 /* FIXME: verify for this SoC */
+
enum ExtGicId {
EXT_GIC_ID_MDMA_LCD0 = 66,
EXT_GIC_ID_PDMA0,
@@ -588,6 +590,8 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
/* Private memory region and Internal GIC */
qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
+ qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-irq",
+ GIC_EXT_IRQS + GIC_INTERNAL);
busdev = SYS_BUS_DEVICE(&s->a9mpcore);
sysbus_realize(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 17/41] hw/arm/realview: Specify explicitly the GIC has 64 external IRQs
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2025-02-20 16:20 ` [PULL 16/41] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:20 ` [PULL 18/41] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Peter Maydell
` (24 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"). Add the GIC_EXT_IRQS definition (with a comment)
to make that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/realview.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 436eef816ed..008eeaf049a 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -35,6 +35,8 @@
#define SMP_BOOT_ADDR 0xe0000000
#define SMP_BOOTREG_ADDR 0x10000030
+#define GIC_EXT_IRQS 64 /* Realview PBX-A9 development board */
+
/* Board init. */
static struct arm_boot_info realview_binfo = {
@@ -185,7 +187,12 @@ static void realview_init(MachineState *machine,
sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
if (is_mpcore) {
- dev = qdev_new(is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore");
+ if (is_pb) {
+ dev = qdev_new(TYPE_A9MPCORE_PRIV);
+ qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL);
+ } else {
+ dev = qdev_new("realview_mpcore");
+ }
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
@@ -201,7 +208,7 @@ static void realview_init(MachineState *machine,
/* For now just create the nIRQ GIC, and ignore the others. */
dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]);
}
- for (n = 0; n < 64; n++) {
+ for (n = 0; n < GIC_EXT_IRQS; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 18/41] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2025-02-20 16:20 ` [PULL 17/41] hw/arm/realview: " Peter Maydell
@ 2025-02-20 16:20 ` Peter Maydell
2025-02-20 16:21 ` [PULL 19/41] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs Peter Maydell
` (23 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:20 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
We already have a definition to distinct GIC internal
IRQs versus external ones, use it. No logical changes.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xilinx_zynq.c | 34 ++++++++++++++++------------------
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 3c6a4604cc9..22c0bb17262 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -54,8 +54,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
#define FLASH_SIZE (64 * 1024 * 1024)
#define FLASH_SECTOR_SIZE (128 * 1024)
-#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
-
#define MPCORE_PERIPHBASE 0xF8F00000
#define ZYNQ_BOARD_MIDR 0x413FC090
@@ -281,12 +279,12 @@ static void zynq_init(MachineState *machine)
pic[n] = qdev_get_gpio_in(dev, n);
}
- n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0);
- n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n);
- n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n);
+ n = zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false, 0);
+ n = zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false, n);
+ n = zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, n);
- sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
- sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
+ sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]);
+ sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]);
dev = qdev_new(TYPE_CADENCE_UART);
busdev = SYS_BUS_DEVICE(dev);
@@ -295,7 +293,7 @@ static void zynq_init(MachineState *machine)
qdev_get_clock_out(slcr, "uart0_ref_clk"));
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xE0000000);
- sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
+ sysbus_connect_irq(busdev, 0, pic[59 - GIC_INTERNAL]);
dev = qdev_new(TYPE_CADENCE_UART);
busdev = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", serial_hd(1));
@@ -303,15 +301,15 @@ static void zynq_init(MachineState *machine)
qdev_get_clock_out(slcr, "uart1_ref_clk"));
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xE0001000);
- sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
+ sysbus_connect_irq(busdev, 0, pic[82 - GIC_INTERNAL]);
sysbus_create_varargs("cadence_ttc", 0xF8001000,
- pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
+ pic[42-GIC_INTERNAL], pic[43-GIC_INTERNAL], pic[44-GIC_INTERNAL], NULL);
sysbus_create_varargs("cadence_ttc", 0xF8002000,
- pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
+ pic[69-GIC_INTERNAL], pic[70-GIC_INTERNAL], pic[71-GIC_INTERNAL], NULL);
- gem_init(0xE000B000, pic[54 - IRQ_OFFSET]);
- gem_init(0xE000C000, pic[77 - IRQ_OFFSET]);
+ gem_init(0xE000B000, pic[54 - GIC_INTERNAL]);
+ gem_init(0xE000C000, pic[77 - GIC_INTERNAL]);
for (n = 0; n < 2; n++) {
int hci_irq = n ? 79 : 56;
@@ -330,7 +328,7 @@ static void zynq_init(MachineState *machine)
qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - GIC_INTERNAL]);
di = drive_get(IF_SD, 0, n);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
@@ -343,7 +341,7 @@ static void zynq_init(MachineState *machine)
dev = qdev_new(TYPE_ZYNQ_XADC);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-GIC_INTERNAL]);
dev = qdev_new("pl330");
object_property_set_link(OBJECT(dev), "memory",
@@ -363,15 +361,15 @@ static void zynq_init(MachineState *machine)
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xF8003000);
- sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
+ sysbus_connect_irq(busdev, 0, pic[45-GIC_INTERNAL]); /* abort irq line */
for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
- sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
+ sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - GIC_INTERNAL]);
}
dev = qdev_new("xlnx.ps7-dev-cfg");
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
- sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
+ sysbus_connect_irq(busdev, 0, pic[40 - GIC_INTERNAL]);
sysbus_mmio_map(busdev, 0, 0xF8007000);
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 19/41] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2025-02-20 16:20 ` [PULL 18/41] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 20/41] hw/arm/vexpress: " Peter Maydell
` (22 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Looking at the Zynq 7000 SoC Technical Reference Manual (UG585 v1.14)
on Appendix A: Register Details, the mpcore Interrupt Controller Type
Register (ICDICTR) has the IT_Lines_Number field read-only with value
0x2, described as:
IT_Lines_Number
b00010 = the distributor provides 96 interrupts,
64 external interrupt lines.
Add a GIC_EXT_IRQS definition (with a comment) to make the number of
GIC external IRQs explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xilinx_zynq.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 22c0bb17262..b8916665ed6 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -57,6 +57,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
#define MPCORE_PERIPHBASE 0xF8F00000
#define ZYNQ_BOARD_MIDR 0x413FC090
+#define GIC_EXT_IRQS 64 /* Zynq 7000 SoC */
+
static const int dma_irqs[8] = {
46, 47, 48, 49, 72, 73, 74, 75
};
@@ -205,7 +207,7 @@ static void zynq_init(MachineState *machine)
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
DeviceState *dev, *slcr;
SysBusDevice *busdev;
- qemu_irq pic[64];
+ qemu_irq pic[GIC_EXT_IRQS];
int n;
unsigned int smp_cpus = machine->smp.cpus;
@@ -261,6 +263,7 @@ static void zynq_init(MachineState *machine)
dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
+ qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
@@ -275,7 +278,7 @@ static void zynq_init(MachineState *machine)
qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
}
- for (n = 0; n < 64; n++) {
+ for (n = 0; n < GIC_EXT_IRQS; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
}
@@ -458,7 +461,7 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data)
};
MachineClass *mc = MACHINE_CLASS(oc);
ObjectProperty *prop;
- mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
+ mc->desc = "Xilinx Zynq 7000 Platform Baseboard for Cortex-A9";
mc->init = zynq_init;
mc->max_cpus = ZYNQ_MAX_CPUS;
mc->ignore_memory_transaction_failures = true;
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 20/41] hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2025-02-20 16:21 ` [PULL 19/41] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 21/41] hw/arm/highbank: Specify explicitly the GIC has 128 " Peter Maydell
` (21 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Versatile Express board however expects a fixed set of 64
interrupts (see the fixed IRQ length when this board was added in
commit 2055283bcc8 ("hw/vexpress: Add model of ARM Versatile Express
board"). Add the GIC_EXT_IRQS definition (with a comment) to make
that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/vexpress.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 48e18a49d54..76c6107766c 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -51,6 +51,8 @@
#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
+#define GIC_EXT_IRQS 64 /* Versatile Express A9 development board */
+
/* Number of virtio transports to create (0..8; limited by
* number of available IRQ lines).
*/
@@ -241,6 +243,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type,
*/
dev = qdev_new(privdev);
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
+ qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, periphbase);
@@ -251,7 +254,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type,
* external interrupts starting from 32 (because there
* are internal interrupts 0..31).
*/
- for (n = 0; n < 64; n++) {
+ for (n = 0; n < GIC_EXT_IRQS; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
}
@@ -543,7 +546,7 @@ static void vexpress_common_init(MachineState *machine)
VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
VEDBoardInfo *daughterboard = vmc->daughterboard;
DeviceState *dev, *sysctl, *pl041;
- qemu_irq pic[64];
+ qemu_irq pic[GIC_EXT_IRQS];
uint32_t sys_id;
DriveInfo *dinfo;
PFlashCFI01 *pflash0;
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 21/41] hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2025-02-20 16:21 ` [PULL 20/41] hw/arm/vexpress: " Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 22/41] hw/cpu/arm_mpcore: Remove default values for GIC " Peter Maydell
` (20 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Caldexa Highbank board however expects a fixed set of 128
interrupts (see the fixed IRQ length when this board was added in
commit 2488514cef2 ("arm: SoC model for Calxeda Highbank"). Add the
GIC_EXT_IRQS definition (with a comment) to make that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/highbank.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 495704d9726..0f3c207d548 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -45,7 +45,7 @@
#define MVBAR_ADDR 0x200
#define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
-#define NIRQ_GIC 160
+#define GIC_EXT_IRQS 128 /* EnergyCore ECX-1000 & ECX-2000 */
/* Board init. */
@@ -180,7 +180,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
{
DeviceState *dev = NULL;
SysBusDevice *busdev;
- qemu_irq pic[128];
+ qemu_irq pic[GIC_EXT_IRQS];
int n;
unsigned int smp_cpus = machine->smp.cpus;
qemu_irq cpu_irq[4];
@@ -260,7 +260,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
break;
}
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
- qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
+ qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
@@ -271,7 +271,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]);
}
- for (n = 0; n < 128; n++) {
+ for (n = 0; n < GIC_EXT_IRQS; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 22/41] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2025-02-20 16:21 ` [PULL 21/41] hw/arm/highbank: Specify explicitly the GIC has 128 " Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 23/41] Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX Peter Maydell
` (19 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Implicit default values are often hard to figure out, better
be explicit. Now that all boards explicitly set the number of
GIC external IRQs, remove the default values (displaying an
error message if it is out of range).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/cpu/a15mpcore.c | 18 ++++++++++++------
hw/cpu/a9mpcore.c | 18 ++++++++++++------
2 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index d24ab0a6ab2..676f65a0af4 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -58,6 +58,11 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
bool has_el2 = false;
Object *cpuobj;
+ if (s->num_irq < 32 || s->num_irq > 256) {
+ error_setg(errp, "Property 'num-irq' must be between 32 and 256");
+ return;
+ }
+
gicdev = DEVICE(&s->gic);
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
@@ -146,13 +151,14 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
static const Property a15mp_priv_properties[] = {
DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
- /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
- * IRQ lines (with another 32 internal). We default to 128+32, which
- * is the number provided by the Cortex-A15MP test chip in the
- * Versatile Express A15 development board.
- * Other boards may differ and should set this property appropriately.
+ /*
+ * The Cortex-A15MP may have anything from 0 to 224 external interrupt
+ * lines, plus always 32 internal IRQs. This property sets the total
+ * of internal + external, so the valid range is from 32 to 256.
+ * The board model must set this to whatever the configuration
+ * used for the CPU on that board or SoC is.
*/
- DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
+ DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 0),
};
static void a15mp_priv_class_init(ObjectClass *klass, void *data)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 25416c5032b..1b9f2bef93c 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -56,6 +56,11 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
CPUState *cpu0;
Object *cpuobj;
+ if (s->num_irq < 32 || s->num_irq > 256) {
+ error_setg(errp, "Property 'num-irq' must be between 32 and 256");
+ return;
+ }
+
cpu0 = qemu_get_cpu(0);
cpuobj = OBJECT(cpu0);
if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) {
@@ -160,13 +165,14 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
static const Property a9mp_priv_properties[] = {
DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
- /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
- * IRQ lines (with another 32 internal). We default to 64+32, which
- * is the number provided by the Cortex-A9MP test chip in the
- * Realview PBX-A9 and Versatile Express A9 development boards.
- * Other boards may differ and should set this property appropriately.
+ /*
+ * The Cortex-A9MP may have anything from 0 to 224 external interrupt
+ * lines, plus always 32 internal IRQs. This property sets the total
+ * of internal + external, so the valid range is from 32 to 256.
+ * The board model must set this to whatever the configuration
+ * used for the CPU on that board or SoC is.
*/
- DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
+ DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 0),
};
static void a9mp_priv_class_init(ObjectClass *klass, void *data)
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 23/41] Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2025-02-20 16:21 ` [PULL 22/41] hw/cpu/arm_mpcore: Remove default values for GIC " Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 24/41] target/arm: Use uint32_t in t32_expandimm_imm() Peter Maydell
` (18 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Bernhard Beschow <shentey@gmail.com>
TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_SYSBUS while
TYPE_CHIPIDEA is a separate compilation unit, so only works by accident if
CONFIG_IMX is given. Fix that by extracting CONFIG_USB_CHIPIDEA from CONFIG_IMX.
cc: qemu-stable@nongnu.org
Fixes: 616ec12d0fcc "hw/arm/xilinx_zynq: Fix USB port instantiation"
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20250209103604.29545-1-shentey@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/Kconfig | 6 +++++-
hw/usb/Kconfig | 4 ++++
hw/usb/meson.build | 2 +-
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 256013ca808..7eab3914d4b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -303,7 +303,7 @@ config ZYNQ
select PL330
select SDHCI
select SSI_M25P80
- select USB_EHCI_SYSBUS
+ select USB_CHIPIDEA
select XILINX # UART
select XILINX_AXI
select XILINX_SPI
@@ -489,6 +489,7 @@ config FSL_IMX25
select IMX
select IMX_FEC
select IMX_I2C
+ select USB_CHIPIDEA
select WDT_IMX2
select SDHCI
@@ -516,6 +517,7 @@ config FSL_IMX6
select PL310 # cache controller
select PCI_EXPRESS_DESIGNWARE
select SDHCI
+ select USB_CHIPIDEA
select OR_IRQ
config ASPEED_SOC
@@ -576,6 +578,7 @@ config FSL_IMX7
select SDHCI
select OR_IRQ
select UNIMP
+ select USB_CHIPIDEA
config ARM_SMMUV3
bool
@@ -591,6 +594,7 @@ config FSL_IMX6UL
select IMX_I2C
select WDT_IMX2
select SDHCI
+ select USB_CHIPIDEA
select UNIMP
config MICROBIT
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index 5fbecd2f43b..69c663be52f 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -143,3 +143,7 @@ config USB_DWC3
config XLNX_USB_SUBSYS
bool
select USB_DWC3
+
+config USB_CHIPIDEA
+ bool
+ select USB_EHCI_SYSBUS
diff --git a/hw/usb/meson.build b/hw/usb/meson.build
index 1b4d1507e41..17360a5b5a4 100644
--- a/hw/usb/meson.build
+++ b/hw/usb/meson.build
@@ -25,8 +25,8 @@ system_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: files('hcd-xhci-sysbus.c'
system_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c'))
system_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c'))
system_ss.add(when: 'CONFIG_USB_DWC3', if_true: files('hcd-dwc3.c'))
+system_ss.add(when: 'CONFIG_USB_CHIPIDEA', if_true: files('chipidea.c'))
-system_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c'))
system_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c'))
system_ss.add(when: 'CONFIG_VT82C686', if_true: files('vt82c686-uhci-pci.c'))
system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-usb2-ctrl-regs.c'))
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 24/41] target/arm: Use uint32_t in t32_expandimm_imm()
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2025-02-20 16:21 ` [PULL 23/41] Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 25/41] roms: Update vbootrom to 1287b6e Peter Maydell
` (17 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Stephen Longfield <slongfield@google.com>
In t32_expandimm_imm(), we take an 8 bit value XY and construct a
32-bit value which might be of the form XY, 00XY00XY, XY00XY00, or
XYXYXYXY. We do this with multiplications, and we use an 'int' type.
For the cases where we're setting the high byte of the 32-bit value
to XY, this means that we do an integer multiplication that might
overflow, and rely on the -fwrapv semantics to keep this from being
undefined behaviour.
It's clearer to use an unsigned type here, because we're really
doing operations on the value considered as a set of bits. The
result is the same.
The return value from the function remains 'int', because this
is a decodetree !function function, and follows the API for those
functions.
Signed-off-by: Stephen Longfield <slongfield@google.com>
Signed-off-by: Roque Arcudia Hernandez <roqueh@google.com>
Message-id: 20250219165534.3387376-1-slongfield@google.com
[PMM: Rewrote the commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index 68ac3934153..d8225b77c8c 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -3510,7 +3510,7 @@ static int t32_expandimm_rot(DisasContext *s, int x)
/* Return the unrotated immediate from T32ExpandImm. */
static int t32_expandimm_imm(DisasContext *s, int x)
{
- int imm = extract32(x, 0, 8);
+ uint32_t imm = extract32(x, 0, 8);
switch (extract32(x, 8, 4)) {
case 0: /* XY */
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 25/41] roms: Update vbootrom to 1287b6e
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2025-02-20 16:21 ` [PULL 24/41] target/arm: Use uint32_t in t32_expandimm_imm() Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 26/41] pc-bios: Add NPCM8XX vBootrom Peter Maydell
` (16 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-2-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
pc-bios/npcm7xx_bootrom.bin | Bin 768 -> 768 bytes
roms/vbootrom | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/pc-bios/npcm7xx_bootrom.bin b/pc-bios/npcm7xx_bootrom.bin
index 38f89d1b97b0c2e133af2a9fbed0521be132065b..903f126636f9ef5d1100c056656ccfb2b32e5e10 100644
GIT binary patch
delta 90
zcmZo*Yhc^(l+nU*!D9x6DNkDr=09a-2ztoGz`#|*F#jn7L;r()|Np;c0m>C1$z?$0
Ywog`Ma%Vh0Ig_b-VgU<}A_D>d06Rh+WdHyG
delta 69
zcmZo*Yhc^(lu^NO!D9x2$xoRb7CdZGnE#ZCA@Cs+0|QqL!~CZV4E+!GPG)41X52Pe
SmdTy*+~icIZXQJj1ONb5*AzJb
diff --git a/roms/vbootrom b/roms/vbootrom
index 0c37a43527f..1287b6e42e8 160000
--- a/roms/vbootrom
+++ b/roms/vbootrom
@@ -1 +1 @@
-Subproject commit 0c37a43527f0ee2b9584e7fb2fdc805e902635ac
+Subproject commit 1287b6e42e839ba2ab0f06268c5b53ae60df3537
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 26/41] pc-bios: Add NPCM8XX vBootrom
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2025-02-20 16:21 ` [PULL 25/41] roms: Update vbootrom to 1287b6e Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 27/41] hw/ssi: Make flash size a property in NPCM7XX FIU Peter Maydell
` (15 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
The bootrom is a minimal bootrom used to load an NPCM8XX image.
The source code is located in the same repo as the NPCM7XX one:
github.com/google/vbootrom/tree/master/npcm8xx.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-3-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
MAINTAINERS | 1 +
pc-bios/README | 8 ++++----
pc-bios/meson.build | 1 +
pc-bios/npcm8xx_bootrom.bin | Bin 0 -> 608 bytes
roms/Makefile | 6 ++++++
5 files changed, 12 insertions(+), 4 deletions(-)
create mode 100644 pc-bios/npcm8xx_bootrom.bin
diff --git a/MAINTAINERS b/MAINTAINERS
index 3848d37a38d..e145017d533 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -878,6 +878,7 @@ F: include/hw/*/npcm*
F: tests/qtest/npcm*
F: tests/qtest/adm1266-test.c
F: pc-bios/npcm7xx_bootrom.bin
+F: pc-bios/npcm8xx_bootrom.bin
F: roms/vbootrom
F: docs/system/arm/nuvoton.rst
F: tests/functional/test_arm_quanta_gsj.py
diff --git a/pc-bios/README b/pc-bios/README
index 7ffb2f43a46..700dcaab523 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -70,10 +70,10 @@
source code also contains code reused from other projects described here:
https://github.com/riscv/opensbi/blob/master/ThirdPartyNotices.md.
-- npcm7xx_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for Nuvoton
- NPCM7xx BMC devices. It currently implements the bare minimum to load, parse,
- initialize and run boot images stored in SPI flash, but may grow more
- features over time as needed. The source code is available at:
+- npcm{7xx,8xx}_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for
+ Nuvoton NPCM7xx/8xx BMC devices. It currently implements the bare minimum to
+ load, parse, initialize and run boot images stored in SPI flash, but may grow
+ more features over time as needed. The source code is available at:
https://github.com/google/vbootrom
- hppa-firmware.img (32-bit) and hppa-firmware64.img (64-bit) are firmware
diff --git a/pc-bios/meson.build b/pc-bios/meson.build
index b68b29cc7d1..51e95cc9031 100644
--- a/pc-bios/meson.build
+++ b/pc-bios/meson.build
@@ -80,6 +80,7 @@ blobs = [
'opensbi-riscv32-generic-fw_dynamic.bin',
'opensbi-riscv64-generic-fw_dynamic.bin',
'npcm7xx_bootrom.bin',
+ 'npcm8xx_bootrom.bin',
'vof.bin',
'vof-nvram.bin',
]
diff --git a/pc-bios/npcm8xx_bootrom.bin b/pc-bios/npcm8xx_bootrom.bin
new file mode 100644
index 0000000000000000000000000000000000000000..6370d6475635c4d445d2b927311edcd591949c82
GIT binary patch
literal 608
zcmdUrKTE?<6vfX=0{*3B5ET?nwWA^;qEk()n=Xb9-4dxoSBrz#p|QJQL~zokn{Eyc
z?PBXUkU+aB?k?IbNQftG5ej|*FC2c{bKkr7zLy3jhNxj`gc_y5h&V=Ru)PgZC)Y`f
zTqA9Am28qL<U6@cMtA>Hlr*^&hT#;re-)dpxT0U42|O+cWOcx=B;{6xXH04vx?cjm
z+%U{oFx!aPpV3>ZKz0i$XA-yq{f}<H?{MHBq+VwIvR9WmcL(xr1vuIRGELcRC-S+P
zl3%RlR5(6+1;xg_<~xR#bPItDN1*Hp^{JyNs7o*BMq0Q9q1#>x4;|pb<NWIbQ8wb1
zTac^<ebj^E^Ig<?U?(PO-w>w;l#@9zGd|z-rs*H@V-o%PEV)D-)8n2%DyH5@w_^Y8
LH5R3RMV#gjxYTW}
literal 0
HcmV?d00001
diff --git a/roms/Makefile b/roms/Makefile
index 31e4b97c983..beff58d9d50 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -34,6 +34,7 @@ find-cross-gcc = $(firstword $(wildcard $(patsubst %ld,%gcc,$(call find-cross-ld
# finally strip off path + toolname so we get the prefix
find-cross-prefix = $(subst gcc,,$(notdir $(call find-cross-gcc,$(1))))
+aarch64_cross_prefix := $(call find-cross-prefix,aarch64)
arm_cross_prefix := $(call find-cross-prefix,arm)
powerpc64_cross_prefix := $(call find-cross-prefix,powerpc64)
powerpc_cross_prefix := $(call find-cross-prefix,powerpc)
@@ -66,6 +67,7 @@ default help:
@echo " u-boot.e500 -- update u-boot.e500"
@echo " u-boot.sam460 -- update u-boot.sam460"
@echo " npcm7xx_bootrom -- update vbootrom for npcm7xx"
+ @echo " npcm8xx_bootrom -- update vbootrom for npcm8xx"
@echo " efi -- update UEFI (edk2) platform firmware"
@echo " opensbi32-generic -- update OpenSBI for 32-bit generic machine"
@echo " opensbi64-generic -- update OpenSBI for 64-bit generic machine"
@@ -194,6 +196,10 @@ npcm7xx_bootrom:
$(MAKE) -C vbootrom CROSS_COMPILE=$(arm_cross_prefix)
cp vbootrom/npcm7xx_bootrom.bin ../pc-bios/npcm7xx_bootrom.bin
+npcm8xx_bootrom:
+ $(MAKE) -C vbootrom CROSS_COMPILE=$(aarch64_cross_prefix)
+ cp vbootrom/npcm8xx_bootrom.bin ../pc-bios/npcm8xx_bootrom.bin
+
hppa-firmware:
$(MAKE) -C seabios-hppa parisc
cp seabios-hppa/out/hppa-firmware.img ../pc-bios/
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 27/41] hw/ssi: Make flash size a property in NPCM7XX FIU
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2025-02-20 16:21 ` [PULL 26/41] pc-bios: Add NPCM8XX vBootrom Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 28/41] hw/misc: Rename npcm7xx_gcr to npcm_gcr Peter Maydell
` (14 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
Message-id: 20250219184609.1839281-4-wuhaotsh@google.com
[PMM: flash_size must be a uint64_t to build on 32-bit hosts]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/ssi/npcm7xx_fiu.h | 1 +
hw/arm/npcm7xx.c | 6 ++++++
hw/ssi/npcm7xx_fiu.c | 16 ++++++++++++++--
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/include/hw/ssi/npcm7xx_fiu.h b/include/hw/ssi/npcm7xx_fiu.h
index a3a17042896..7ebd422ca6c 100644
--- a/include/hw/ssi/npcm7xx_fiu.h
+++ b/include/hw/ssi/npcm7xx_fiu.h
@@ -60,6 +60,7 @@ struct NPCM7xxFIUState {
int32_t cs_count;
int32_t active_cs;
qemu_irq *cs_lines;
+ uint64_t flash_size;
NPCM7xxFIUFlash *flash;
SSIBus *spi;
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 386b2c35e9b..2d6e08b72ba 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -292,17 +292,21 @@ static const struct {
hwaddr regs_addr;
int cs_count;
const hwaddr *flash_addr;
+ size_t flash_size;
} npcm7xx_fiu[] = {
{
.name = "fiu0",
.regs_addr = 0xfb000000,
.cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
.flash_addr = npcm7xx_fiu0_flash_addr,
+ .flash_size = 128 * MiB,
+
}, {
.name = "fiu3",
.regs_addr = 0xc0000000,
.cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
.flash_addr = npcm7xx_fiu3_flash_addr,
+ .flash_size = 128 * MiB,
},
};
@@ -735,6 +739,8 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(sbd), "cs-count",
npcm7xx_fiu[i].cs_count, &error_abort);
+ object_property_set_int(OBJECT(sbd), "flash-size",
+ npcm7xx_fiu[i].flash_size, &error_abort);
sysbus_realize(sbd, &error_abort);
sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
index 21fc4890383..8df4bec3f17 100644
--- a/hw/ssi/npcm7xx_fiu.c
+++ b/hw/ssi/npcm7xx_fiu.c
@@ -29,7 +29,7 @@
#include "trace.h"
/* Up to 128 MiB of flash may be accessed directly as memory. */
-#define NPCM7XX_FIU_FLASH_WINDOW_SIZE (128 * MiB)
+#define NPCM7XX_FIU_MAX_FLASH_WINDOW_SIZE (128 * MiB)
/* Each module has 4 KiB of register space. Only a fraction of it is used. */
#define NPCM7XX_FIU_CTRL_REGS_SIZE (4 * KiB)
@@ -507,6 +507,17 @@ static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
return;
}
+ if (s->flash_size == 0) {
+ error_setg(errp, "%s: flash size must be set", dev->canonical_path);
+ return;
+ }
+
+ if (s->flash_size > NPCM7XX_FIU_MAX_FLASH_WINDOW_SIZE) {
+ error_setg(errp, "%s: flash size should not exceed 128 MiB",
+ dev->canonical_path);
+ return;
+ }
+
s->spi = ssi_create_bus(dev, "spi");
s->cs_lines = g_new0(qemu_irq, s->cs_count);
qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", s->cs_count);
@@ -525,7 +536,7 @@ static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
flash->fiu = s;
memory_region_init_io(&flash->direct_access, OBJECT(s),
&npcm7xx_fiu_flash_ops, &s->flash[i], "flash",
- NPCM7XX_FIU_FLASH_WINDOW_SIZE);
+ s->flash_size);
sysbus_init_mmio(sbd, &flash->direct_access);
}
}
@@ -543,6 +554,7 @@ static const VMStateDescription vmstate_npcm7xx_fiu = {
static const Property npcm7xx_fiu_properties[] = {
DEFINE_PROP_INT32("cs-count", NPCM7xxFIUState, cs_count, 0),
+ DEFINE_PROP_SIZE("flash-size", NPCM7xxFIUState, flash_size, 0),
};
static void npcm7xx_fiu_class_init(ObjectClass *klass, void *data)
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 28/41] hw/misc: Rename npcm7xx_gcr to npcm_gcr
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (26 preceding siblings ...)
2025-02-20 16:21 ` [PULL 27/41] hw/ssi: Make flash size a property in NPCM7XX FIU Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 29/41] hw/misc: Move NPCM7XX GCR to NPCM GCR Peter Maydell
` (13 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-5-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/npcm7xx.h | 2 +-
include/hw/misc/{npcm7xx_gcr.h => npcm_gcr.h} | 6 +++---
hw/misc/{npcm7xx_gcr.c => npcm_gcr.c} | 2 +-
hw/misc/meson.build | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
rename include/hw/misc/{npcm7xx_gcr.h => npcm_gcr.h} (96%)
rename hw/misc/{npcm7xx_gcr.c => npcm_gcr.c} (99%)
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index 4e0d2101885..510170471e0 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -24,7 +24,7 @@
#include "hw/i2c/npcm7xx_smbus.h"
#include "hw/mem/npcm7xx_mc.h"
#include "hw/misc/npcm7xx_clk.h"
-#include "hw/misc/npcm7xx_gcr.h"
+#include "hw/misc/npcm_gcr.h"
#include "hw/misc/npcm7xx_mft.h"
#include "hw/misc/npcm7xx_pwm.h"
#include "hw/misc/npcm7xx_rng.h"
diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm_gcr.h
similarity index 96%
rename from include/hw/misc/npcm7xx_gcr.h
rename to include/hw/misc/npcm_gcr.h
index c0bbdda77e5..9b4998950cc 100644
--- a/include/hw/misc/npcm7xx_gcr.h
+++ b/include/hw/misc/npcm_gcr.h
@@ -13,8 +13,8 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
-#ifndef NPCM7XX_GCR_H
-#define NPCM7XX_GCR_H
+#ifndef NPCM_GCR_H
+#define NPCM_GCR_H
#include "exec/memory.h"
#include "hw/sysbus.h"
@@ -70,4 +70,4 @@ struct NPCM7xxGCRState {
#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR)
-#endif /* NPCM7XX_GCR_H */
+#endif /* NPCM_GCR_H */
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm_gcr.c
similarity index 99%
rename from hw/misc/npcm7xx_gcr.c
rename to hw/misc/npcm_gcr.c
index 07464a4dc93..826fd41123b 100644
--- a/hw/misc/npcm7xx_gcr.c
+++ b/hw/misc/npcm_gcr.c
@@ -16,7 +16,7 @@
#include "qemu/osdep.h"
-#include "hw/misc/npcm7xx_gcr.h"
+#include "hw/misc/npcm_gcr.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 55f493521be..554eb8df5bc 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -70,7 +70,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files(
))
system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
'npcm7xx_clk.c',
- 'npcm7xx_gcr.c',
+ 'npcm_gcr.c',
'npcm7xx_mft.c',
'npcm7xx_pwm.c',
'npcm7xx_rng.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 29/41] hw/misc: Move NPCM7XX GCR to NPCM GCR
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (27 preceding siblings ...)
2025-02-20 16:21 ` [PULL 28/41] hw/misc: Rename npcm7xx_gcr to npcm_gcr Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 30/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
` (12 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-6-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/npcm7xx.h | 2 +-
include/hw/misc/npcm_gcr.h | 7 +--
hw/misc/npcm_gcr.c | 92 +++++++++++++++++++++-----------------
hw/misc/trace-events | 6 +--
4 files changed, 59 insertions(+), 48 deletions(-)
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index 510170471e0..2e708471ece 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -89,7 +89,7 @@ struct NPCM7xxState {
MemoryRegion ram3;
MemoryRegion *dram;
- NPCM7xxGCRState gcr;
+ NPCMGCRState gcr;
NPCM7xxCLKState clk;
NPCM7xxTimerCtrlState tim[3];
NPCM7xxADCState adc;
diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h
index 9b4998950cc..6d3d00d2602 100644
--- a/include/hw/misc/npcm_gcr.h
+++ b/include/hw/misc/npcm_gcr.h
@@ -55,7 +55,7 @@
*/
#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
-struct NPCM7xxGCRState {
+typedef struct NPCMGCRState {
SysBusDevice parent;
MemoryRegion iomem;
@@ -65,9 +65,10 @@ struct NPCM7xxGCRState {
uint32_t reset_pwron;
uint32_t reset_mdlr;
uint32_t reset_intcr3;
-};
+} NPCMGCRState;
+#define TYPE_NPCM_GCR "npcm-gcr"
#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
-OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR)
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMGCRState, NPCM_GCR)
#endif /* NPCM_GCR_H */
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index 826fd41123b..0959f2e5c4b 100644
--- a/hw/misc/npcm_gcr.c
+++ b/hw/misc/npcm_gcr.c
@@ -84,10 +84,10 @@ static const uint32_t cold_reset_values[NPCM7XX_GCR_NR_REGS] = {
[NPCM7XX_GCR_USB2PHYCTL] = 0x034730e4,
};
-static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr offset, unsigned size)
+static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
- NPCM7xxGCRState *s = opaque;
+ NPCMGCRState *s = opaque;
if (reg >= NPCM7XX_GCR_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -96,19 +96,19 @@ static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr offset, unsigned size)
return 0;
}
- trace_npcm7xx_gcr_read(offset, s->regs[reg]);
+ trace_npcm_gcr_read(offset, s->regs[reg]);
return s->regs[reg];
}
-static void npcm7xx_gcr_write(void *opaque, hwaddr offset,
+static void npcm_gcr_write(void *opaque, hwaddr offset,
uint64_t v, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
- NPCM7xxGCRState *s = opaque;
+ NPCMGCRState *s = opaque;
uint32_t value = v;
- trace_npcm7xx_gcr_write(offset, value);
+ trace_npcm_gcr_write(offset, value);
if (reg >= NPCM7XX_GCR_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -142,9 +142,9 @@ static void npcm7xx_gcr_write(void *opaque, hwaddr offset,
s->regs[reg] = value;
}
-static const struct MemoryRegionOps npcm7xx_gcr_ops = {
- .read = npcm7xx_gcr_read,
- .write = npcm7xx_gcr_write,
+static const struct MemoryRegionOps npcm_gcr_ops = {
+ .read = npcm_gcr_read,
+ .write = npcm_gcr_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
@@ -155,7 +155,7 @@ static const struct MemoryRegionOps npcm7xx_gcr_ops = {
static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
{
- NPCM7xxGCRState *s = NPCM7XX_GCR(obj);
+ NPCMGCRState *s = NPCM_GCR(obj);
QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
@@ -165,10 +165,10 @@ static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
}
-static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp)
+static void npcm_gcr_realize(DeviceState *dev, Error **errp)
{
ERRP_GUARD();
- NPCM7xxGCRState *s = NPCM7XX_GCR(dev);
+ NPCMGCRState *s = NPCM_GCR(dev);
uint64_t dram_size;
Object *obj;
@@ -210,55 +210,65 @@ static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp)
s->reset_intcr3 |= ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8;
}
-static void npcm7xx_gcr_init(Object *obj)
+static void npcm_gcr_init(Object *obj)
{
- NPCM7xxGCRState *s = NPCM7XX_GCR(obj);
+ NPCMGCRState *s = NPCM_GCR(obj);
- memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
- TYPE_NPCM7XX_GCR, 4 * KiB);
+ memory_region_init_io(&s->iomem, obj, &npcm_gcr_ops, s,
+ TYPE_NPCM_GCR, 4 * KiB);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
}
-static const VMStateDescription vmstate_npcm7xx_gcr = {
- .name = "npcm7xx-gcr",
- .version_id = 0,
- .minimum_version_id = 0,
+static const VMStateDescription vmstate_npcm_gcr = {
+ .name = "npcm-gcr",
+ .version_id = 1,
+ .minimum_version_id = 1,
.fields = (const VMStateField[]) {
- VMSTATE_UINT32_ARRAY(regs, NPCM7xxGCRState, NPCM7XX_GCR_NR_REGS),
+ VMSTATE_UINT32_ARRAY(regs, NPCMGCRState, NPCM7XX_GCR_NR_REGS),
VMSTATE_END_OF_LIST(),
},
};
-static const Property npcm7xx_gcr_properties[] = {
- DEFINE_PROP_UINT32("disabled-modules", NPCM7xxGCRState, reset_mdlr, 0),
- DEFINE_PROP_UINT32("power-on-straps", NPCM7xxGCRState, reset_pwron, 0),
+static const Property npcm_gcr_properties[] = {
+ DEFINE_PROP_UINT32("disabled-modules", NPCMGCRState, reset_mdlr, 0),
+ DEFINE_PROP_UINT32("power-on-straps", NPCMGCRState, reset_pwron, 0),
};
-static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
+static void npcm_gcr_class_init(ObjectClass *klass, void *data)
{
- ResettableClass *rc = RESETTABLE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM7XX_GCR_NR_REGS);
+ dc->realize = npcm_gcr_realize;
+ dc->vmsd = &vmstate_npcm_gcr;
+ device_class_set_props(dc, npcm_gcr_properties);
+}
+
+static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+ QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END != NPCM7XX_GCR_NR_REGS);
dc->desc = "NPCM7xx System Global Control Registers";
- dc->realize = npcm7xx_gcr_realize;
- dc->vmsd = &vmstate_npcm7xx_gcr;
rc->phases.enter = npcm7xx_gcr_enter_reset;
- device_class_set_props(dc, npcm7xx_gcr_properties);
}
-static const TypeInfo npcm7xx_gcr_info = {
- .name = TYPE_NPCM7XX_GCR,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(NPCM7xxGCRState),
- .instance_init = npcm7xx_gcr_init,
- .class_init = npcm7xx_gcr_class_init,
+static const TypeInfo npcm_gcr_info[] = {
+ {
+ .name = TYPE_NPCM_GCR,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCMGCRState),
+ .instance_init = npcm_gcr_init,
+ .class_init = npcm_gcr_class_init,
+ .abstract = true,
+ },
+ {
+ .name = TYPE_NPCM7XX_GCR,
+ .parent = TYPE_NPCM_GCR,
+ .class_init = npcm7xx_gcr_class_init,
+ },
};
-
-static void npcm7xx_gcr_register_type(void)
-{
- type_register_static(&npcm7xx_gcr_info);
-}
-type_init(npcm7xx_gcr_register_type);
+DEFINE_TYPES(npcm_gcr_info)
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index b35b0e77f7d..0f7204a237e 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -134,9 +134,9 @@ mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%
npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
-# npcm7xx_gcr.c
-npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
-npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+# npcm_gcr.c
+npcm_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
# npcm7xx_mft.c
npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 30/41] hw/misc: Add nr_regs and cold_reset_values to NPCM GCR
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (28 preceding siblings ...)
2025-02-20 16:21 ` [PULL 29/41] hw/misc: Move NPCM7XX GCR to NPCM GCR Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 31/41] hw/misc: Add support for NPCM8XX GCR Peter Maydell
` (11 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
These 2 values are different between NPCM7XX and NPCM8XX
GCRs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-7-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/misc/npcm_gcr.h | 13 +++++++++++--
hw/misc/npcm_gcr.c | 27 ++++++++++++++++-----------
2 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h
index 6d3d00d2602..9af24e5cdc8 100644
--- a/include/hw/misc/npcm_gcr.h
+++ b/include/hw/misc/npcm_gcr.h
@@ -18,6 +18,7 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
+#include "qom/object.h"
/*
* NPCM7XX PWRON STRAP bit fields
@@ -53,6 +54,7 @@
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.
*/
+#define NPCM_GCR_MAX_NR_REGS NPCM7XX_GCR_NR_REGS
#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
typedef struct NPCMGCRState {
@@ -60,15 +62,22 @@ typedef struct NPCMGCRState {
MemoryRegion iomem;
- uint32_t regs[NPCM7XX_GCR_NR_REGS];
+ uint32_t regs[NPCM_GCR_MAX_NR_REGS];
uint32_t reset_pwron;
uint32_t reset_mdlr;
uint32_t reset_intcr3;
} NPCMGCRState;
+typedef struct NPCMGCRClass {
+ SysBusDeviceClass parent;
+
+ size_t nr_regs;
+ const uint32_t *cold_reset_values;
+} NPCMGCRClass;
+
#define TYPE_NPCM_GCR "npcm-gcr"
#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
-OBJECT_DECLARE_SIMPLE_TYPE(NPCMGCRState, NPCM_GCR)
+OBJECT_DECLARE_TYPE(NPCMGCRState, NPCMGCRClass, NPCM_GCR)
#endif /* NPCM_GCR_H */
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index 0959f2e5c4b..d89e8c2c3bf 100644
--- a/hw/misc/npcm_gcr.c
+++ b/hw/misc/npcm_gcr.c
@@ -66,10 +66,9 @@ enum NPCM7xxGCRRegisters {
NPCM7XX_GCR_SCRPAD = 0x013c / sizeof(uint32_t),
NPCM7XX_GCR_USB1PHYCTL,
NPCM7XX_GCR_USB2PHYCTL,
- NPCM7XX_GCR_REGS_END,
};
-static const uint32_t cold_reset_values[NPCM7XX_GCR_NR_REGS] = {
+static const uint32_t npcm7xx_cold_reset_values[NPCM7XX_GCR_NR_REGS] = {
[NPCM7XX_GCR_PDID] = 0x04a92750, /* Poleg A1 */
[NPCM7XX_GCR_MISCPE] = 0x0000ffff,
[NPCM7XX_GCR_SPSWC] = 0x00000003,
@@ -88,8 +87,9 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
NPCMGCRState *s = opaque;
+ NPCMGCRClass *c = NPCM_GCR_GET_CLASS(s);
- if (reg >= NPCM7XX_GCR_NR_REGS) {
+ if (reg >= c->nr_regs) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: offset 0x%04" HWADDR_PRIx " out of range\n",
__func__, offset);
@@ -106,11 +106,12 @@ static void npcm_gcr_write(void *opaque, hwaddr offset,
{
uint32_t reg = offset / sizeof(uint32_t);
NPCMGCRState *s = opaque;
+ NPCMGCRClass *c = NPCM_GCR_GET_CLASS(s);
uint32_t value = v;
- trace_npcm_gcr_write(offset, value);
+ trace_npcm_gcr_write(offset, v);
- if (reg >= NPCM7XX_GCR_NR_REGS) {
+ if (reg >= c->nr_regs) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: offset 0x%04" HWADDR_PRIx " out of range\n",
__func__, offset);
@@ -156,10 +157,12 @@ static const struct MemoryRegionOps npcm_gcr_ops = {
static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
{
NPCMGCRState *s = NPCM_GCR(obj);
+ NPCMGCRClass *c = NPCM_GCR_GET_CLASS(obj);
- QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
-
- memcpy(s->regs, cold_reset_values, sizeof(s->regs));
+ g_assert(sizeof(s->regs) >= sizeof(c->cold_reset_values));
+ g_assert(sizeof(s->regs) >= c->nr_regs * sizeof(uint32_t));
+ memcpy(s->regs, c->cold_reset_values, c->nr_regs * sizeof(uint32_t));
+ /* These 3 registers are at the same location in both 7xx and 8xx. */
s->regs[NPCM7XX_GCR_PWRON] = s->reset_pwron;
s->regs[NPCM7XX_GCR_MDLR] = s->reset_mdlr;
s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
@@ -224,7 +227,7 @@ static const VMStateDescription vmstate_npcm_gcr = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (const VMStateField[]) {
- VMSTATE_UINT32_ARRAY(regs, NPCMGCRState, NPCM7XX_GCR_NR_REGS),
+ VMSTATE_UINT32_ARRAY(regs, NPCMGCRState, NPCM_GCR_MAX_NR_REGS),
VMSTATE_END_OF_LIST(),
},
};
@@ -238,7 +241,6 @@ static void npcm_gcr_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM7XX_GCR_NR_REGS);
dc->realize = npcm_gcr_realize;
dc->vmsd = &vmstate_npcm_gcr;
@@ -247,13 +249,15 @@ static void npcm_gcr_class_init(ObjectClass *klass, void *data)
static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
{
+ NPCMGCRClass *c = NPCM_GCR_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
- QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END != NPCM7XX_GCR_NR_REGS);
dc->desc = "NPCM7xx System Global Control Registers";
rc->phases.enter = npcm7xx_gcr_enter_reset;
+ c->nr_regs = NPCM7XX_GCR_NR_REGS;
+ c->cold_reset_values = npcm7xx_cold_reset_values;
}
static const TypeInfo npcm_gcr_info[] = {
@@ -262,6 +266,7 @@ static const TypeInfo npcm_gcr_info[] = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCMGCRState),
.instance_init = npcm_gcr_init,
+ .class_size = sizeof(NPCMGCRClass),
.class_init = npcm_gcr_class_init,
.abstract = true,
},
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 31/41] hw/misc: Add support for NPCM8XX GCR
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (29 preceding siblings ...)
2025-02-20 16:21 ` [PULL 30/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 32/41] hw/misc: Store DRAM size in NPCM8XX GCR Module Peter Maydell
` (10 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-8-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/misc/npcm_gcr.h | 6 +-
hw/misc/npcm_gcr.c | 133 ++++++++++++++++++++++++++++++++++++-
2 files changed, 134 insertions(+), 5 deletions(-)
diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h
index 9af24e5cdc8..9ac76ca9abb 100644
--- a/include/hw/misc/npcm_gcr.h
+++ b/include/hw/misc/npcm_gcr.h
@@ -1,5 +1,5 @@
/*
- * Nuvoton NPCM7xx System Global Control Registers.
+ * Nuvoton NPCM7xx/8xx System Global Control Registers.
*
* Copyright 2020 Google LLC
*
@@ -54,8 +54,9 @@
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.
*/
-#define NPCM_GCR_MAX_NR_REGS NPCM7XX_GCR_NR_REGS
+#define NPCM_GCR_MAX_NR_REGS NPCM8XX_GCR_NR_REGS
#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
+#define NPCM8XX_GCR_NR_REGS (0xf80 / sizeof(uint32_t))
typedef struct NPCMGCRState {
SysBusDevice parent;
@@ -78,6 +79,7 @@ typedef struct NPCMGCRClass {
#define TYPE_NPCM_GCR "npcm-gcr"
#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
+#define TYPE_NPCM8XX_GCR "npcm8xx-gcr"
OBJECT_DECLARE_TYPE(NPCMGCRState, NPCMGCRClass, NPCM_GCR)
#endif /* NPCM_GCR_H */
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index d89e8c2c3bf..ac22fb08cb2 100644
--- a/hw/misc/npcm_gcr.c
+++ b/hw/misc/npcm_gcr.c
@@ -1,5 +1,5 @@
/*
- * Nuvoton NPCM7xx System Global Control Registers.
+ * Nuvoton NPCM7xx/8xx System Global Control Registers.
*
* Copyright 2020 Google LLC
*
@@ -83,6 +83,118 @@ static const uint32_t npcm7xx_cold_reset_values[NPCM7XX_GCR_NR_REGS] = {
[NPCM7XX_GCR_USB2PHYCTL] = 0x034730e4,
};
+enum NPCM8xxGCRRegisters {
+ NPCM8XX_GCR_PDID,
+ NPCM8XX_GCR_PWRON,
+ NPCM8XX_GCR_MISCPE = 0x014 / sizeof(uint32_t),
+ NPCM8XX_GCR_FLOCKR2 = 0x020 / sizeof(uint32_t),
+ NPCM8XX_GCR_FLOCKR3,
+ NPCM8XX_GCR_A35_MODE = 0x034 / sizeof(uint32_t),
+ NPCM8XX_GCR_SPSWC,
+ NPCM8XX_GCR_INTCR,
+ NPCM8XX_GCR_INTSR,
+ NPCM8XX_GCR_HIFCR = 0x050 / sizeof(uint32_t),
+ NPCM8XX_GCR_INTCR2 = 0x060 / sizeof(uint32_t),
+ NPCM8XX_GCR_SRCNT = 0x068 / sizeof(uint32_t),
+ NPCM8XX_GCR_RESSR,
+ NPCM8XX_GCR_RLOCKR1,
+ NPCM8XX_GCR_FLOCKR1,
+ NPCM8XX_GCR_DSCNT,
+ NPCM8XX_GCR_MDLR,
+ NPCM8XX_GCR_SCRPAD_C = 0x080 / sizeof(uint32_t),
+ NPCM8XX_GCR_SCRPAD_B,
+ NPCM8XX_GCR_DAVCLVLR = 0x098 / sizeof(uint32_t),
+ NPCM8XX_GCR_INTCR3,
+ NPCM8XX_GCR_PCIRCTL = 0x0a0 / sizeof(uint32_t),
+ NPCM8XX_GCR_VSINTR,
+ NPCM8XX_GCR_SD2SUR1 = 0x0b4 / sizeof(uint32_t),
+ NPCM8XX_GCR_SD2SUR2,
+ NPCM8XX_GCR_INTCR4 = 0x0c0 / sizeof(uint32_t),
+ NPCM8XX_GCR_CPCTL = 0x0d0 / sizeof(uint32_t),
+ NPCM8XX_GCR_CP2BST,
+ NPCM8XX_GCR_B2CPNT,
+ NPCM8XX_GCR_CPPCTL,
+ NPCM8XX_GCR_I2CSEGSEL = 0x0e0 / sizeof(uint32_t),
+ NPCM8XX_GCR_I2CSEGCTL,
+ NPCM8XX_GCR_VSRCR,
+ NPCM8XX_GCR_MLOCKR,
+ NPCM8XX_GCR_SCRPAD = 0x13c / sizeof(uint32_t),
+ NPCM8XX_GCR_USB1PHYCTL,
+ NPCM8XX_GCR_USB2PHYCTL,
+ NPCM8XX_GCR_USB3PHYCTL,
+ NPCM8XX_GCR_MFSEL1 = 0x260 / sizeof(uint32_t),
+ NPCM8XX_GCR_MFSEL2,
+ NPCM8XX_GCR_MFSEL3,
+ NPCM8XX_GCR_MFSEL4,
+ NPCM8XX_GCR_MFSEL5,
+ NPCM8XX_GCR_MFSEL6,
+ NPCM8XX_GCR_MFSEL7,
+ NPCM8XX_GCR_MFSEL_LK1 = 0x280 / sizeof(uint32_t),
+ NPCM8XX_GCR_MFSEL_LK2,
+ NPCM8XX_GCR_MFSEL_LK3,
+ NPCM8XX_GCR_MFSEL_LK4,
+ NPCM8XX_GCR_MFSEL_LK5,
+ NPCM8XX_GCR_MFSEL_LK6,
+ NPCM8XX_GCR_MFSEL_LK7,
+ NPCM8XX_GCR_MFSEL_SET1 = 0x2a0 / sizeof(uint32_t),
+ NPCM8XX_GCR_MFSEL_SET2,
+ NPCM8XX_GCR_MFSEL_SET3,
+ NPCM8XX_GCR_MFSEL_SET4,
+ NPCM8XX_GCR_MFSEL_SET5,
+ NPCM8XX_GCR_MFSEL_SET6,
+ NPCM8XX_GCR_MFSEL_SET7,
+ NPCM8XX_GCR_MFSEL_CLR1 = 0x2c0 / sizeof(uint32_t),
+ NPCM8XX_GCR_MFSEL_CLR2,
+ NPCM8XX_GCR_MFSEL_CLR3,
+ NPCM8XX_GCR_MFSEL_CLR4,
+ NPCM8XX_GCR_MFSEL_CLR5,
+ NPCM8XX_GCR_MFSEL_CLR6,
+ NPCM8XX_GCR_MFSEL_CLR7,
+ NPCM8XX_GCR_WD0RCRLK = 0x400 / sizeof(uint32_t),
+ NPCM8XX_GCR_WD1RCRLK,
+ NPCM8XX_GCR_WD2RCRLK,
+ NPCM8XX_GCR_SWRSTC1LK,
+ NPCM8XX_GCR_SWRSTC2LK,
+ NPCM8XX_GCR_SWRSTC3LK,
+ NPCM8XX_GCR_TIPRSTCLK,
+ NPCM8XX_GCR_CORSTCLK,
+ NPCM8XX_GCR_WD0RCRBLK,
+ NPCM8XX_GCR_WD1RCRBLK,
+ NPCM8XX_GCR_WD2RCRBLK,
+ NPCM8XX_GCR_SWRSTC1BLK,
+ NPCM8XX_GCR_SWRSTC2BLK,
+ NPCM8XX_GCR_SWRSTC3BLK,
+ NPCM8XX_GCR_TIPRSTCBLK,
+ NPCM8XX_GCR_CORSTCBLK,
+ /* 64 scratch pad registers start here. 0xe00 ~ 0xefc */
+ NPCM8XX_GCR_SCRPAD_00 = 0xe00 / sizeof(uint32_t),
+ /* 32 semaphore registers start here. 0xf00 ~ 0xf7c */
+ NPCM8XX_GCR_GP_SEMFR_00 = 0xf00 / sizeof(uint32_t),
+ NPCM8XX_GCR_GP_SEMFR_31 = 0xf7c / sizeof(uint32_t),
+};
+
+static const uint32_t npcm8xx_cold_reset_values[NPCM8XX_GCR_NR_REGS] = {
+ [NPCM8XX_GCR_PDID] = 0x04a35850, /* Arbel A1 */
+ [NPCM8XX_GCR_MISCPE] = 0x0000ffff,
+ [NPCM8XX_GCR_A35_MODE] = 0xfff4ff30,
+ [NPCM8XX_GCR_SPSWC] = 0x00000003,
+ [NPCM8XX_GCR_INTCR] = 0x0010035e,
+ [NPCM8XX_GCR_HIFCR] = 0x0000004e,
+ [NPCM8XX_GCR_SD2SUR1] = 0xfdc80000,
+ [NPCM8XX_GCR_SD2SUR2] = 0x5200b130,
+ [NPCM8XX_GCR_INTCR2] = (1U << 19), /* DDR initialized */
+ [NPCM8XX_GCR_RESSR] = 0x80000000,
+ [NPCM8XX_GCR_DAVCLVLR] = 0x5a00f3cf,
+ [NPCM8XX_GCR_INTCR3] = 0x5e001002,
+ [NPCM8XX_GCR_VSRCR] = 0x00004800,
+ [NPCM8XX_GCR_SCRPAD] = 0x00000008,
+ [NPCM8XX_GCR_USB1PHYCTL] = 0x034730e4,
+ [NPCM8XX_GCR_USB2PHYCTL] = 0x034730e4,
+ [NPCM8XX_GCR_USB3PHYCTL] = 0x034730e4,
+ /* All 32 semaphores should be initialized to 1. */
+ [NPCM8XX_GCR_GP_SEMFR_00...NPCM8XX_GCR_GP_SEMFR_31] = 0x00000001,
+};
+
static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
@@ -224,8 +336,8 @@ static void npcm_gcr_init(Object *obj)
static const VMStateDescription vmstate_npcm_gcr = {
.name = "npcm-gcr",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, NPCMGCRState, NPCM_GCR_MAX_NR_REGS),
VMSTATE_END_OF_LIST(),
@@ -260,6 +372,16 @@ static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
c->cold_reset_values = npcm7xx_cold_reset_values;
}
+static void npcm8xx_gcr_class_init(ObjectClass *klass, void *data)
+{
+ NPCMGCRClass *c = NPCM_GCR_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "NPCM8xx System Global Control Registers";
+ c->nr_regs = NPCM8XX_GCR_NR_REGS;
+ c->cold_reset_values = npcm8xx_cold_reset_values;
+}
+
static const TypeInfo npcm_gcr_info[] = {
{
.name = TYPE_NPCM_GCR,
@@ -275,5 +397,10 @@ static const TypeInfo npcm_gcr_info[] = {
.parent = TYPE_NPCM_GCR,
.class_init = npcm7xx_gcr_class_init,
},
+ {
+ .name = TYPE_NPCM8XX_GCR,
+ .parent = TYPE_NPCM_GCR,
+ .class_init = npcm8xx_gcr_class_init,
+ },
};
DEFINE_TYPES(npcm_gcr_info)
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 32/41] hw/misc: Store DRAM size in NPCM8XX GCR Module
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (30 preceding siblings ...)
2025-02-20 16:21 ` [PULL 31/41] hw/misc: Add support for NPCM8XX GCR Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 33/41] hw/misc: Support 8-bytes memop in NPCM GCR module Peter Maydell
` (9 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-9-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/misc/npcm_gcr.h | 1 +
hw/misc/npcm_gcr.c | 24 ++++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h
index 9ac76ca9abb..d81bb9afb26 100644
--- a/include/hw/misc/npcm_gcr.h
+++ b/include/hw/misc/npcm_gcr.h
@@ -68,6 +68,7 @@ typedef struct NPCMGCRState {
uint32_t reset_pwron;
uint32_t reset_mdlr;
uint32_t reset_intcr3;
+ uint32_t reset_scrpad_b;
} NPCMGCRState;
typedef struct NPCMGCRClass {
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index ac22fb08cb2..9e4a6aee611 100644
--- a/hw/misc/npcm_gcr.c
+++ b/hw/misc/npcm_gcr.c
@@ -280,6 +280,19 @@ static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
}
+static void npcm8xx_gcr_enter_reset(Object *obj, ResetType type)
+{
+ NPCMGCRState *s = NPCM_GCR(obj);
+ NPCMGCRClass *c = NPCM_GCR_GET_CLASS(obj);
+
+ memcpy(s->regs, c->cold_reset_values, c->nr_regs * sizeof(uint32_t));
+ /* These 3 registers are at the same location in both 7xx and 8xx. */
+ s->regs[NPCM8XX_GCR_PWRON] = s->reset_pwron;
+ s->regs[NPCM8XX_GCR_MDLR] = s->reset_mdlr;
+ s->regs[NPCM8XX_GCR_INTCR3] = s->reset_intcr3;
+ s->regs[NPCM8XX_GCR_SCRPAD_B] = s->reset_scrpad_b;
+}
+
static void npcm_gcr_realize(DeviceState *dev, Error **errp)
{
ERRP_GUARD();
@@ -323,6 +336,14 @@ static void npcm_gcr_realize(DeviceState *dev, Error **errp)
* https://github.com/Nuvoton-Israel/u-boot/blob/2aef993bd2aafeb5408dbaad0f3ce099ee40c4aa/board/nuvoton/poleg/poleg.c#L244
*/
s->reset_intcr3 |= ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8;
+
+ /*
+ * The boot block starting from 0.0.6 for NPCM8xx SoCs stores the DRAM size
+ * in the SCRPAD2 registers. We need to set this field correctly since
+ * the initialization is skipped as we mentioned above.
+ * https://github.com/Nuvoton-Israel/u-boot/blob/npcm8mnx-v2019.01_tmp/board/nuvoton/arbel/arbel.c#L737
+ */
+ s->reset_scrpad_b = dram_size;
}
static void npcm_gcr_init(Object *obj)
@@ -370,16 +391,19 @@ static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
c->nr_regs = NPCM7XX_GCR_NR_REGS;
c->cold_reset_values = npcm7xx_cold_reset_values;
+ rc->phases.enter = npcm7xx_gcr_enter_reset;
}
static void npcm8xx_gcr_class_init(ObjectClass *klass, void *data)
{
NPCMGCRClass *c = NPCM_GCR_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->desc = "NPCM8xx System Global Control Registers";
c->nr_regs = NPCM8XX_GCR_NR_REGS;
c->cold_reset_values = npcm8xx_cold_reset_values;
+ rc->phases.enter = npcm8xx_gcr_enter_reset;
}
static const TypeInfo npcm_gcr_info[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 33/41] hw/misc: Support 8-bytes memop in NPCM GCR module
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (31 preceding siblings ...)
2025-02-20 16:21 ` [PULL 32/41] hw/misc: Store DRAM size in NPCM8XX GCR Module Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 34/41] hw/misc: Rename npcm7xx_clk to npcm_clk Peter Maydell
` (8 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
Message-id: 20250219184609.1839281-10-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/npcm_gcr.c | 92 ++++++++++++++++++++++++++++++++++----------
hw/misc/trace-events | 4 +-
2 files changed, 73 insertions(+), 23 deletions(-)
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index 9e4a6aee611..ec16ea620eb 100644
--- a/hw/misc/npcm_gcr.c
+++ b/hw/misc/npcm_gcr.c
@@ -200,6 +200,7 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size)
uint32_t reg = offset / sizeof(uint32_t);
NPCMGCRState *s = opaque;
NPCMGCRClass *c = NPCM_GCR_GET_CLASS(s);
+ uint64_t value;
if (reg >= c->nr_regs) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -208,9 +209,21 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size)
return 0;
}
- trace_npcm_gcr_read(offset, s->regs[reg]);
+ switch (size) {
+ case 4:
+ value = s->regs[reg];
+ break;
- return s->regs[reg];
+ case 8:
+ value = deposit64(s->regs[reg], 32, 32, s->regs[reg + 1]);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+
+ trace_npcm_gcr_read(offset, value);
+ return value;
}
static void npcm_gcr_write(void *opaque, hwaddr offset,
@@ -230,29 +243,65 @@ static void npcm_gcr_write(void *opaque, hwaddr offset,
return;
}
- switch (reg) {
- case NPCM7XX_GCR_PDID:
- case NPCM7XX_GCR_PWRON:
- case NPCM7XX_GCR_INTSR:
- qemu_log_mask(LOG_GUEST_ERROR,
- "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
- __func__, offset);
- return;
+ switch (size) {
+ case 4:
+ switch (reg) {
+ case NPCM7XX_GCR_PDID:
+ case NPCM7XX_GCR_PWRON:
+ case NPCM7XX_GCR_INTSR:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+ __func__, offset);
+ return;
- case NPCM7XX_GCR_RESSR:
- case NPCM7XX_GCR_CP2BST:
- /* Write 1 to clear */
- value = s->regs[reg] & ~value;
+ case NPCM7XX_GCR_RESSR:
+ case NPCM7XX_GCR_CP2BST:
+ /* Write 1 to clear */
+ value = s->regs[reg] & ~value;
+ break;
+
+ case NPCM7XX_GCR_RLOCKR1:
+ case NPCM7XX_GCR_MDLR:
+ /* Write 1 to set */
+ value |= s->regs[reg];
+ break;
+ };
+ s->regs[reg] = value;
break;
- case NPCM7XX_GCR_RLOCKR1:
- case NPCM7XX_GCR_MDLR:
- /* Write 1 to set */
- value |= s->regs[reg];
+ case 8:
+ s->regs[reg] = value;
+ s->regs[reg + 1] = extract64(v, 32, 32);
break;
- };
- s->regs[reg] = value;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static bool npcm_gcr_check_mem_op(void *opaque, hwaddr offset,
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
+{
+ NPCMGCRClass *c = NPCM_GCR_GET_CLASS(opaque);
+
+ if (offset >= c->nr_regs * sizeof(uint32_t)) {
+ return false;
+ }
+
+ switch (size) {
+ case 4:
+ return true;
+ case 8:
+ if (offset >= NPCM8XX_GCR_SCRPAD_00 * sizeof(uint32_t) &&
+ offset < (NPCM8XX_GCR_NR_REGS - 1) * sizeof(uint32_t)) {
+ return true;
+ } else {
+ return false;
+ }
+ default:
+ return false;
+ }
}
static const struct MemoryRegionOps npcm_gcr_ops = {
@@ -261,7 +310,8 @@ static const struct MemoryRegionOps npcm_gcr_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
- .max_access_size = 4,
+ .max_access_size = 8,
+ .accepts = npcm_gcr_check_mem_op,
.unaligned = false,
},
};
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 0f7204a237e..f25dbd6030c 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -135,8 +135,8 @@ npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " valu
npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
# npcm_gcr.c
-npcm_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
-npcm_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx64
+npcm_gcr_write(uint64_t offset, uint64_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx64
# npcm7xx_mft.c
npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 34/41] hw/misc: Rename npcm7xx_clk to npcm_clk
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (32 preceding siblings ...)
2025-02-20 16:21 ` [PULL 33/41] hw/misc: Support 8-bytes memop in NPCM GCR module Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 35/41] hw/misc: Move NPCM7XX CLK to NPCM CLK Peter Maydell
` (7 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
NPCM7XX and NPCM8XX have a different set of CLK registers. This
commit changes the name of the clk files to be used by both
NPCM7XX and NPCM8XX CLK modules.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-11-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/npcm7xx.h | 2 +-
include/hw/misc/{npcm7xx_clk.h => npcm_clk.h} | 6 +++---
hw/misc/{npcm7xx_clk.c => npcm_clk.c} | 2 +-
hw/misc/meson.build | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
rename include/hw/misc/{npcm7xx_clk.h => npcm_clk.h} (98%)
rename hw/misc/{npcm7xx_clk.c => npcm_clk.c} (99%)
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index 2e708471ece..e80fd91f204 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -23,7 +23,7 @@
#include "hw/gpio/npcm7xx_gpio.h"
#include "hw/i2c/npcm7xx_smbus.h"
#include "hw/mem/npcm7xx_mc.h"
-#include "hw/misc/npcm7xx_clk.h"
+#include "hw/misc/npcm_clk.h"
#include "hw/misc/npcm_gcr.h"
#include "hw/misc/npcm7xx_mft.h"
#include "hw/misc/npcm7xx_pwm.h"
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm_clk.h
similarity index 98%
rename from include/hw/misc/npcm7xx_clk.h
rename to include/hw/misc/npcm_clk.h
index 5ed4a4672b3..0aef81e10c8 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm_clk.h
@@ -13,8 +13,8 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
-#ifndef NPCM7XX_CLK_H
-#define NPCM7XX_CLK_H
+#ifndef NPCM_CLK_H
+#define NPCM_CLK_H
#include "exec/memory.h"
#include "hw/clock.h"
@@ -177,4 +177,4 @@ struct NPCM7xxCLKState {
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
-#endif /* NPCM7XX_CLK_H */
+#endif /* NPCM_CLK_H */
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm_clk.c
similarity index 99%
rename from hw/misc/npcm7xx_clk.c
rename to hw/misc/npcm_clk.c
index 46f907b61c2..2bcb731099e 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm_clk.c
@@ -16,7 +16,7 @@
#include "qemu/osdep.h"
-#include "hw/misc/npcm7xx_clk.h"
+#include "hw/misc/npcm_clk.h"
#include "hw/timer/npcm7xx_timer.h"
#include "hw/qdev-clock.h"
#include "migration/vmstate.h"
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 554eb8df5bc..edd36a334d7 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -69,7 +69,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files(
'imx_rngc.c',
))
system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
- 'npcm7xx_clk.c',
+ 'npcm_clk.c',
'npcm_gcr.c',
'npcm7xx_mft.c',
'npcm7xx_pwm.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 35/41] hw/misc: Move NPCM7XX CLK to NPCM CLK
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (33 preceding siblings ...)
2025-02-20 16:21 ` [PULL 34/41] hw/misc: Rename npcm7xx_clk to npcm_clk Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 36/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
` (6 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-12-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/npcm7xx.h | 2 +-
include/hw/misc/npcm_clk.h | 24 +++++----
hw/misc/npcm_clk.c | 106 +++++++++++++++++++++----------------
hw/misc/trace-events | 6 +--
4 files changed, 77 insertions(+), 61 deletions(-)
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index e80fd91f204..56536565b74 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -90,7 +90,7 @@ struct NPCM7xxState {
MemoryRegion *dram;
NPCMGCRState gcr;
- NPCM7xxCLKState clk;
+ NPCMCLKState clk;
NPCM7xxTimerCtrlState tim[3];
NPCM7xxADCState adc;
NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES];
diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h
index 0aef81e10c8..db03b46a52b 100644
--- a/include/hw/misc/npcm_clk.h
+++ b/include/hw/misc/npcm_clk.h
@@ -20,11 +20,12 @@
#include "hw/clock.h"
#include "hw/sysbus.h"
-/*
- * Number of registers in our device state structure. Don't change this without
- * incrementing the version_id in the vmstate.
- */
#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
+/*
+ * Number of maximum registers in NPCM device state structure. Don't change
+ * this without incrementing the version_id in the vmstate.
+ */
+#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
@@ -80,7 +81,7 @@ typedef enum NPCM7xxClockDivider {
NPCM7XX_CLOCK_NR_DIVIDERS,
} NPCM7xxClockConverter;
-typedef struct NPCM7xxCLKState NPCM7xxCLKState;
+typedef struct NPCMCLKState NPCMCLKState;
/**
* struct NPCM7xxClockPLLState - A PLL module in CLK module.
@@ -94,7 +95,7 @@ typedef struct NPCM7xxClockPLLState {
DeviceState parent;
const char *name;
- NPCM7xxCLKState *clk;
+ NPCMCLKState *clk;
Clock *clock_in;
Clock *clock_out;
@@ -115,7 +116,7 @@ typedef struct NPCM7xxClockSELState {
DeviceState parent;
const char *name;
- NPCM7xxCLKState *clk;
+ NPCMCLKState *clk;
uint8_t input_size;
Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
Clock *clock_out;
@@ -140,7 +141,7 @@ typedef struct NPCM7xxClockDividerState {
DeviceState parent;
const char *name;
- NPCM7xxCLKState *clk;
+ NPCMCLKState *clk;
Clock *clock_in;
Clock *clock_out;
@@ -155,7 +156,7 @@ typedef struct NPCM7xxClockDividerState {
};
} NPCM7xxClockDividerState;
-struct NPCM7xxCLKState {
+struct NPCMCLKState {
SysBusDevice parent;
MemoryRegion iomem;
@@ -165,7 +166,7 @@ struct NPCM7xxCLKState {
NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
- uint32_t regs[NPCM7XX_CLK_NR_REGS];
+ uint32_t regs[NPCM_CLK_MAX_NR_REGS];
/* Time reference for SECCNT and CNTR25M, initialized by power on reset */
int64_t ref_ns;
@@ -174,7 +175,8 @@ struct NPCM7xxCLKState {
Clock *clkref;
};
+#define TYPE_NPCM_CLK "npcm-clk"
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMCLKState, NPCM_CLK)
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
-OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
#endif /* NPCM_CLK_H */
diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c
index 2bcb731099e..0ecf0df3bbf 100644
--- a/hw/misc/npcm_clk.c
+++ b/hw/misc/npcm_clk.c
@@ -198,7 +198,7 @@ static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
}
}
-static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
+static void npcm7xx_clk_update_all_plls(NPCMCLKState *clk)
{
int i;
@@ -207,7 +207,7 @@ static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
}
}
-static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
+static void npcm7xx_clk_update_all_sels(NPCMCLKState *clk)
{
int i;
@@ -216,7 +216,7 @@ static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
}
}
-static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
+static void npcm7xx_clk_update_all_dividers(NPCMCLKState *clk)
{
int i;
@@ -225,7 +225,7 @@ static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
}
}
-static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
+static void npcm7xx_clk_update_all_clocks(NPCMCLKState *clk)
{
clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
npcm7xx_clk_update_all_plls(clk);
@@ -635,7 +635,7 @@ static void npcm7xx_clk_divider_init(Object *obj)
}
static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
- NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
+ NPCMCLKState *clk, const PLLInitInfo *init_info)
{
pll->name = init_info->name;
pll->clk = clk;
@@ -647,7 +647,7 @@ static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
}
static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
- NPCM7xxCLKState *clk, const SELInitInfo *init_info)
+ NPCMCLKState *clk, const SELInitInfo *init_info)
{
int input_size = init_info->input_size;
@@ -664,7 +664,7 @@ static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
}
static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
- NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
+ NPCMCLKState *clk, const DividerInitInfo *init_info)
{
div->name = init_info->name;
div->clk = clk;
@@ -683,7 +683,7 @@ static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
}
}
-static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
+static Clock *npcm7xx_get_clock(NPCMCLKState *clk, ClockSrcType type,
int index)
{
switch (type) {
@@ -700,7 +700,7 @@ static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
}
}
-static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
+static void npcm7xx_connect_clocks(NPCMCLKState *clk)
{
int i, j;
Clock *src;
@@ -724,10 +724,10 @@ static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
}
}
-static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
+static uint64_t npcm_clk_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
- NPCM7xxCLKState *s = opaque;
+ NPCMCLKState *s = opaque;
int64_t now_ns;
uint32_t value = 0;
@@ -766,19 +766,19 @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
break;
};
- trace_npcm7xx_clk_read(offset, value);
+ trace_npcm_clk_read(offset, value);
return value;
}
-static void npcm7xx_clk_write(void *opaque, hwaddr offset,
+static void npcm_clk_write(void *opaque, hwaddr offset,
uint64_t v, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
- NPCM7xxCLKState *s = opaque;
+ NPCMCLKState *s = opaque;
uint32_t value = v;
- trace_npcm7xx_clk_write(offset, value);
+ trace_npcm_clk_write(offset, value);
if (reg >= NPCM7XX_CLK_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -842,7 +842,7 @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
int level)
{
- NPCM7xxCLKState *clk = NPCM7XX_CLK(opaque);
+ NPCMCLKState *clk = NPCM_CLK(opaque);
uint32_t rcr;
g_assert(n >= 0 && n <= NPCM7XX_NR_WATCHDOGS);
@@ -856,9 +856,9 @@ static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
}
}
-static const struct MemoryRegionOps npcm7xx_clk_ops = {
- .read = npcm7xx_clk_read,
- .write = npcm7xx_clk_write,
+static const struct MemoryRegionOps npcm_clk_ops = {
+ .read = npcm_clk_read,
+ .write = npcm_clk_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
@@ -867,9 +867,9 @@ static const struct MemoryRegionOps npcm7xx_clk_ops = {
},
};
-static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
+static void npcm_clk_enter_reset(Object *obj, ResetType type)
{
- NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
+ NPCMCLKState *s = NPCM_CLK(obj);
QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
@@ -882,7 +882,7 @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
*/
}
-static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
+static void npcm7xx_clk_init_clock_hierarchy(NPCMCLKState *s)
{
int i;
@@ -918,19 +918,19 @@ static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
}
-static void npcm7xx_clk_init(Object *obj)
+static void npcm_clk_init(Object *obj)
{
- NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
+ NPCMCLKState *s = NPCM_CLK(obj);
- memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
- TYPE_NPCM7XX_CLK, 4 * KiB);
+ memory_region_init_io(&s->iomem, obj, &npcm_clk_ops, s,
+ TYPE_NPCM_CLK, 4 * KiB);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
}
-static int npcm7xx_clk_post_load(void *opaque, int version_id)
+static int npcm_clk_post_load(void *opaque, int version_id)
{
if (version_id >= 1) {
- NPCM7xxCLKState *clk = opaque;
+ NPCMCLKState *clk = opaque;
npcm7xx_clk_update_all_clocks(clk);
}
@@ -938,10 +938,10 @@ static int npcm7xx_clk_post_load(void *opaque, int version_id)
return 0;
}
-static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
+static void npcm_clk_realize(DeviceState *dev, Error **errp)
{
int i;
- NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
+ NPCMCLKState *s = NPCM_CLK(dev);
qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
@@ -996,15 +996,15 @@ static const VMStateDescription vmstate_npcm7xx_clk_divider = {
},
};
-static const VMStateDescription vmstate_npcm7xx_clk = {
- .name = "npcm7xx-clk",
- .version_id = 1,
- .minimum_version_id = 1,
- .post_load = npcm7xx_clk_post_load,
+static const VMStateDescription vmstate_npcm_clk = {
+ .name = "npcm-clk",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .post_load = npcm_clk_post_load,
.fields = (const VMStateField[]) {
- VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
- VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
- VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
+ VMSTATE_UINT32_ARRAY(regs, NPCMCLKState, NPCM_CLK_MAX_NR_REGS),
+ VMSTATE_INT64(ref_ns, NPCMCLKState),
+ VMSTATE_CLOCK(clkref, NPCMCLKState),
VMSTATE_END_OF_LIST(),
},
};
@@ -1033,17 +1033,23 @@ static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_npcm7xx_clk_divider;
}
-static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
+static void npcm_clk_class_init(ObjectClass *klass, void *data)
{
ResettableClass *rc = RESETTABLE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM7XX_CLK_NR_REGS);
+ dc->vmsd = &vmstate_npcm_clk;
+ dc->realize = npcm_clk_realize;
+ rc->phases.enter = npcm_clk_enter_reset;
+}
+static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS);
+ QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END != NPCM7XX_CLK_NR_REGS);
dc->desc = "NPCM7xx Clock Control Registers";
- dc->vmsd = &vmstate_npcm7xx_clk;
- dc->realize = npcm7xx_clk_realize;
- rc->phases.enter = npcm7xx_clk_enter_reset;
}
static const TypeInfo npcm7xx_clk_pll_info = {
@@ -1070,11 +1076,18 @@ static const TypeInfo npcm7xx_clk_divider_info = {
.class_init = npcm7xx_clk_divider_class_init,
};
+static const TypeInfo npcm_clk_info = {
+ .name = TYPE_NPCM_CLK,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCMCLKState),
+ .instance_init = npcm_clk_init,
+ .class_init = npcm_clk_class_init,
+ .abstract = true,
+};
+
static const TypeInfo npcm7xx_clk_info = {
.name = TYPE_NPCM7XX_CLK,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(NPCM7xxCLKState),
- .instance_init = npcm7xx_clk_init,
+ .parent = TYPE_NPCM_CLK,
.class_init = npcm7xx_clk_class_init,
};
@@ -1083,6 +1096,7 @@ static void npcm7xx_clk_register_type(void)
type_register_static(&npcm7xx_clk_pll_info);
type_register_static(&npcm7xx_clk_sel_info);
type_register_static(&npcm7xx_clk_divider_info);
+ type_register_static(&npcm_clk_info);
type_register_static(&npcm7xx_clk_info);
}
type_init(npcm7xx_clk_register_type);
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index f25dbd6030c..4383808d7ad 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -130,9 +130,9 @@ mos6522_set_sr_int(void) "set sr_int"
mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64
mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x"
-# npcm7xx_clk.c
-npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
-npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+# npcm_clk.c
+npcm_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
# npcm_gcr.c
npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx64
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 36/41] hw/misc: Add nr_regs and cold_reset_values to NPCM CLK
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (34 preceding siblings ...)
2025-02-20 16:21 ` [PULL 35/41] hw/misc: Move NPCM7XX CLK to NPCM CLK Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 37/41] hw/misc: Support NPCM8XX CLK Module Registers Peter Maydell
` (5 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-13-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/misc/npcm_clk.h | 9 ++++++++-
hw/misc/npcm_clk.c | 18 ++++++++++++------
hw/misc/npcm_gcr.c | 2 ++
3 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h
index db03b46a52b..f47614ac8da 100644
--- a/include/hw/misc/npcm_clk.h
+++ b/include/hw/misc/npcm_clk.h
@@ -175,8 +175,15 @@ struct NPCMCLKState {
Clock *clkref;
};
+typedef struct NPCMCLKClass {
+ SysBusDeviceClass parent;
+
+ size_t nr_regs;
+ const uint32_t *cold_reset_values;
+} NPCMCLKClass;
+
#define TYPE_NPCM_CLK "npcm-clk"
-OBJECT_DECLARE_SIMPLE_TYPE(NPCMCLKState, NPCM_CLK)
+OBJECT_DECLARE_TYPE(NPCMCLKState, NPCMCLKClass, NPCM_CLK)
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
#endif /* NPCM_CLK_H */
diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c
index 0ecf0df3bbf..78144b14e37 100644
--- a/hw/misc/npcm_clk.c
+++ b/hw/misc/npcm_clk.c
@@ -81,7 +81,7 @@ enum NPCM7xxCLKRegisters {
* All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
* core domain reset, but this reset type is not yet supported by QEMU.
*/
-static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
+static const uint32_t npcm7xx_cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
[NPCM7XX_CLK_CLKEN1] = 0xffffffff,
[NPCM7XX_CLK_CLKSEL] = 0x004aaaaa,
[NPCM7XX_CLK_CLKDIV1] = 0x5413f855,
@@ -728,10 +728,11 @@ static uint64_t npcm_clk_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t reg = offset / sizeof(uint32_t);
NPCMCLKState *s = opaque;
+ NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s);
int64_t now_ns;
uint32_t value = 0;
- if (reg >= NPCM7XX_CLK_NR_REGS) {
+ if (reg >= c->nr_regs) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: offset 0x%04" HWADDR_PRIx " out of range\n",
__func__, offset);
@@ -776,11 +777,12 @@ static void npcm_clk_write(void *opaque, hwaddr offset,
{
uint32_t reg = offset / sizeof(uint32_t);
NPCMCLKState *s = opaque;
+ NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s);
uint32_t value = v;
trace_npcm_clk_write(offset, value);
- if (reg >= NPCM7XX_CLK_NR_REGS) {
+ if (reg >= c->nr_regs) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: offset 0x%04" HWADDR_PRIx " out of range\n",
__func__, offset);
@@ -870,10 +872,10 @@ static const struct MemoryRegionOps npcm_clk_ops = {
static void npcm_clk_enter_reset(Object *obj, ResetType type)
{
NPCMCLKState *s = NPCM_CLK(obj);
+ NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s);
- QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
-
- memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
+ g_assert(sizeof(s->regs) >= c->nr_regs * sizeof(uint32_t));
+ memcpy(s->regs, c->cold_reset_values, sizeof(s->regs));
s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
npcm7xx_clk_update_all_clocks(s);
/*
@@ -1045,11 +1047,14 @@ static void npcm_clk_class_init(ObjectClass *klass, void *data)
static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
{
+ NPCMCLKClass *c = NPCM_CLK_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS);
QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END != NPCM7XX_CLK_NR_REGS);
dc->desc = "NPCM7xx Clock Control Registers";
+ c->nr_regs = NPCM7XX_CLK_NR_REGS;
+ c->cold_reset_values = npcm7xx_cold_reset_values;
}
static const TypeInfo npcm7xx_clk_pll_info = {
@@ -1081,6 +1086,7 @@ static const TypeInfo npcm_clk_info = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCMCLKState),
.instance_init = npcm_clk_init,
+ .class_size = sizeof(NPCMCLKClass),
.class_init = npcm_clk_class_init,
.abstract = true,
};
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index ec16ea620eb..4e8ce2cb89d 100644
--- a/hw/misc/npcm_gcr.c
+++ b/hw/misc/npcm_gcr.c
@@ -215,6 +215,7 @@ static uint64_t npcm_gcr_read(void *opaque, hwaddr offset, unsigned size)
break;
case 8:
+ g_assert(!(reg & 1));
value = deposit64(s->regs[reg], 32, 32, s->regs[reg + 1]);
break;
@@ -270,6 +271,7 @@ static void npcm_gcr_write(void *opaque, hwaddr offset,
break;
case 8:
+ g_assert(!(reg & 1));
s->regs[reg] = value;
s->regs[reg + 1] = extract64(v, 32, 32);
break;
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 37/41] hw/misc: Support NPCM8XX CLK Module Registers
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (35 preceding siblings ...)
2025-02-20 16:21 ` [PULL 36/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 38/41] hw/net: Add NPCM8XX PCS Module Peter Maydell
` (4 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
NPCM8XX adds a few new registers and have a different set of reset
values to the CLK modules. This patch supports them.
This patch doesn't support the new clock values generated by these
registers. Currently no modules use these new clock values so they
are not necessary at this point.
Implementation of these clocks might be required when implementing
these modules.
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-14-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/misc/npcm_clk.h | 10 +++-
hw/misc/npcm_clk.c | 117 +++++++++++++++++++++++++++++++++++--
2 files changed, 119 insertions(+), 8 deletions(-)
diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h
index f47614ac8da..8fa1e14bddf 100644
--- a/include/hw/misc/npcm_clk.h
+++ b/include/hw/misc/npcm_clk.h
@@ -1,5 +1,5 @@
/*
- * Nuvoton NPCM7xx Clock Control Registers.
+ * Nuvoton NPCM7xx/8xx Clock Control Registers.
*
* Copyright 2020 Google LLC
*
@@ -21,11 +21,12 @@
#include "hw/sysbus.h"
#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
+#define NPCM8XX_CLK_NR_REGS (0xc4 / sizeof(uint32_t))
/*
* Number of maximum registers in NPCM device state structure. Don't change
* this without incrementing the version_id in the vmstate.
*/
-#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS
+#define NPCM_CLK_MAX_NR_REGS NPCM8XX_CLK_NR_REGS
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
@@ -162,6 +163,10 @@ struct NPCMCLKState {
MemoryRegion iomem;
/* Clock converters */
+ /*
+ * TODO: Implement unique clock converters for NPCM8xx.
+ * NPCM8xx adds a few more clock outputs.
+ */
NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
@@ -185,5 +190,6 @@ typedef struct NPCMCLKClass {
#define TYPE_NPCM_CLK "npcm-clk"
OBJECT_DECLARE_TYPE(NPCMCLKState, NPCMCLKClass, NPCM_CLK)
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
+#define TYPE_NPCM8XX_CLK "npcm8xx-clk"
#endif /* NPCM_CLK_H */
diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c
index 78144b14e37..d1f29759d59 100644
--- a/hw/misc/npcm_clk.c
+++ b/hw/misc/npcm_clk.c
@@ -1,5 +1,5 @@
/*
- * Nuvoton NPCM7xx Clock Control Registers.
+ * Nuvoton NPCM7xx/8xx Clock Control Registers.
*
* Copyright 2020 Google LLC
*
@@ -72,7 +72,57 @@ enum NPCM7xxCLKRegisters {
NPCM7XX_CLK_AHBCKFI,
NPCM7XX_CLK_SECCNT,
NPCM7XX_CLK_CNTR25M,
- NPCM7XX_CLK_REGS_END,
+};
+
+enum NPCM8xxCLKRegisters {
+ NPCM8XX_CLK_CLKEN1,
+ NPCM8XX_CLK_CLKSEL,
+ NPCM8XX_CLK_CLKDIV1,
+ NPCM8XX_CLK_PLLCON0,
+ NPCM8XX_CLK_PLLCON1,
+ NPCM8XX_CLK_SWRSTR,
+ NPCM8XX_CLK_IPSRST1 = 0x20 / sizeof(uint32_t),
+ NPCM8XX_CLK_IPSRST2,
+ NPCM8XX_CLK_CLKEN2,
+ NPCM8XX_CLK_CLKDIV2,
+ NPCM8XX_CLK_CLKEN3,
+ NPCM8XX_CLK_IPSRST3,
+ NPCM8XX_CLK_WD0RCR,
+ NPCM8XX_CLK_WD1RCR,
+ NPCM8XX_CLK_WD2RCR,
+ NPCM8XX_CLK_SWRSTC1,
+ NPCM8XX_CLK_SWRSTC2,
+ NPCM8XX_CLK_SWRSTC3,
+ NPCM8XX_CLK_TIPRSTC,
+ NPCM8XX_CLK_PLLCON2,
+ NPCM8XX_CLK_CLKDIV3,
+ NPCM8XX_CLK_CORSTC,
+ NPCM8XX_CLK_PLLCONG,
+ NPCM8XX_CLK_AHBCKFI,
+ NPCM8XX_CLK_SECCNT,
+ NPCM8XX_CLK_CNTR25M,
+ /* Registers unique to NPCM8XX SoC */
+ NPCM8XX_CLK_CLKEN4,
+ NPCM8XX_CLK_IPSRST4,
+ NPCM8XX_CLK_BUSTO,
+ NPCM8XX_CLK_CLKDIV4,
+ NPCM8XX_CLK_WD0RCRB,
+ NPCM8XX_CLK_WD1RCRB,
+ NPCM8XX_CLK_WD2RCRB,
+ NPCM8XX_CLK_SWRSTC1B,
+ NPCM8XX_CLK_SWRSTC2B,
+ NPCM8XX_CLK_SWRSTC3B,
+ NPCM8XX_CLK_TIPRSTCB,
+ NPCM8XX_CLK_CORSTCB,
+ NPCM8XX_CLK_IPSRSTDIS1,
+ NPCM8XX_CLK_IPSRSTDIS2,
+ NPCM8XX_CLK_IPSRSTDIS3,
+ NPCM8XX_CLK_IPSRSTDIS4,
+ NPCM8XX_CLK_CLKENDIS1,
+ NPCM8XX_CLK_CLKENDIS2,
+ NPCM8XX_CLK_CLKENDIS3,
+ NPCM8XX_CLK_CLKENDIS4,
+ NPCM8XX_CLK_THRTL_CNT,
};
/*
@@ -103,6 +153,46 @@ static const uint32_t npcm7xx_cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
};
+/*
+ * These reset values were taken from version 0.92 of the NPCM8xx data sheet.
+ */
+static const uint32_t npcm8xx_cold_reset_values[NPCM8XX_CLK_NR_REGS] = {
+ [NPCM8XX_CLK_CLKEN1] = 0xffffffff,
+ [NPCM8XX_CLK_CLKSEL] = 0x154aaaaa,
+ [NPCM8XX_CLK_CLKDIV1] = 0x5413f855,
+ [NPCM8XX_CLK_PLLCON0] = 0x00222101 | PLLCON_LOKI,
+ [NPCM8XX_CLK_PLLCON1] = 0x00202101 | PLLCON_LOKI,
+ [NPCM8XX_CLK_IPSRST1] = 0x00001000,
+ [NPCM8XX_CLK_IPSRST2] = 0x80000000,
+ [NPCM8XX_CLK_CLKEN2] = 0xffffffff,
+ [NPCM8XX_CLK_CLKDIV2] = 0xaa4f8f9f,
+ [NPCM8XX_CLK_CLKEN3] = 0xffffffff,
+ [NPCM8XX_CLK_IPSRST3] = 0x03000000,
+ [NPCM8XX_CLK_WD0RCR] = 0xffffffff,
+ [NPCM8XX_CLK_WD1RCR] = 0xffffffff,
+ [NPCM8XX_CLK_WD2RCR] = 0xffffffff,
+ [NPCM8XX_CLK_SWRSTC1] = 0x00000003,
+ [NPCM8XX_CLK_SWRSTC2] = 0x00000001,
+ [NPCM8XX_CLK_SWRSTC3] = 0x00000001,
+ [NPCM8XX_CLK_TIPRSTC] = 0x00000001,
+ [NPCM8XX_CLK_PLLCON2] = 0x00c02105 | PLLCON_LOKI,
+ [NPCM8XX_CLK_CLKDIV3] = 0x00009100,
+ [NPCM8XX_CLK_CORSTC] = 0x04000003,
+ [NPCM8XX_CLK_PLLCONG] = 0x01228606 | PLLCON_LOKI,
+ [NPCM8XX_CLK_AHBCKFI] = 0x000000c8,
+ [NPCM8XX_CLK_CLKEN4] = 0xffffffff,
+ [NPCM8XX_CLK_CLKDIV4] = 0x70009000,
+ [NPCM8XX_CLK_IPSRST4] = 0x02000000,
+ [NPCM8XX_CLK_WD0RCRB] = 0xfffffe71,
+ [NPCM8XX_CLK_WD1RCRB] = 0xfffffe71,
+ [NPCM8XX_CLK_WD2RCRB] = 0xfffffe71,
+ [NPCM8XX_CLK_SWRSTC1B] = 0xfffffe71,
+ [NPCM8XX_CLK_SWRSTC2B] = 0xfffffe71,
+ [NPCM8XX_CLK_SWRSTC3B] = 0xfffffe71,
+ [NPCM8XX_CLK_TIPRSTCB] = 0xfffffe71,
+ [NPCM8XX_CLK_CORSTCB] = 0xfffffe71,
+};
+
/* The number of watchdogs that can trigger a reset. */
#define NPCM7XX_NR_WATCHDOGS (3)
@@ -1000,8 +1090,8 @@ static const VMStateDescription vmstate_npcm7xx_clk_divider = {
static const VMStateDescription vmstate_npcm_clk = {
.name = "npcm-clk",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.post_load = npcm_clk_post_load,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, NPCMCLKState, NPCM_CLK_MAX_NR_REGS),
@@ -1050,13 +1140,21 @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
NPCMCLKClass *c = NPCM_CLK_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS);
- QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END != NPCM7XX_CLK_NR_REGS);
dc->desc = "NPCM7xx Clock Control Registers";
c->nr_regs = NPCM7XX_CLK_NR_REGS;
c->cold_reset_values = npcm7xx_cold_reset_values;
}
+static void npcm8xx_clk_class_init(ObjectClass *klass, void *data)
+{
+ NPCMCLKClass *c = NPCM_CLK_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "NPCM8xx Clock Control Registers";
+ c->nr_regs = NPCM8XX_CLK_NR_REGS;
+ c->cold_reset_values = npcm8xx_cold_reset_values;
+}
+
static const TypeInfo npcm7xx_clk_pll_info = {
.name = TYPE_NPCM7XX_CLOCK_PLL,
.parent = TYPE_DEVICE,
@@ -1097,6 +1195,12 @@ static const TypeInfo npcm7xx_clk_info = {
.class_init = npcm7xx_clk_class_init,
};
+static const TypeInfo npcm8xx_clk_info = {
+ .name = TYPE_NPCM8XX_CLK,
+ .parent = TYPE_NPCM_CLK,
+ .class_init = npcm8xx_clk_class_init,
+};
+
static void npcm7xx_clk_register_type(void)
{
type_register_static(&npcm7xx_clk_pll_info);
@@ -1104,5 +1208,6 @@ static void npcm7xx_clk_register_type(void)
type_register_static(&npcm7xx_clk_divider_info);
type_register_static(&npcm_clk_info);
type_register_static(&npcm7xx_clk_info);
+ type_register_static(&npcm8xx_clk_info);
}
type_init(npcm7xx_clk_register_type);
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 38/41] hw/net: Add NPCM8XX PCS Module
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (36 preceding siblings ...)
2025-02-20 16:21 ` [PULL 37/41] hw/misc: Support NPCM8XX CLK Module Registers Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 39/41] hw/arm: Add NPCM8XX SoC Peter Maydell
` (3 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250219184609.1839281-15-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/net/npcm_pcs.h | 42 ++++
hw/net/npcm_pcs.c | 410 ++++++++++++++++++++++++++++++++++++++
hw/net/meson.build | 1 +
hw/net/trace-events | 4 +-
4 files changed, 455 insertions(+), 2 deletions(-)
create mode 100644 include/hw/net/npcm_pcs.h
create mode 100644 hw/net/npcm_pcs.c
diff --git a/include/hw/net/npcm_pcs.h b/include/hw/net/npcm_pcs.h
new file mode 100644
index 00000000000..d5c481ad70d
--- /dev/null
+++ b/include/hw/net/npcm_pcs.h
@@ -0,0 +1,42 @@
+/*
+ * Nuvoton NPCM8xx PCS Module
+ *
+ * Copyright 2022 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef NPCM_PCS_H
+#define NPCM_PCS_H
+
+#include "hw/sysbus.h"
+
+#define NPCM_PCS_NR_SR_CTLS (0x12 / sizeof(uint16_t))
+#define NPCM_PCS_NR_SR_MIIS (0x20 / sizeof(uint16_t))
+#define NPCM_PCS_NR_SR_TIMS (0x22 / sizeof(uint16_t))
+#define NPCM_PCS_NR_VR_MIIS (0x1c6 / sizeof(uint16_t))
+
+struct NPCMPCSState {
+ SysBusDevice parent;
+
+ MemoryRegion iomem;
+
+ uint16_t indirect_access_base;
+ uint16_t sr_ctl[NPCM_PCS_NR_SR_CTLS];
+ uint16_t sr_mii[NPCM_PCS_NR_SR_MIIS];
+ uint16_t sr_tim[NPCM_PCS_NR_SR_TIMS];
+ uint16_t vr_mii[NPCM_PCS_NR_VR_MIIS];
+};
+
+#define TYPE_NPCM_PCS "npcm-pcs"
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMPCSState, NPCM_PCS)
+
+#endif /* NPCM_PCS_H */
diff --git a/hw/net/npcm_pcs.c b/hw/net/npcm_pcs.c
new file mode 100644
index 00000000000..ce5034e2343
--- /dev/null
+++ b/hw/net/npcm_pcs.c
@@ -0,0 +1,410 @@
+/*
+ * Nuvoton NPCM8xx PCS Module
+ *
+ * Copyright 2022 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+/*
+ * Disclaimer:
+ * Currently we only implemented the default values of the registers and
+ * the soft reset feature. These are required to boot up the GMAC module
+ * in Linux kernel for NPCM845 boards. Other functionalities are not modeled.
+ */
+
+#include "qemu/osdep.h"
+
+#include "exec/hwaddr.h"
+#include "hw/registerfields.h"
+#include "hw/net/npcm_pcs.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+#define NPCM_PCS_IND_AC_BA 0x1fe
+#define NPCM_PCS_IND_SR_CTL 0x1e00
+#define NPCM_PCS_IND_SR_MII 0x1f00
+#define NPCM_PCS_IND_SR_TIM 0x1f07
+#define NPCM_PCS_IND_VR_MII 0x1f80
+
+REG16(NPCM_PCS_SR_CTL_ID1, 0x08)
+REG16(NPCM_PCS_SR_CTL_ID2, 0x0a)
+REG16(NPCM_PCS_SR_CTL_STS, 0x10)
+
+REG16(NPCM_PCS_SR_MII_CTRL, 0x00)
+REG16(NPCM_PCS_SR_MII_STS, 0x02)
+REG16(NPCM_PCS_SR_MII_DEV_ID1, 0x04)
+REG16(NPCM_PCS_SR_MII_DEV_ID2, 0x06)
+REG16(NPCM_PCS_SR_MII_AN_ADV, 0x08)
+REG16(NPCM_PCS_SR_MII_LP_BABL, 0x0a)
+REG16(NPCM_PCS_SR_MII_AN_EXPN, 0x0c)
+REG16(NPCM_PCS_SR_MII_EXT_STS, 0x1e)
+
+REG16(NPCM_PCS_SR_TIM_SYNC_ABL, 0x10)
+REG16(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x12)
+REG16(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0x14)
+REG16(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x16)
+REG16(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0x18)
+REG16(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x1a)
+REG16(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0x1c)
+REG16(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x1e)
+REG16(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0x20)
+
+REG16(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x000)
+REG16(NPCM_PCS_VR_MII_AN_CTRL, 0x002)
+REG16(NPCM_PCS_VR_MII_AN_INTR_STS, 0x004)
+REG16(NPCM_PCS_VR_MII_TC, 0x006)
+REG16(NPCM_PCS_VR_MII_DBG_CTRL, 0x00a)
+REG16(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x00c)
+REG16(NPCM_PCS_VR_MII_EEE_TXTIMER, 0x010)
+REG16(NPCM_PCS_VR_MII_EEE_RXTIMER, 0x012)
+REG16(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0x014)
+REG16(NPCM_PCS_VR_MII_EEE_MCTRL1, 0x016)
+REG16(NPCM_PCS_VR_MII_DIG_STS, 0x020)
+REG16(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0x022)
+REG16(NPCM_PCS_VR_MII_MISC_STS, 0x030)
+REG16(NPCM_PCS_VR_MII_RX_LSTS, 0x040)
+REG16(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x070)
+REG16(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x074)
+REG16(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x07a)
+REG16(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0x07c)
+REG16(NPCM_PCS_VR_MII_MP_TX_STS, 0x090)
+REG16(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0b0)
+REG16(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x0b2)
+REG16(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x0ba)
+REG16(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0f0)
+REG16(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0f2)
+REG16(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x110)
+REG16(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0x126)
+REG16(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x130)
+REG16(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0x132)
+REG16(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0x134)
+REG16(NPCM_PCS_VR_MII_DIG_CTRL2, 0x1c2)
+REG16(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0x1c4)
+
+/* Register Fields */
+#define NPCM_PCS_SR_MII_CTRL_RST BIT(15)
+
+static const uint16_t npcm_pcs_sr_ctl_cold_reset_values[NPCM_PCS_NR_SR_CTLS] = {
+ [R_NPCM_PCS_SR_CTL_ID1] = 0x699e,
+ [R_NPCM_PCS_SR_CTL_STS] = 0x8000,
+};
+
+static const uint16_t npcm_pcs_sr_mii_cold_reset_values[NPCM_PCS_NR_SR_MIIS] = {
+ [R_NPCM_PCS_SR_MII_CTRL] = 0x1140,
+ [R_NPCM_PCS_SR_MII_STS] = 0x0109,
+ [R_NPCM_PCS_SR_MII_DEV_ID1] = 0x699e,
+ [R_NPCM_PCS_SR_MII_DEV_ID2] = 0xced0,
+ [R_NPCM_PCS_SR_MII_AN_ADV] = 0x0020,
+ [R_NPCM_PCS_SR_MII_EXT_STS] = 0xc000,
+};
+
+static const uint16_t npcm_pcs_sr_tim_cold_reset_values[NPCM_PCS_NR_SR_TIMS] = {
+ [R_NPCM_PCS_SR_TIM_SYNC_ABL] = 0x0003,
+ [R_NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR] = 0x0038,
+ [R_NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR] = 0x0038,
+ [R_NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR] = 0x0058,
+ [R_NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR] = 0x0048,
+};
+
+static const uint16_t npcm_pcs_vr_mii_cold_reset_values[NPCM_PCS_NR_VR_MIIS] = {
+ [R_NPCM_PCS_VR_MII_MMD_DIG_CTRL1] = 0x2400,
+ [R_NPCM_PCS_VR_MII_AN_INTR_STS] = 0x000a,
+ [R_NPCM_PCS_VR_MII_EEE_MCTRL0] = 0x899c,
+ [R_NPCM_PCS_VR_MII_DIG_STS] = 0x0010,
+ [R_NPCM_PCS_VR_MII_MP_TX_BSTCTRL0] = 0x000a,
+ [R_NPCM_PCS_VR_MII_MP_TX_LVLCTRL0] = 0x007f,
+ [R_NPCM_PCS_VR_MII_MP_TX_GENCTRL0] = 0x0001,
+ [R_NPCM_PCS_VR_MII_MP_RX_GENCTRL0] = 0x0100,
+ [R_NPCM_PCS_VR_MII_MP_RX_GENCTRL1] = 0x1100,
+ [R_NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0] = 0x000e,
+ [R_NPCM_PCS_VR_MII_MP_MPLL_CTRL0] = 0x0100,
+ [R_NPCM_PCS_VR_MII_MP_MPLL_CTRL1] = 0x0032,
+ [R_NPCM_PCS_VR_MII_MP_MPLL_STS] = 0x0001,
+ [R_NPCM_PCS_VR_MII_MP_LVL_CTRL] = 0x0019,
+};
+
+static void npcm_pcs_soft_reset(NPCMPCSState *s)
+{
+ memcpy(s->sr_ctl, npcm_pcs_sr_ctl_cold_reset_values,
+ NPCM_PCS_NR_SR_CTLS * sizeof(uint16_t));
+ memcpy(s->sr_mii, npcm_pcs_sr_mii_cold_reset_values,
+ NPCM_PCS_NR_SR_MIIS * sizeof(uint16_t));
+ memcpy(s->sr_tim, npcm_pcs_sr_tim_cold_reset_values,
+ NPCM_PCS_NR_SR_TIMS * sizeof(uint16_t));
+ memcpy(s->vr_mii, npcm_pcs_vr_mii_cold_reset_values,
+ NPCM_PCS_NR_VR_MIIS * sizeof(uint16_t));
+}
+
+static uint16_t npcm_pcs_read_sr_ctl(NPCMPCSState *s, hwaddr offset)
+{
+ hwaddr regno = offset / sizeof(uint16_t);
+
+ if (regno >= NPCM_PCS_NR_SR_CTLS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: SR_CTL read offset 0x%04" HWADDR_PRIx
+ " is out of range.\n",
+ DEVICE(s)->canonical_path, offset);
+ return 0;
+ }
+
+ return s->sr_ctl[regno];
+}
+
+static uint16_t npcm_pcs_read_sr_mii(NPCMPCSState *s, hwaddr offset)
+{
+ hwaddr regno = offset / sizeof(uint16_t);
+
+ if (regno >= NPCM_PCS_NR_SR_MIIS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: SR_MII read offset 0x%04" HWADDR_PRIx
+ " is out of range.\n",
+ DEVICE(s)->canonical_path, offset);
+ return 0;
+ }
+
+ return s->sr_mii[regno];
+}
+
+static uint16_t npcm_pcs_read_sr_tim(NPCMPCSState *s, hwaddr offset)
+{
+ hwaddr regno = offset / sizeof(uint16_t);
+
+ if (regno >= NPCM_PCS_NR_SR_TIMS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: SR_TIM read offset 0x%04" HWADDR_PRIx
+ " is out of range.\n",
+ DEVICE(s)->canonical_path, offset);
+ return 0;
+ }
+
+ return s->sr_tim[regno];
+}
+
+static uint16_t npcm_pcs_read_vr_mii(NPCMPCSState *s, hwaddr offset)
+{
+ hwaddr regno = offset / sizeof(uint16_t);
+
+ if (regno >= NPCM_PCS_NR_VR_MIIS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: VR_MII read offset 0x%04" HWADDR_PRIx
+ " is out of range.\n",
+ DEVICE(s)->canonical_path, offset);
+ return 0;
+ }
+
+ return s->vr_mii[regno];
+}
+
+static void npcm_pcs_write_sr_ctl(NPCMPCSState *s, hwaddr offset, uint16_t v)
+{
+ hwaddr regno = offset / sizeof(uint16_t);
+
+ if (regno >= NPCM_PCS_NR_SR_CTLS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: SR_CTL write offset 0x%04" HWADDR_PRIx
+ " is out of range.\n",
+ DEVICE(s)->canonical_path, offset);
+ return;
+ }
+
+ s->sr_ctl[regno] = v;
+}
+
+static void npcm_pcs_write_sr_mii(NPCMPCSState *s, hwaddr offset, uint16_t v)
+{
+ hwaddr regno = offset / sizeof(uint16_t);
+
+ if (regno >= NPCM_PCS_NR_SR_MIIS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: SR_MII write offset 0x%04" HWADDR_PRIx
+ " is out of range.\n",
+ DEVICE(s)->canonical_path, offset);
+ return;
+ }
+
+ s->sr_mii[regno] = v;
+
+ if ((offset == A_NPCM_PCS_SR_MII_CTRL) && (v & NPCM_PCS_SR_MII_CTRL_RST)) {
+ /* Trigger a soft reset */
+ npcm_pcs_soft_reset(s);
+ }
+}
+
+static void npcm_pcs_write_sr_tim(NPCMPCSState *s, hwaddr offset, uint16_t v)
+{
+ hwaddr regno = offset / sizeof(uint16_t);
+
+ if (regno >= NPCM_PCS_NR_SR_TIMS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: SR_TIM write offset 0x%04" HWADDR_PRIx
+ " is out of range.\n",
+ DEVICE(s)->canonical_path, offset);
+ return;
+ }
+
+ s->sr_tim[regno] = v;
+}
+
+static void npcm_pcs_write_vr_mii(NPCMPCSState *s, hwaddr offset, uint16_t v)
+{
+ hwaddr regno = offset / sizeof(uint16_t);
+
+ if (regno >= NPCM_PCS_NR_VR_MIIS) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: VR_MII write offset 0x%04" HWADDR_PRIx
+ " is out of range.\n",
+ DEVICE(s)->canonical_path, offset);
+ return;
+ }
+
+ s->vr_mii[regno] = v;
+}
+
+static uint64_t npcm_pcs_read(void *opaque, hwaddr offset, unsigned size)
+{
+ NPCMPCSState *s = opaque;
+ uint16_t v = 0;
+
+ if (offset == NPCM_PCS_IND_AC_BA) {
+ v = s->indirect_access_base;
+ } else {
+ switch (s->indirect_access_base) {
+ case NPCM_PCS_IND_SR_CTL:
+ v = npcm_pcs_read_sr_ctl(s, offset);
+ break;
+
+ case NPCM_PCS_IND_SR_MII:
+ v = npcm_pcs_read_sr_mii(s, offset);
+ break;
+
+ case NPCM_PCS_IND_SR_TIM:
+ v = npcm_pcs_read_sr_tim(s, offset);
+ break;
+
+ case NPCM_PCS_IND_VR_MII:
+ v = npcm_pcs_read_vr_mii(s, offset);
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Read with invalid indirect address base: 0x%"
+ PRIx16 "\n", DEVICE(s)->canonical_path,
+ s->indirect_access_base);
+ }
+ }
+
+ trace_npcm_pcs_reg_read(DEVICE(s)->canonical_path, s->indirect_access_base,
+ offset, v);
+ return v;
+}
+
+static void npcm_pcs_write(void *opaque, hwaddr offset,
+ uint64_t v, unsigned size)
+{
+ NPCMPCSState *s = opaque;
+
+ trace_npcm_pcs_reg_write(DEVICE(s)->canonical_path, s->indirect_access_base,
+ offset, v);
+ if (offset == NPCM_PCS_IND_AC_BA) {
+ s->indirect_access_base = v;
+ } else {
+ switch (s->indirect_access_base) {
+ case NPCM_PCS_IND_SR_CTL:
+ npcm_pcs_write_sr_ctl(s, offset, v);
+ break;
+
+ case NPCM_PCS_IND_SR_MII:
+ npcm_pcs_write_sr_mii(s, offset, v);
+ break;
+
+ case NPCM_PCS_IND_SR_TIM:
+ npcm_pcs_write_sr_tim(s, offset, v);
+ break;
+
+ case NPCM_PCS_IND_VR_MII:
+ npcm_pcs_write_vr_mii(s, offset, v);
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Write with invalid indirect address base: 0x%02"
+ PRIx16 "\n", DEVICE(s)->canonical_path,
+ s->indirect_access_base);
+ }
+ }
+}
+
+static void npcm_pcs_enter_reset(Object *obj, ResetType type)
+{
+ NPCMPCSState *s = NPCM_PCS(obj);
+
+ npcm_pcs_soft_reset(s);
+}
+
+static const struct MemoryRegionOps npcm_pcs_ops = {
+ .read = npcm_pcs_read,
+ .write = npcm_pcs_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 2,
+ .max_access_size = 2,
+ .unaligned = false,
+ },
+};
+
+static void npcm_pcs_realize(DeviceState *dev, Error **errp)
+{
+ NPCMPCSState *pcs = NPCM_PCS(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init_io(&pcs->iomem, OBJECT(pcs), &npcm_pcs_ops, pcs,
+ TYPE_NPCM_PCS, 8 * KiB);
+ sysbus_init_mmio(sbd, &pcs->iomem);
+}
+
+static const VMStateDescription vmstate_npcm_pcs = {
+ .name = TYPE_NPCM_PCS,
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT16(indirect_access_base, NPCMPCSState),
+ VMSTATE_UINT16_ARRAY(sr_ctl, NPCMPCSState, NPCM_PCS_NR_SR_CTLS),
+ VMSTATE_UINT16_ARRAY(sr_mii, NPCMPCSState, NPCM_PCS_NR_SR_MIIS),
+ VMSTATE_UINT16_ARRAY(sr_tim, NPCMPCSState, NPCM_PCS_NR_SR_TIMS),
+ VMSTATE_UINT16_ARRAY(vr_mii, NPCMPCSState, NPCM_PCS_NR_VR_MIIS),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+static void npcm_pcs_class_init(ObjectClass *klass, void *data)
+{
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+ dc->desc = "NPCM PCS Controller";
+ dc->realize = npcm_pcs_realize;
+ dc->vmsd = &vmstate_npcm_pcs;
+ rc->phases.enter = npcm_pcs_enter_reset;
+}
+
+static const TypeInfo npcm_pcs_types[] = {
+ {
+ .name = TYPE_NPCM_PCS,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCMPCSState),
+ .class_init = npcm_pcs_class_init,
+ },
+};
+DEFINE_TYPES(npcm_pcs_types)
diff --git a/hw/net/meson.build b/hw/net/meson.build
index 3bb5d749a83..e6759e26ca6 100644
--- a/hw/net/meson.build
+++ b/hw/net/meson.build
@@ -40,6 +40,7 @@ system_ss.add(when: 'CONFIG_SUNHME', if_true: files('sunhme.c'))
system_ss.add(when: 'CONFIG_FTGMAC100', if_true: files('ftgmac100.c'))
system_ss.add(when: 'CONFIG_SUNGEM', if_true: files('sungem.c'))
system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_emc.c', 'npcm_gmac.c'))
+system_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm_pcs.c'))
system_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_fec.c'))
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_llan.c'))
diff --git a/hw/net/trace-events b/hw/net/trace-events
index c35bfb2eb8d..72b69c4a8bb 100644
--- a/hw/net/trace-events
+++ b/hw/net/trace-events
@@ -483,8 +483,8 @@ npcm_gmac_packet_tx_desc_data(const char* name, uint32_t tdes0, uint32_t tdes1)
npcm_gmac_tx_desc_owner(const char* name, uint32_t desc_addr) "%s: TX Descriptor @0x%04" PRIX32 " is owned by software"
# npcm_pcs.c
-npcm_pcs_reg_read(const char *name, uint16_t indirect_access_baes, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
-npcm_pcs_reg_write(const char *name, uint16_t indirect_access_baes, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
+npcm_pcs_reg_read(const char *name, uint16_t indirect_access_base, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
+npcm_pcs_reg_write(const char *name, uint16_t indirect_access_base, uint64_t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 " value: 0x%04" PRIx16
# dp8398x.c
dp8393x_raise_irq(int isr) "raise irq, isr is 0x%04x"
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 39/41] hw/arm: Add NPCM8XX SoC
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (37 preceding siblings ...)
2025-02-20 16:21 ` [PULL 38/41] hw/net: Add NPCM8XX PCS Module Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 40/41] hw/arm: Add NPCM845 Evaluation board Peter Maydell
` (2 subsequent siblings)
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250219184609.1839281-16-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
configs/devices/aarch64-softmmu/default.mak | 1 +
include/hw/arm/npcm8xx.h | 106 +++
hw/arm/npcm8xx.c | 805 ++++++++++++++++++++
hw/arm/Kconfig | 13 +
hw/arm/meson.build | 1 +
5 files changed, 926 insertions(+)
create mode 100644 include/hw/arm/npcm8xx.h
create mode 100644 hw/arm/npcm8xx.c
diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/aarch64-softmmu/default.mak
index f82a04c27d1..93f4022ad62 100644
--- a/configs/devices/aarch64-softmmu/default.mak
+++ b/configs/devices/aarch64-softmmu/default.mak
@@ -8,3 +8,4 @@ include ../arm-softmmu/default.mak
# CONFIG_XLNX_ZYNQMP_ARM=n
# CONFIG_XLNX_VERSAL=n
# CONFIG_SBSA_REF=n
+# CONFIG_NPCM8XX=n
diff --git a/include/hw/arm/npcm8xx.h b/include/hw/arm/npcm8xx.h
new file mode 100644
index 00000000000..a32fbb035b5
--- /dev/null
+++ b/include/hw/arm/npcm8xx.h
@@ -0,0 +1,106 @@
+/*
+ * Nuvoton NPCM8xx SoC family.
+ *
+ * Copyright 2022 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM8XX_H
+#define NPCM8XX_H
+
+#include "hw/adc/npcm7xx_adc.h"
+#include "hw/core/split-irq.h"
+#include "hw/cpu/cluster.h"
+#include "hw/gpio/npcm7xx_gpio.h"
+#include "hw/i2c/npcm7xx_smbus.h"
+#include "hw/intc/arm_gic_common.h"
+#include "hw/mem/npcm7xx_mc.h"
+#include "hw/misc/npcm_clk.h"
+#include "hw/misc/npcm_gcr.h"
+#include "hw/misc/npcm7xx_mft.h"
+#include "hw/misc/npcm7xx_pwm.h"
+#include "hw/misc/npcm7xx_rng.h"
+#include "hw/net/npcm7xx_emc.h"
+#include "hw/nvram/npcm7xx_otp.h"
+#include "hw/sd/npcm7xx_sdhci.h"
+#include "hw/timer/npcm7xx_timer.h"
+#include "hw/ssi/npcm7xx_fiu.h"
+#include "hw/usb/hcd-ehci.h"
+#include "hw/usb/hcd-ohci.h"
+#include "target/arm/cpu.h"
+
+#define NPCM8XX_MAX_NUM_CPUS (4)
+
+/* The first half of the address space is reserved for DDR4 DRAM. */
+#define NPCM8XX_DRAM_BA (0x00000000)
+#define NPCM8XX_DRAM_SZ (2 * GiB)
+
+/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
+#define NPCM8XX_LOADER_START (0x00000000) /* Start of SDRAM */
+#define NPCM8XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */
+#define NPCM8XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */
+#define NPCM8XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */
+
+#define NPCM8XX_NR_PWM_MODULES 3
+
+struct NPCM8xxState {
+ DeviceState parent_obj;
+
+ ARMCPU cpu[NPCM8XX_MAX_NUM_CPUS];
+ CPUClusterState cpu_cluster;
+ GICState gic;
+
+ MemoryRegion sram;
+ MemoryRegion irom;
+ MemoryRegion ram3;
+ MemoryRegion *dram;
+
+ NPCMGCRState gcr;
+ NPCMCLKState clk;
+ NPCM7xxTimerCtrlState tim[3];
+ NPCM7xxADCState adc;
+ NPCM7xxPWMState pwm[NPCM8XX_NR_PWM_MODULES];
+ NPCM7xxMFTState mft[8];
+ NPCM7xxOTPState fuse_array;
+ NPCM7xxMCState mc;
+ NPCM7xxRNGState rng;
+ NPCM7xxGPIOState gpio[8];
+ NPCM7xxSMBusState smbus[27];
+ EHCISysBusState ehci[2];
+ OHCISysBusState ohci[2];
+ NPCM7xxFIUState fiu[3];
+ NPCM7xxSDHCIState mmc;
+};
+
+struct NPCM8xxClass {
+ DeviceClass parent_class;
+
+ /* Bitmask of modules that are permanently disabled on this chip. */
+ uint32_t disabled_modules;
+ /* Number of CPU cores enabled in this SoC class. */
+ uint32_t num_cpus;
+};
+
+#define TYPE_NPCM8XX "npcm8xx"
+OBJECT_DECLARE_TYPE(NPCM8xxState, NPCM8xxClass, NPCM8XX)
+
+/**
+ * npcm8xx_load_kernel - Loads memory with everything needed to boot
+ * @machine - The machine containing the SoC to be booted.
+ * @soc - The SoC containing the CPU to be booted.
+ *
+ * This will set up the ARM boot info structure for the specific NPCM8xx
+ * derivative and call arm_load_kernel() to set up loading of the kernel, etc.
+ * into memory, if requested by the user.
+ */
+void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc);
+
+#endif /* NPCM8XX_H */
diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
new file mode 100644
index 00000000000..f182accc47c
--- /dev/null
+++ b/hw/arm/npcm8xx.c
@@ -0,0 +1,805 @@
+/*
+ * Nuvoton NPCM8xx SoC family.
+ *
+ * Copyright 2022 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/boards.h"
+#include "hw/arm/boot.h"
+#include "hw/arm/bsa.h"
+#include "hw/arm/npcm8xx.h"
+#include "hw/char/serial-mm.h"
+#include "hw/intc/arm_gic.h"
+#include "hw/loader.h"
+#include "hw/misc/unimp.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/units.h"
+#include "system/system.h"
+
+/*
+ * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
+ * that aren't handled by a device.
+ */
+#define NPCM8XX_MMIO_BA 0x80000000
+#define NPCM8XX_MMIO_SZ 0x7ffd0000
+
+/* OTP fuse array */
+#define NPCM8XX_OTP_BA 0xf0189000
+
+/* GIC Distributor */
+#define NPCM8XX_GICD_BA 0xdfff9000
+#define NPCM8XX_GICC_BA 0xdfffa000
+
+/* Core system modules. */
+#define NPCM8XX_CPUP_BA 0xf03fe000
+#define NPCM8XX_GCR_BA 0xf0800000
+#define NPCM8XX_CLK_BA 0xf0801000
+#define NPCM8XX_MC_BA 0xf0824000
+#define NPCM8XX_RNG_BA 0xf000b000
+
+/* ADC Module */
+#define NPCM8XX_ADC_BA 0xf000c000
+
+/* Internal AHB SRAM */
+#define NPCM8XX_RAM3_BA 0xc0008000
+#define NPCM8XX_RAM3_SZ (4 * KiB)
+
+/* Memory blocks at the end of the address space */
+#define NPCM8XX_RAM2_BA 0xfffb0000
+#define NPCM8XX_RAM2_SZ (256 * KiB)
+#define NPCM8XX_ROM_BA 0xffff0100
+#define NPCM8XX_ROM_SZ (64 * KiB)
+
+/* SDHCI Modules */
+#define NPCM8XX_MMC_BA 0xf0842000
+
+/* Run PLL1 at 1600 MHz */
+#define NPCM8XX_PLLCON1_FIXUP_VAL 0x00402101
+/* Run the CPU from PLL1 and UART from PLL2 */
+#define NPCM8XX_CLKSEL_FIXUP_VAL 0x004aaba9
+
+/* Clock configuration values to be fixed up when bypassing bootloader */
+
+/*
+ * Interrupt lines going into the GIC. This does not include internal Cortex-A35
+ * interrupts.
+ */
+enum NPCM8xxInterrupt {
+ NPCM8XX_ADC_IRQ = 0,
+ NPCM8XX_PECI_IRQ = 6,
+ NPCM8XX_KCS_HIB_IRQ = 9,
+ NPCM8XX_MMC_IRQ = 26,
+ NPCM8XX_TIMER0_IRQ = 32, /* Timer Module 0 */
+ NPCM8XX_TIMER1_IRQ,
+ NPCM8XX_TIMER2_IRQ,
+ NPCM8XX_TIMER3_IRQ,
+ NPCM8XX_TIMER4_IRQ,
+ NPCM8XX_TIMER5_IRQ, /* Timer Module 1 */
+ NPCM8XX_TIMER6_IRQ,
+ NPCM8XX_TIMER7_IRQ,
+ NPCM8XX_TIMER8_IRQ,
+ NPCM8XX_TIMER9_IRQ,
+ NPCM8XX_TIMER10_IRQ, /* Timer Module 2 */
+ NPCM8XX_TIMER11_IRQ,
+ NPCM8XX_TIMER12_IRQ,
+ NPCM8XX_TIMER13_IRQ,
+ NPCM8XX_TIMER14_IRQ,
+ NPCM8XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
+ NPCM8XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
+ NPCM8XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
+ NPCM8XX_EHCI1_IRQ = 61,
+ NPCM8XX_OHCI1_IRQ,
+ NPCM8XX_EHCI2_IRQ,
+ NPCM8XX_OHCI2_IRQ,
+ NPCM8XX_PWM0_IRQ = 93, /* PWM module 0 */
+ NPCM8XX_PWM1_IRQ, /* PWM module 1 */
+ NPCM8XX_MFT0_IRQ = 96, /* MFT module 0 */
+ NPCM8XX_MFT1_IRQ, /* MFT module 1 */
+ NPCM8XX_MFT2_IRQ, /* MFT module 2 */
+ NPCM8XX_MFT3_IRQ, /* MFT module 3 */
+ NPCM8XX_MFT4_IRQ, /* MFT module 4 */
+ NPCM8XX_MFT5_IRQ, /* MFT module 5 */
+ NPCM8XX_MFT6_IRQ, /* MFT module 6 */
+ NPCM8XX_MFT7_IRQ, /* MFT module 7 */
+ NPCM8XX_PCI_MBOX1_IRQ = 105,
+ NPCM8XX_PCI_MBOX2_IRQ,
+ NPCM8XX_GPIO0_IRQ = 116,
+ NPCM8XX_GPIO1_IRQ,
+ NPCM8XX_GPIO2_IRQ,
+ NPCM8XX_GPIO3_IRQ,
+ NPCM8XX_GPIO4_IRQ,
+ NPCM8XX_GPIO5_IRQ,
+ NPCM8XX_GPIO6_IRQ,
+ NPCM8XX_GPIO7_IRQ,
+ NPCM8XX_SMBUS0_IRQ = 128,
+ NPCM8XX_SMBUS1_IRQ,
+ NPCM8XX_SMBUS2_IRQ,
+ NPCM8XX_SMBUS3_IRQ,
+ NPCM8XX_SMBUS4_IRQ,
+ NPCM8XX_SMBUS5_IRQ,
+ NPCM8XX_SMBUS6_IRQ,
+ NPCM8XX_SMBUS7_IRQ,
+ NPCM8XX_SMBUS8_IRQ,
+ NPCM8XX_SMBUS9_IRQ,
+ NPCM8XX_SMBUS10_IRQ,
+ NPCM8XX_SMBUS11_IRQ,
+ NPCM8XX_SMBUS12_IRQ,
+ NPCM8XX_SMBUS13_IRQ,
+ NPCM8XX_SMBUS14_IRQ,
+ NPCM8XX_SMBUS15_IRQ,
+ NPCM8XX_SMBUS16_IRQ,
+ NPCM8XX_SMBUS17_IRQ,
+ NPCM8XX_SMBUS18_IRQ,
+ NPCM8XX_SMBUS19_IRQ,
+ NPCM8XX_SMBUS20_IRQ,
+ NPCM8XX_SMBUS21_IRQ,
+ NPCM8XX_SMBUS22_IRQ,
+ NPCM8XX_SMBUS23_IRQ,
+ NPCM8XX_SMBUS24_IRQ,
+ NPCM8XX_SMBUS25_IRQ,
+ NPCM8XX_SMBUS26_IRQ,
+ NPCM8XX_UART0_IRQ = 192,
+ NPCM8XX_UART1_IRQ,
+ NPCM8XX_UART2_IRQ,
+ NPCM8XX_UART3_IRQ,
+ NPCM8XX_UART4_IRQ,
+ NPCM8XX_UART5_IRQ,
+ NPCM8XX_UART6_IRQ,
+};
+
+/* Total number of GIC interrupts, including internal Cortex-A35 interrupts. */
+#define NPCM8XX_NUM_IRQ (288)
+#define NPCM8XX_PPI_BASE(cpu) \
+ ((NPCM8XX_NUM_IRQ - GIC_INTERNAL) + (cpu) * GIC_INTERNAL)
+
+/* Register base address for each Timer Module */
+static const hwaddr npcm8xx_tim_addr[] = {
+ 0xf0008000,
+ 0xf0009000,
+ 0xf000a000,
+};
+
+/* Register base address for each 16550 UART */
+static const hwaddr npcm8xx_uart_addr[] = {
+ 0xf0000000,
+ 0xf0001000,
+ 0xf0002000,
+ 0xf0003000,
+ 0xf0004000,
+ 0xf0005000,
+ 0xf0006000,
+};
+
+/* Direct memory-mapped access to SPI0 CS0-1. */
+static const hwaddr npcm8xx_fiu0_flash_addr[] = {
+ 0x80000000, /* CS0 */
+ 0x88000000, /* CS1 */
+};
+
+/* Direct memory-mapped access to SPI1 CS0-3. */
+static const hwaddr npcm8xx_fiu1_flash_addr[] = {
+ 0x90000000, /* CS0 */
+ 0x91000000, /* CS1 */
+ 0x92000000, /* CS2 */
+ 0x93000000, /* CS3 */
+};
+
+/* Direct memory-mapped access to SPI3 CS0-3. */
+static const hwaddr npcm8xx_fiu3_flash_addr[] = {
+ 0xa0000000, /* CS0 */
+ 0xa8000000, /* CS1 */
+ 0xb0000000, /* CS2 */
+ 0xb8000000, /* CS3 */
+};
+
+/* Register base address for each PWM Module */
+static const hwaddr npcm8xx_pwm_addr[] = {
+ 0xf0103000,
+ 0xf0104000,
+ 0xf0105000,
+};
+
+/* Register base address for each MFT Module */
+static const hwaddr npcm8xx_mft_addr[] = {
+ 0xf0180000,
+ 0xf0181000,
+ 0xf0182000,
+ 0xf0183000,
+ 0xf0184000,
+ 0xf0185000,
+ 0xf0186000,
+ 0xf0187000,
+};
+
+/* Direct memory-mapped access to each SMBus Module. */
+static const hwaddr npcm8xx_smbus_addr[] = {
+ 0xf0080000,
+ 0xf0081000,
+ 0xf0082000,
+ 0xf0083000,
+ 0xf0084000,
+ 0xf0085000,
+ 0xf0086000,
+ 0xf0087000,
+ 0xf0088000,
+ 0xf0089000,
+ 0xf008a000,
+ 0xf008b000,
+ 0xf008c000,
+ 0xf008d000,
+ 0xf008e000,
+ 0xf008f000,
+ 0xfff00000,
+ 0xfff01000,
+ 0xfff02000,
+ 0xfff03000,
+ 0xfff04000,
+ 0xfff05000,
+ 0xfff06000,
+ 0xfff07000,
+ 0xfff08000,
+ 0xfff09000,
+ 0xfff0a000,
+};
+
+/* Register base address for each USB host EHCI registers */
+static const hwaddr npcm8xx_ehci_addr[] = {
+ 0xf0828100,
+ 0xf082a100,
+};
+
+/* Register base address for each USB host OHCI registers */
+static const hwaddr npcm8xx_ohci_addr[] = {
+ 0xf0829000,
+ 0xf082b000,
+};
+
+static const struct {
+ hwaddr regs_addr;
+ uint32_t reset_pu;
+ uint32_t reset_pd;
+ uint32_t reset_osrc;
+ uint32_t reset_odsc;
+} npcm8xx_gpio[] = {
+ {
+ .regs_addr = 0xf0010000,
+ .reset_pu = 0x00000300,
+ .reset_pd = 0x000f0000,
+ }, {
+ .regs_addr = 0xf0011000,
+ .reset_pu = 0xe0fefe01,
+ .reset_pd = 0x07000000,
+ }, {
+ .regs_addr = 0xf0012000,
+ .reset_pu = 0xc00fffff,
+ .reset_pd = 0x3ff00000,
+ }, {
+ .regs_addr = 0xf0013000,
+ .reset_pd = 0x00003000,
+ }, {
+ .regs_addr = 0xf0014000,
+ .reset_pu = 0xffff0000,
+ }, {
+ .regs_addr = 0xf0015000,
+ .reset_pu = 0xff8387fe,
+ .reset_pd = 0x007c0001,
+ .reset_osrc = 0x08000000,
+ }, {
+ .regs_addr = 0xf0016000,
+ .reset_pu = 0x00000801,
+ .reset_pd = 0x00000302,
+ }, {
+ .regs_addr = 0xf0017000,
+ .reset_pu = 0x000002ff,
+ .reset_pd = 0x00000c00,
+ },
+};
+
+static const struct {
+ const char *name;
+ hwaddr regs_addr;
+ int cs_count;
+ const hwaddr *flash_addr;
+ size_t flash_size;
+} npcm8xx_fiu[] = {
+ {
+ .name = "fiu0",
+ .regs_addr = 0xfb000000,
+ .cs_count = ARRAY_SIZE(npcm8xx_fiu0_flash_addr),
+ .flash_addr = npcm8xx_fiu0_flash_addr,
+ .flash_size = 128 * MiB,
+ },
+ {
+ .name = "fiu1",
+ .regs_addr = 0xfb002000,
+ .cs_count = ARRAY_SIZE(npcm8xx_fiu1_flash_addr),
+ .flash_addr = npcm8xx_fiu1_flash_addr,
+ .flash_size = 16 * MiB,
+ }, {
+ .name = "fiu3",
+ .regs_addr = 0xc0000000,
+ .cs_count = ARRAY_SIZE(npcm8xx_fiu3_flash_addr),
+ .flash_addr = npcm8xx_fiu3_flash_addr,
+ .flash_size = 128 * MiB,
+ },
+};
+
+static struct arm_boot_info npcm8xx_binfo = {
+ .loader_start = NPCM8XX_LOADER_START,
+ .smp_loader_start = NPCM8XX_SMP_LOADER_START,
+ .smp_bootreg_addr = NPCM8XX_SMP_BOOTREG_ADDR,
+ .gic_cpu_if_addr = NPCM8XX_GICC_BA,
+ .secure_boot = false,
+ .board_id = -1,
+ .board_setup_addr = NPCM8XX_BOARD_SETUP_ADDR,
+};
+
+void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc)
+{
+ npcm8xx_binfo.ram_size = machine->ram_size;
+
+ arm_load_kernel(&soc->cpu[0], machine, &npcm8xx_binfo);
+}
+
+static void npcm8xx_init_fuses(NPCM8xxState *s)
+{
+ NPCM8xxClass *nc = NPCM8XX_GET_CLASS(s);
+ uint32_t value;
+
+ /*
+ * The initial mask of disabled modules indicates the chip derivative (e.g.
+ * NPCM750 or NPCM730).
+ */
+ value = cpu_to_le32(nc->disabled_modules);
+ npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
+ sizeof(value));
+}
+
+static void npcm8xx_write_adc_calibration(NPCM8xxState *s)
+{
+ /* Both ADC and the fuse array must have realized. */
+ QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
+ npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
+ NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
+}
+
+static qemu_irq npcm8xx_irq(NPCM8xxState *s, int n)
+{
+ return qdev_get_gpio_in(DEVICE(&s->gic), n);
+}
+
+static void npcm8xx_init(Object *obj)
+{
+ NPCM8xxState *s = NPCM8XX(obj);
+ int i;
+
+ object_initialize_child(obj, "cpu-cluster", &s->cpu_cluster,
+ TYPE_CPU_CLUSTER);
+ for (i = 0; i < NPCM8XX_MAX_NUM_CPUS; i++) {
+ object_initialize_child(OBJECT(&s->cpu_cluster), "cpu[*]", &s->cpu[i],
+ ARM_CPU_TYPE_NAME("cortex-a35"));
+ }
+ object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
+ object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM8XX_GCR);
+ object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
+ "power-on-straps");
+ object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM8XX_CLK);
+ object_initialize_child(obj, "otp", &s->fuse_array,
+ TYPE_NPCM7XX_FUSE_ARRAY);
+ object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
+ object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
+ object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
+
+ for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
+ object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
+ object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
+ }
+
+
+ for (i = 0; i < ARRAY_SIZE(s->smbus); i++) {
+ object_initialize_child(obj, "smbus[*]", &s->smbus[i],
+ TYPE_NPCM7XX_SMBUS);
+ DEVICE(&s->smbus[i])->id = g_strdup_printf("smbus[%d]", i);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->ehci); i++) {
+ object_initialize_child(obj, "ehci[*]", &s->ehci[i], TYPE_NPCM7XX_EHCI);
+ }
+ for (i = 0; i < ARRAY_SIZE(s->ohci); i++) {
+ object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI);
+ }
+
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) != ARRAY_SIZE(s->fiu));
+ for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
+ object_initialize_child(obj, npcm8xx_fiu[i].name, &s->fiu[i],
+ TYPE_NPCM7XX_FIU);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+ object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
+ object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT);
+ }
+
+ object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
+}
+
+static void npcm8xx_realize(DeviceState *dev, Error **errp)
+{
+ NPCM8xxState *s = NPCM8XX(dev);
+ NPCM8xxClass *nc = NPCM8XX_GET_CLASS(s);
+ int i;
+
+ if (memory_region_size(s->dram) > NPCM8XX_DRAM_SZ) {
+ error_setg(errp, "%s: NPCM8xx cannot address more than %" PRIu64
+ " MiB of DRAM", __func__, NPCM8XX_DRAM_SZ / MiB);
+ return;
+ }
+
+ /* CPUs */
+ for (i = 0; i < nc->num_cpus; i++) {
+ object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
+ arm_build_mp_affinity(i, NPCM8XX_MAX_NUM_CPUS),
+ &error_abort);
+ object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true,
+ &error_abort);
+ object_property_set_int(OBJECT(&s->cpu[i]), "core-count",
+ nc->num_cpus, &error_abort);
+
+ /* Disable security extensions. */
+ object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false,
+ &error_abort);
+
+ if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
+ return;
+ }
+ }
+
+ /* ARM GIC for Cortex A35. Can only fail if we pass bad parameters here. */
+ object_property_set_uint(OBJECT(&s->gic), "num-cpu", nc->num_cpus, errp);
+ object_property_set_uint(OBJECT(&s->gic), "num-irq", NPCM8XX_NUM_IRQ, errp);
+ object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp);
+ object_property_set_bool(OBJECT(&s->gic), "has-security-extensions", true,
+ errp);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
+ return;
+ }
+ for (i = 0; i < nc->num_cpus; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
+ qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus,
+ qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 2,
+ qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VIRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 3,
+ qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VFIQ));
+
+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_PHYS,
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ NPCM8XX_PPI_BASE(i) + ARCH_TIMER_NS_EL1_IRQ));
+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_VIRT,
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ NPCM8XX_PPI_BASE(i) + ARCH_TIMER_VIRT_IRQ));
+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_HYP,
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ NPCM8XX_PPI_BASE(i) + ARCH_TIMER_NS_EL2_IRQ));
+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_SEC,
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ NPCM8XX_PPI_BASE(i) + ARCH_TIMER_S_EL1_IRQ));
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, NPCM8XX_GICD_BA);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, NPCM8XX_GICC_BA);
+
+ /* CPU cluster */
+ qdev_prop_set_uint32(DEVICE(&s->cpu_cluster), "cluster-id", 0);
+ qdev_realize(DEVICE(&s->cpu_cluster), NULL, &error_fatal);
+
+ /* System Global Control Registers (GCR). Can fail due to user input. */
+ object_property_set_int(OBJECT(&s->gcr), "disabled-modules",
+ nc->disabled_modules, &error_abort);
+ object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram));
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM8XX_GCR_BA);
+
+ /* Clock Control Registers (CLK). Cannot fail. */
+ sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM8XX_CLK_BA);
+
+ /* OTP fuse strap array. Cannot fail. */
+ sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM8XX_OTP_BA);
+ npcm8xx_init_fuses(s);
+
+ /* Fake Memory Controller (MC). Cannot fail. */
+ sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM8XX_MC_BA);
+
+ /* ADC Modules. Cannot fail. */
+ qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
+ DEVICE(&s->clk), "adc-clock"));
+ sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM8XX_ADC_BA);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
+ npcm8xx_irq(s, NPCM8XX_ADC_IRQ));
+ npcm8xx_write_adc_calibration(s);
+
+ /* Timer Modules (TIM). Cannot fail. */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_tim_addr) != ARRAY_SIZE(s->tim));
+ for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
+ int first_irq;
+ int j;
+
+ /* Connect the timer clock. */
+ qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
+ DEVICE(&s->clk), "timer-clock"));
+
+ sysbus_realize(sbd, &error_abort);
+ sysbus_mmio_map(sbd, 0, npcm8xx_tim_addr[i]);
+
+ first_irq = NPCM8XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
+ for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
+ qemu_irq irq = npcm8xx_irq(s, first_irq + j);
+ sysbus_connect_irq(sbd, j, irq);
+ }
+
+ /* IRQ for watchdogs */
+ sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
+ npcm8xx_irq(s, NPCM8XX_WDG0_IRQ + i));
+ /* GPIO that connects clk module with watchdog */
+ qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
+ NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
+ qdev_get_gpio_in_named(DEVICE(&s->clk),
+ NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
+ }
+
+ /* UART0..6 (16550 compatible) */
+ for (i = 0; i < ARRAY_SIZE(npcm8xx_uart_addr); i++) {
+ serial_mm_init(get_system_memory(), npcm8xx_uart_addr[i], 2,
+ npcm8xx_irq(s, NPCM8XX_UART0_IRQ + i), 115200,
+ serial_hd(i), DEVICE_LITTLE_ENDIAN);
+ }
+
+ /* Random Number Generator. Cannot fail. */
+ sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM8XX_RNG_BA);
+
+ /* GPIO modules. Cannot fail. */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_gpio) != ARRAY_SIZE(s->gpio));
+ for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
+ Object *obj = OBJECT(&s->gpio[i]);
+
+ object_property_set_uint(obj, "reset-pullup",
+ npcm8xx_gpio[i].reset_pu, &error_abort);
+ object_property_set_uint(obj, "reset-pulldown",
+ npcm8xx_gpio[i].reset_pd, &error_abort);
+ object_property_set_uint(obj, "reset-osrc",
+ npcm8xx_gpio[i].reset_osrc, &error_abort);
+ object_property_set_uint(obj, "reset-odsc",
+ npcm8xx_gpio[i].reset_odsc, &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_gpio[i].regs_addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
+ npcm8xx_irq(s, NPCM8XX_GPIO0_IRQ + i));
+ }
+
+ /* SMBus modules. Cannot fail. */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_smbus_addr) != ARRAY_SIZE(s->smbus));
+ for (i = 0; i < ARRAY_SIZE(s->smbus); i++) {
+ Object *obj = OBJECT(&s->smbus[i]);
+
+ sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_smbus_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
+ npcm8xx_irq(s, NPCM8XX_SMBUS0_IRQ + i));
+ }
+
+ /* USB Host */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->ohci) != ARRAY_SIZE(s->ehci));
+ for (i = 0; i < ARRAY_SIZE(s->ehci); i++) {
+ object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true,
+ &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, npcm8xx_ehci_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ npcm8xx_irq(s, NPCM8XX_EHCI1_IRQ + 2 * i));
+ }
+ for (i = 0; i < ARRAY_SIZE(s->ohci); i++) {
+ object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", "usb-bus.0",
+ &error_abort);
+ object_property_set_uint(OBJECT(&s->ohci[i]), "num-ports", 1,
+ &error_abort);
+ object_property_set_uint(OBJECT(&s->ohci[i]), "firstport", i,
+ &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, npcm8xx_ohci_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
+ npcm8xx_irq(s, NPCM8XX_OHCI1_IRQ + 2 * i));
+ }
+
+ /* PWM Modules. Cannot fail. */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_pwm_addr) != ARRAY_SIZE(s->pwm));
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
+
+ qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
+ DEVICE(&s->clk), "apb3-clock"));
+ sysbus_realize(sbd, &error_abort);
+ sysbus_mmio_map(sbd, 0, npcm8xx_pwm_addr[i]);
+ sysbus_connect_irq(sbd, i, npcm8xx_irq(s, NPCM8XX_PWM0_IRQ + i));
+ }
+
+ /* MFT Modules. Cannot fail. */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_mft_addr) != ARRAY_SIZE(s->mft));
+ for (i = 0; i < ARRAY_SIZE(s->mft); i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]);
+
+ qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in",
+ qdev_get_clock_out(DEVICE(&s->clk),
+ "apb4-clock"));
+ sysbus_realize(sbd, &error_abort);
+ sysbus_mmio_map(sbd, 0, npcm8xx_mft_addr[i]);
+ sysbus_connect_irq(sbd, 0, npcm8xx_irq(s, NPCM8XX_MFT0_IRQ + i));
+ }
+
+ /*
+ * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
+ * specified, but this is a programming error.
+ */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) != ARRAY_SIZE(s->fiu));
+ for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
+ int j;
+
+ object_property_set_int(OBJECT(sbd), "cs-count",
+ npcm8xx_fiu[i].cs_count, &error_abort);
+ object_property_set_int(OBJECT(sbd), "flash-size",
+ npcm8xx_fiu[i].flash_size, &error_abort);
+ sysbus_realize(sbd, &error_abort);
+
+ sysbus_mmio_map(sbd, 0, npcm8xx_fiu[i].regs_addr);
+ for (j = 0; j < npcm8xx_fiu[i].cs_count; j++) {
+ sysbus_mmio_map(sbd, j + 1, npcm8xx_fiu[i].flash_addr[j]);
+ }
+ }
+
+ /* RAM2 (SRAM) */
+ memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
+ NPCM8XX_RAM2_SZ, &error_abort);
+ memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM2_BA, &s->sram);
+
+ /* RAM3 (SRAM) */
+ memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
+ NPCM8XX_RAM3_SZ, &error_abort);
+ memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM3_BA, &s->ram3);
+
+ /* Internal ROM */
+ memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM8XX_ROM_SZ,
+ &error_abort);
+ memory_region_add_subregion(get_system_memory(), NPCM8XX_ROM_BA, &s->irom);
+
+ /* SDHCI */
+ sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM8XX_MMC_BA);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
+ npcm8xx_irq(s, NPCM8XX_MMC_IRQ));
+
+
+ create_unimplemented_device("npcm8xx.shm", 0xc0001000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.gicextra", 0xdfffa000, 24 * KiB);
+ create_unimplemented_device("npcm8xx.vdmx", 0xe0800000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.pcierc", 0xe1000000, 64 * KiB);
+ create_unimplemented_device("npcm8xx.rootc", 0xe8000000, 128 * MiB);
+ create_unimplemented_device("npcm8xx.kcs", 0xf0007000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.gfxi", 0xf000e000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.fsw", 0xf000f000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.bt", 0xf0030000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.espi", 0xf009f000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.peci", 0xf0100000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.siox[1]", 0xf0101000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.siox[2]", 0xf0102000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.tmps", 0xf0188000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.pspi", 0xf0201000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.viru1", 0xf0204000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.viru2", 0xf0205000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.jtm1", 0xf0208000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.jtm2", 0xf0209000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.flm0", 0xf0210000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.flm1", 0xf0211000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.flm2", 0xf0212000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.flm3", 0xf0213000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.ahbpci", 0xf0400000, 1 * MiB);
+ create_unimplemented_device("npcm8xx.dap", 0xf0500000, 960 * KiB);
+ create_unimplemented_device("npcm8xx.mcphy", 0xf05f0000, 64 * KiB);
+ create_unimplemented_device("npcm8xx.pcs", 0xf0780000, 256 * KiB);
+ create_unimplemented_device("npcm8xx.tsgen", 0xf07fc000, 8 * KiB);
+ create_unimplemented_device("npcm8xx.gmac1", 0xf0802000, 8 * KiB);
+ create_unimplemented_device("npcm8xx.gmac2", 0xf0804000, 8 * KiB);
+ create_unimplemented_device("npcm8xx.gmac3", 0xf0806000, 8 * KiB);
+ create_unimplemented_device("npcm8xx.gmac4", 0xf0808000, 8 * KiB);
+ create_unimplemented_device("npcm8xx.copctl", 0xf080c000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.tipctl", 0xf080d000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.rst", 0xf080e000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.vcd", 0xf0810000, 64 * KiB);
+ create_unimplemented_device("npcm8xx.ece", 0xf0820000, 8 * KiB);
+ create_unimplemented_device("npcm8xx.vdma", 0xf0822000, 8 * KiB);
+ create_unimplemented_device("npcm8xx.usbd[0]", 0xf0830000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.usbd[1]", 0xf0831000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.usbd[2]", 0xf0832000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.usbd[3]", 0xf0833000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.usbd[4]", 0xf0834000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.usbd[5]", 0xf0835000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.usbd[6]", 0xf0836000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.usbd[7]", 0xf0837000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.usbd[8]", 0xf0838000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.usbd[9]", 0xf0839000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.pci_mbox1", 0xf0848000, 64 * KiB);
+ create_unimplemented_device("npcm8xx.gdma0", 0xf0850000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.gdma1", 0xf0851000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.gdma2", 0xf0852000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.aes", 0xf0858000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.des", 0xf0859000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.sha", 0xf085a000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.pci_mbox2", 0xf0868000, 64 * KiB);
+ create_unimplemented_device("npcm8xx.i3c0", 0xfff10000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.i3c1", 0xfff11000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.i3c2", 0xfff12000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.i3c3", 0xfff13000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.i3c4", 0xfff14000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.i3c5", 0xfff15000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.spixcs0", 0xf8000000, 16 * MiB);
+ create_unimplemented_device("npcm8xx.spixcs1", 0xf9000000, 16 * MiB);
+ create_unimplemented_device("npcm8xx.spix", 0xfb001000, 4 * KiB);
+ create_unimplemented_device("npcm8xx.vect", 0xffff0000, 256);
+}
+
+static const Property npcm8xx_properties[] = {
+ DEFINE_PROP_LINK("dram-mr", NPCM8xxState, dram, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+};
+
+static void npcm8xx_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ NPCM8xxClass *nc = NPCM8XX_CLASS(oc);
+
+ dc->realize = npcm8xx_realize;
+ dc->user_creatable = false;
+ nc->disabled_modules = 0x00000000;
+ nc->num_cpus = NPCM8XX_MAX_NUM_CPUS;
+ device_class_set_props(dc, npcm8xx_properties);
+}
+
+static const TypeInfo npcm8xx_soc_types[] = {
+ {
+ .name = TYPE_NPCM8XX,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(NPCM8xxState),
+ .instance_init = npcm8xx_init,
+ .class_size = sizeof(NPCM8xxClass),
+ .class_init = npcm8xx_class_init,
+ },
+};
+
+DEFINE_TYPES(npcm8xx_soc_types);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 7eab3914d4b..504841ccab4 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -481,6 +481,19 @@ config NPCM7XX
select PCA954X
select USB_OHCI_SYSBUS
+config NPCM8XX
+ bool
+ default y
+ depends on TCG && AARCH64
+ select ARM_GIC
+ select SMBUS
+ select PL310 # cache controller
+ select NPCM7XX
+ select SERIAL
+ select SSI
+ select UNIMP
+
+
config FSL_IMX25
bool
default y
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 490234b3b84..d7813c089c5 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -12,6 +12,7 @@ arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
+arm_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c'))
arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 40/41] hw/arm: Add NPCM845 Evaluation board
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (38 preceding siblings ...)
2025-02-20 16:21 ` [PULL 39/41] hw/arm: Add NPCM8XX SoC Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-20 16:21 ` [PULL 41/41] docs/system/arm: Add Description for NPCM8XX SoC Peter Maydell
2025-02-21 21:02 ` [PULL 00/41] target-arm queue Stefan Hajnoczi
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-17-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/npcm8xx.h | 21 ++++
hw/arm/npcm8xx_boards.c | 253 +++++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 2 +-
3 files changed, 275 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm8xx_boards.c
diff --git a/include/hw/arm/npcm8xx.h b/include/hw/arm/npcm8xx.h
index a32fbb035b5..9812e6fa7ec 100644
--- a/include/hw/arm/npcm8xx.h
+++ b/include/hw/arm/npcm8xx.h
@@ -51,6 +51,27 @@
#define NPCM8XX_NR_PWM_MODULES 3
+struct NPCM8xxMachine {
+ MachineState parent_obj;
+
+ /*
+ * PWM fan splitter. each splitter connects to one PWM output and
+ * multiple MFT inputs.
+ */
+ SplitIRQ fan_splitter[NPCM8XX_NR_PWM_MODULES *
+ NPCM7XX_PWM_PER_MODULE];
+};
+
+
+struct NPCM8xxMachineClass {
+ MachineClass parent_class;
+
+ const char *soc_type;
+};
+
+#define TYPE_NPCM8XX_MACHINE MACHINE_TYPE_NAME("npcm8xx")
+OBJECT_DECLARE_TYPE(NPCM8xxMachine, NPCM8xxMachineClass, NPCM8XX_MACHINE)
+
struct NPCM8xxState {
DeviceState parent_obj;
diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
new file mode 100644
index 00000000000..19610483f93
--- /dev/null
+++ b/hw/arm/npcm8xx_boards.c
@@ -0,0 +1,253 @@
+/*
+ * Machine definitions for boards featuring an NPCM8xx SoC.
+ *
+ * Copyright 2021 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "chardev/char.h"
+#include "hw/arm/npcm8xx.h"
+#include "hw/core/cpu.h"
+#include "hw/loader.h"
+#include "hw/qdev-core.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/datadir.h"
+#include "qemu/units.h"
+
+#define NPCM845_EVB_POWER_ON_STRAPS 0x000017ff
+
+static const char npcm8xx_default_bootrom[] = "npcm8xx_bootrom.bin";
+
+static void npcm8xx_load_bootrom(MachineState *machine, NPCM8xxState *soc)
+{
+ const char *bios_name = machine->firmware ?: npcm8xx_default_bootrom;
+ g_autofree char *filename = NULL;
+ int ret;
+
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (!filename) {
+ error_report("Could not find ROM image '%s'", bios_name);
+ if (!machine->kernel_filename) {
+ /* We can't boot without a bootrom or a kernel image. */
+ exit(1);
+ }
+ return;
+ }
+ ret = load_image_mr(filename, machine->ram);
+ if (ret < 0) {
+ error_report("Failed to load ROM image '%s'", filename);
+ exit(1);
+ }
+}
+
+static void npcm8xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
+ const char *flash_type, DriveInfo *dinfo)
+{
+ DeviceState *flash;
+ qemu_irq flash_cs;
+
+ flash = qdev_new(flash_type);
+ if (dinfo) {
+ qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
+ }
+ qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
+
+ flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
+ qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
+}
+
+static void npcm8xx_connect_dram(NPCM8xxState *soc, MemoryRegion *dram)
+{
+ memory_region_add_subregion(get_system_memory(), NPCM8XX_DRAM_BA, dram);
+
+ object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
+ &error_abort);
+}
+
+static NPCM8xxState *npcm8xx_create_soc(MachineState *machine,
+ uint32_t hw_straps)
+{
+ NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_GET_CLASS(machine);
+ Object *obj;
+
+ obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
+ &error_abort, NULL);
+ object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
+
+ return NPCM8XX(obj);
+}
+
+static I2CBus *npcm8xx_i2c_get_bus(NPCM8xxState *soc, uint32_t num)
+{
+ g_assert(num < ARRAY_SIZE(soc->smbus));
+ return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
+}
+
+static void npcm8xx_init_pwm_splitter(NPCM8xxMachine *machine,
+ NPCM8xxState *soc, const int *fan_counts)
+{
+ SplitIRQ *splitters = machine->fan_splitter;
+
+ /*
+ * PWM 0~3 belong to module 0 output 0~3.
+ * PWM 4~7 belong to module 1 output 0~3.
+ */
+ for (int i = 0; i < NPCM8XX_NR_PWM_MODULES; ++i) {
+ for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) {
+ int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j;
+ DeviceState *splitter;
+
+ if (fan_counts[splitter_no] < 1) {
+ continue;
+ }
+ object_initialize_child(OBJECT(machine), "fan-splitter[*]",
+ &splitters[splitter_no], TYPE_SPLIT_IRQ);
+ splitter = DEVICE(&splitters[splitter_no]);
+ qdev_prop_set_uint16(splitter, "num-lines",
+ fan_counts[splitter_no]);
+ qdev_realize(splitter, NULL, &error_abort);
+ qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out",
+ j, qdev_get_gpio_in(splitter, 0));
+ }
+ }
+}
+
+static void npcm8xx_connect_pwm_fan(NPCM8xxState *soc, SplitIRQ *splitter,
+ int fan_no, int output_no)
+{
+ DeviceState *fan;
+ int fan_input;
+ qemu_irq fan_duty_gpio;
+
+ g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT);
+ /*
+ * Fan 0~1 belong to module 0 input 0~1.
+ * Fan 2~3 belong to module 1 input 0~1.
+ * ...
+ * Fan 14~15 belong to module 7 input 0~1.
+ * Fan 16~17 belong to module 0 input 2~3.
+ * Fan 18~19 belong to module 1 input 2~3.
+ */
+ if (fan_no < 16) {
+ fan = DEVICE(&soc->mft[fan_no / 2]);
+ fan_input = fan_no % 2;
+ } else {
+ fan = DEVICE(&soc->mft[(fan_no - 16) / 2]);
+ fan_input = fan_no % 2 + 2;
+ }
+
+ /* Connect the Fan to PWM module */
+ fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input);
+ qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio);
+}
+
+static void npcm845_evb_i2c_init(NPCM8xxState *soc)
+{
+ /* tmp100 temperature sensor on SVB, tmp105 is compatible */
+ i2c_slave_create_simple(npcm8xx_i2c_get_bus(soc, 6), "tmp105", 0x48);
+}
+
+static void npcm845_evb_fan_init(NPCM8xxMachine *machine, NPCM8xxState *soc)
+{
+ SplitIRQ *splitter = machine->fan_splitter;
+ static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0};
+
+ npcm8xx_init_pwm_splitter(machine, soc, fan_counts);
+ npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
+ npcm8xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
+ npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
+ npcm8xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
+ npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
+ npcm8xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
+ npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0);
+ npcm8xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1);
+ npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0);
+ npcm8xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1);
+ npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0);
+ npcm8xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1);
+ npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0);
+ npcm8xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1);
+ npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0);
+ npcm8xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1);
+}
+
+static void npcm845_evb_init(MachineState *machine)
+{
+ NPCM8xxState *soc;
+
+ soc = npcm8xx_create_soc(machine, NPCM845_EVB_POWER_ON_STRAPS);
+ npcm8xx_connect_dram(soc, machine->ram);
+ qdev_realize(DEVICE(soc), NULL, &error_fatal);
+
+ npcm8xx_load_bootrom(machine, soc);
+ npcm8xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
+ npcm845_evb_i2c_init(soc);
+ npcm845_evb_fan_init(NPCM8XX_MACHINE(machine), soc);
+ npcm8xx_load_kernel(machine, soc);
+}
+
+static void npcm8xx_set_soc_type(NPCM8xxMachineClass *nmc, const char *type)
+{
+ NPCM8xxClass *sc = NPCM8XX_CLASS(object_class_by_name(type));
+ MachineClass *mc = MACHINE_CLASS(nmc);
+
+ nmc->soc_type = type;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
+}
+
+static void npcm8xx_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a9"),
+ NULL
+ };
+
+ mc->no_floppy = 1;
+ mc->no_cdrom = 1;
+ mc->no_parallel = 1;
+ mc->default_ram_id = "ram";
+ mc->valid_cpu_types = valid_cpu_types;
+}
+
+static void npcm845_evb_machine_class_init(ObjectClass *oc, void *data)
+{
+ NPCM8xxMachineClass *nmc = NPCM8XX_MACHINE_CLASS(oc);
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ npcm8xx_set_soc_type(nmc, TYPE_NPCM8XX);
+
+ mc->desc = "Nuvoton NPCM845 Evaluation Board (Cortex-A35)";
+ mc->init = npcm845_evb_init;
+ mc->default_ram_size = 1 * GiB;
+};
+
+static const TypeInfo npcm8xx_machine_types[] = {
+ {
+ .name = TYPE_NPCM8XX_MACHINE,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(NPCM8xxMachine),
+ .class_size = sizeof(NPCM8xxMachineClass),
+ .class_init = npcm8xx_machine_class_init,
+ .abstract = true,
+ }, {
+ .name = MACHINE_TYPE_NAME("npcm845-evb"),
+ .parent = TYPE_NPCM8XX_MACHINE,
+ .class_init = npcm845_evb_machine_class_init,
+ },
+};
+
+DEFINE_TYPES(npcm8xx_machine_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index d7813c089c5..465c757f976 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -12,7 +12,7 @@ arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
-arm_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c'))
+arm_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c', 'npcm8xx_boards.c'))
arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* [PULL 41/41] docs/system/arm: Add Description for NPCM8XX SoC
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (39 preceding siblings ...)
2025-02-20 16:21 ` [PULL 40/41] hw/arm: Add NPCM845 Evaluation board Peter Maydell
@ 2025-02-20 16:21 ` Peter Maydell
2025-02-21 21:02 ` [PULL 00/41] target-arm queue Stefan Hajnoczi
41 siblings, 0 replies; 55+ messages in thread
From: Peter Maydell @ 2025-02-20 16:21 UTC (permalink / raw)
To: qemu-devel
From: Hao Wu <wuhaotsh@google.com>
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
This document describes the NPCM8XX SoC and an evaluation board
(NPCM 845 EVB).
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250219184609.1839281-18-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/nuvoton.rst | 27 ++++++++++++++++++++-------
hw/arm/npcm8xx_boards.c | 1 +
2 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index 05059378e55..e4827fb43a1 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -1,12 +1,13 @@
-Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj``)
-=====================================================================================================
+Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj``, ``npcm845-evb``)
+======================================================================================================================
-The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
+The `Nuvoton iBMC`_ chips are a family of Arm-based SoCs that are
designed to be used as Baseboard Management Controllers (BMCs) in various
-servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an
-assortment of peripherals targeted for either Enterprise or Data Center /
-Hyperscale applications. The former is a superset of the latter, so NPCM750 has
-all the peripherals of NPCM730 and more.
+servers. Currently there are two families: NPCM7XX series and
+NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
+while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
+different assortment of peripherals targeted for either Enterprise or Data
+Center / Hyperscale applications.
.. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
@@ -27,6 +28,11 @@ There are also two more SoCs, NPCM710 and NPCM705, which are single-core
variants of NPCM750 and NPCM730, respectively. These are currently not
supported by QEMU.
+The NPCM8xx SoC is the successor of the NPCM7xx SoC. It has 4 Cortex-A35 cores.
+The following machines are based on this chip :
+
+- ``npcm845-evb`` Nuvoton NPCM845 Evaluation board
+
Supported devices
-----------------
@@ -62,6 +68,8 @@ Missing devices
* System Wake-up Control (SWC)
* Shared memory (SHM)
* eSPI slave interface
+ * Block-transfer interface (8XX only)
+ * Virtual UART (8XX only)
* Ethernet controller (GMAC)
* USB device (USBD)
@@ -76,6 +84,11 @@ Missing devices
* Video capture
* Encoding compression engine
* Security features
+ * I3C buses (8XX only)
+ * Temperature sensor interface (8XX only)
+ * Virtual UART (8XX only)
+ * Flash monitor (8XX only)
+ * JTAG master (8XX only)
Boot options
------------
diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
index 19610483f93..3fb8478e72e 100644
--- a/hw/arm/npcm8xx_boards.c
+++ b/hw/arm/npcm8xx_boards.c
@@ -17,6 +17,7 @@
#include "qemu/osdep.h"
#include "chardev/char.h"
+#include "hw/boards.h"
#include "hw/arm/npcm8xx.h"
#include "hw/core/cpu.h"
#include "hw/loader.h"
--
2.43.0
^ permalink raw reply related [flat|nested] 55+ messages in thread
* Re: [PULL 00/41] target-arm queue
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
` (40 preceding siblings ...)
2025-02-20 16:21 ` [PULL 41/41] docs/system/arm: Add Description for NPCM8XX SoC Peter Maydell
@ 2025-02-21 21:02 ` Stefan Hajnoczi
41 siblings, 0 replies; 55+ messages in thread
From: Stefan Hajnoczi @ 2025-02-21 21:02 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 116 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 484 bytes --]
^ permalink raw reply [flat|nested] 55+ messages in thread
end of thread, other threads:[~2025-02-21 23:34 UTC | newest]
Thread overview: 55+ messages (download: mbox.gz follow: Atom feed
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2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
2025-02-20 16:20 ` [PULL 01/41] target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1 Peter Maydell
2025-02-20 16:20 ` [PULL 02/41] target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS Peter Maydell
2025-02-20 16:20 ` [PULL 03/41] target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3 Peter Maydell
2025-02-20 16:20 ` [PULL 04/41] target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0 Peter Maydell
2025-02-20 16:20 ` [PULL 05/41] target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps Peter Maydell
2025-02-20 16:20 ` [PULL 06/41] hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3 Peter Maydell
2025-02-20 16:20 ` [PULL 07/41] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes Peter Maydell
2025-02-20 16:20 ` [PULL 08/41] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64() Peter Maydell
2025-02-20 16:20 ` [PULL 09/41] target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult Peter Maydell
2025-02-20 16:20 ` [PULL 10/41] target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1 Peter Maydell
2025-02-20 16:20 ` [PULL 11/41] target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps Peter Maydell
2025-02-20 16:20 ` [PULL 12/41] target/arm: Remove CP_ACCESS_TRAP handling Peter Maydell
2025-02-20 16:20 ` [PULL 13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED Peter Maydell
2025-02-20 16:20 ` [PULL 14/41] target/arm: Correct errors in WFI/WFE trapping Peter Maydell
2025-02-20 16:20 ` [PULL 15/41] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Peter Maydell
2025-02-20 16:20 ` [PULL 16/41] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs Peter Maydell
2025-02-20 16:20 ` [PULL 17/41] hw/arm/realview: " Peter Maydell
2025-02-20 16:20 ` [PULL 18/41] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Peter Maydell
2025-02-20 16:21 ` [PULL 19/41] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs Peter Maydell
2025-02-20 16:21 ` [PULL 20/41] hw/arm/vexpress: " Peter Maydell
2025-02-20 16:21 ` [PULL 21/41] hw/arm/highbank: Specify explicitly the GIC has 128 " Peter Maydell
2025-02-20 16:21 ` [PULL 22/41] hw/cpu/arm_mpcore: Remove default values for GIC " Peter Maydell
2025-02-20 16:21 ` [PULL 23/41] Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX Peter Maydell
2025-02-20 16:21 ` [PULL 24/41] target/arm: Use uint32_t in t32_expandimm_imm() Peter Maydell
2025-02-20 16:21 ` [PULL 25/41] roms: Update vbootrom to 1287b6e Peter Maydell
2025-02-20 16:21 ` [PULL 26/41] pc-bios: Add NPCM8XX vBootrom Peter Maydell
2025-02-20 16:21 ` [PULL 27/41] hw/ssi: Make flash size a property in NPCM7XX FIU Peter Maydell
2025-02-20 16:21 ` [PULL 28/41] hw/misc: Rename npcm7xx_gcr to npcm_gcr Peter Maydell
2025-02-20 16:21 ` [PULL 29/41] hw/misc: Move NPCM7XX GCR to NPCM GCR Peter Maydell
2025-02-20 16:21 ` [PULL 30/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
2025-02-20 16:21 ` [PULL 31/41] hw/misc: Add support for NPCM8XX GCR Peter Maydell
2025-02-20 16:21 ` [PULL 32/41] hw/misc: Store DRAM size in NPCM8XX GCR Module Peter Maydell
2025-02-20 16:21 ` [PULL 33/41] hw/misc: Support 8-bytes memop in NPCM GCR module Peter Maydell
2025-02-20 16:21 ` [PULL 34/41] hw/misc: Rename npcm7xx_clk to npcm_clk Peter Maydell
2025-02-20 16:21 ` [PULL 35/41] hw/misc: Move NPCM7XX CLK to NPCM CLK Peter Maydell
2025-02-20 16:21 ` [PULL 36/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
2025-02-20 16:21 ` [PULL 37/41] hw/misc: Support NPCM8XX CLK Module Registers Peter Maydell
2025-02-20 16:21 ` [PULL 38/41] hw/net: Add NPCM8XX PCS Module Peter Maydell
2025-02-20 16:21 ` [PULL 39/41] hw/arm: Add NPCM8XX SoC Peter Maydell
2025-02-20 16:21 ` [PULL 40/41] hw/arm: Add NPCM845 Evaluation board Peter Maydell
2025-02-20 16:21 ` [PULL 41/41] docs/system/arm: Add Description for NPCM8XX SoC Peter Maydell
2025-02-21 21:02 ` [PULL 00/41] target-arm queue Stefan Hajnoczi
-- strict thread matches above, loose matches on Subject: below --
2024-01-11 11:04 Peter Maydell
2024-01-11 15:16 ` Peter Maydell
2023-10-27 14:39 Peter Maydell
2023-10-29 23:15 ` Stefan Hajnoczi
2023-10-30 10:09 ` Peter Maydell
2023-10-30 22:09 ` Stefan Hajnoczi
2023-11-02 11:08 ` Peter Maydell
2023-10-31 7:51 ` Stefan Hajnoczi
2020-10-20 15:56 Peter Maydell
2020-10-20 16:36 ` Philippe Mathieu-Daudé
2020-10-20 16:36 ` no-reply
2019-10-22 13:30 Peter Maydell
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