qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/41] target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult
Date: Thu, 20 Feb 2025 16:20:50 +0000	[thread overview]
Message-ID: <20250220162123.626941-10-peter.maydell@linaro.org> (raw)
In-Reply-To: <20250220162123.626941-1-peter.maydell@linaro.org>

In the CPAccessResult enum, the CP_ACCESS_TRAP* values indicate the
equivalent of the pseudocode AArch64.SystemAccessTrap(..., 0x18),
causing a trap to a specified exception level with a syndrome value
giving information about the failing instructions.  In the
pseudocode, such traps are always taken to a specified target EL.  We
support that for target EL of 2 or 3 via CP_ACCESS_TRAP_EL2 and
CP_ACCESS_TRAP_EL3, but the only way to take the access trap to EL1
currently is to use CP_ACCESS_TRAP, which takes the trap to the
"usual target EL" (EL1 if in EL0, otherwise to the current EL).

Add CP_ACCESS_TRAP_EL1 so that access functions can follow the
pseudocode more closely.

(Note that for the common case in the pseudocode of "trap to
EL2 if HCR_EL2.TGE is set, otherwise trap to EL1", we handle
this in raise_exception(), so access functions don't need to
special case it and can use CP_ACCESS_TRAP_EL1.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-10-peter.maydell@linaro.org
---
 target/arm/cpregs.h        | 1 +
 target/arm/tcg/op_helper.c | 6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 1759d9defbe..fbf5798069d 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -331,6 +331,7 @@ typedef enum CPAccessResult {
      * 0xc or 0x18).
      */
     CP_ACCESS_TRAP = (1 << 2),
+    CP_ACCESS_TRAP_EL1 = CP_ACCESS_TRAP | 1,
     CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
     CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
 
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 1ba727e8e9f..c427118655d 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -781,7 +781,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
      * the other trap takes priority. So we take the "check HSTR_EL2" path
      * for all of those cases.)
      */
-    if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) == 0) &&
+    if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) < 2) &&
         arm_current_el(env) == 0) {
         goto fail;
     }
@@ -887,6 +887,9 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
     case 0:
         target_el = exception_target_el(env);
         break;
+    case 1:
+        assert(arm_current_el(env) < 2);
+        break;
     case 2:
         assert(arm_current_el(env) != 3);
         assert(arm_is_el2_enabled(env));
@@ -895,7 +898,6 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
         assert(arm_feature(env, ARM_FEATURE_EL3));
         break;
     default:
-        /* No "direct" traps to EL1 */
         g_assert_not_reached();
     }
 
-- 
2.43.0



  parent reply	other threads:[~2025-02-20 16:25 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
2025-02-20 16:20 ` [PULL 01/41] target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1 Peter Maydell
2025-02-20 16:20 ` [PULL 02/41] target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS Peter Maydell
2025-02-20 16:20 ` [PULL 03/41] target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3 Peter Maydell
2025-02-20 16:20 ` [PULL 04/41] target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0 Peter Maydell
2025-02-20 16:20 ` [PULL 05/41] target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps Peter Maydell
2025-02-20 16:20 ` [PULL 06/41] hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3 Peter Maydell
2025-02-20 16:20 ` [PULL 07/41] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes Peter Maydell
2025-02-20 16:20 ` [PULL 08/41] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64() Peter Maydell
2025-02-20 16:20 ` Peter Maydell [this message]
2025-02-20 16:20 ` [PULL 10/41] target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1 Peter Maydell
2025-02-20 16:20 ` [PULL 11/41] target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps Peter Maydell
2025-02-20 16:20 ` [PULL 12/41] target/arm: Remove CP_ACCESS_TRAP handling Peter Maydell
2025-02-20 16:20 ` [PULL 13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED Peter Maydell
2025-02-20 16:20 ` [PULL 14/41] target/arm: Correct errors in WFI/WFE trapping Peter Maydell
2025-02-20 16:20 ` [PULL 15/41] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Peter Maydell
2025-02-20 16:20 ` [PULL 16/41] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs Peter Maydell
2025-02-20 16:20 ` [PULL 17/41] hw/arm/realview: " Peter Maydell
2025-02-20 16:20 ` [PULL 18/41] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Peter Maydell
2025-02-20 16:21 ` [PULL 19/41] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs Peter Maydell
2025-02-20 16:21 ` [PULL 20/41] hw/arm/vexpress: " Peter Maydell
2025-02-20 16:21 ` [PULL 21/41] hw/arm/highbank: Specify explicitly the GIC has 128 " Peter Maydell
2025-02-20 16:21 ` [PULL 22/41] hw/cpu/arm_mpcore: Remove default values for GIC " Peter Maydell
2025-02-20 16:21 ` [PULL 23/41] Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX Peter Maydell
2025-02-20 16:21 ` [PULL 24/41] target/arm: Use uint32_t in t32_expandimm_imm() Peter Maydell
2025-02-20 16:21 ` [PULL 25/41] roms: Update vbootrom to 1287b6e Peter Maydell
2025-02-20 16:21 ` [PULL 26/41] pc-bios: Add NPCM8XX vBootrom Peter Maydell
2025-02-20 16:21 ` [PULL 27/41] hw/ssi: Make flash size a property in NPCM7XX FIU Peter Maydell
2025-02-20 16:21 ` [PULL 28/41] hw/misc: Rename npcm7xx_gcr to npcm_gcr Peter Maydell
2025-02-20 16:21 ` [PULL 29/41] hw/misc: Move NPCM7XX GCR to NPCM GCR Peter Maydell
2025-02-20 16:21 ` [PULL 30/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
2025-02-20 16:21 ` [PULL 31/41] hw/misc: Add support for NPCM8XX GCR Peter Maydell
2025-02-20 16:21 ` [PULL 32/41] hw/misc: Store DRAM size in NPCM8XX GCR Module Peter Maydell
2025-02-20 16:21 ` [PULL 33/41] hw/misc: Support 8-bytes memop in NPCM GCR module Peter Maydell
2025-02-20 16:21 ` [PULL 34/41] hw/misc: Rename npcm7xx_clk to npcm_clk Peter Maydell
2025-02-20 16:21 ` [PULL 35/41] hw/misc: Move NPCM7XX CLK to NPCM CLK Peter Maydell
2025-02-20 16:21 ` [PULL 36/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
2025-02-20 16:21 ` [PULL 37/41] hw/misc: Support NPCM8XX CLK Module Registers Peter Maydell
2025-02-20 16:21 ` [PULL 38/41] hw/net: Add NPCM8XX PCS Module Peter Maydell
2025-02-20 16:21 ` [PULL 39/41] hw/arm: Add NPCM8XX SoC Peter Maydell
2025-02-20 16:21 ` [PULL 40/41] hw/arm: Add NPCM845 Evaluation board Peter Maydell
2025-02-20 16:21 ` [PULL 41/41] docs/system/arm: Add Description for NPCM8XX SoC Peter Maydell
2025-02-21 21:02 ` [PULL 00/41] target-arm queue Stefan Hajnoczi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250220162123.626941-10-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).