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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 41/41] docs/system/arm: Add Description for NPCM8XX SoC
Date: Thu, 20 Feb 2025 16:21:22 +0000	[thread overview]
Message-ID: <20250220162123.626941-42-peter.maydell@linaro.org> (raw)
In-Reply-To: <20250220162123.626941-1-peter.maydell@linaro.org>

From: Hao Wu <wuhaotsh@google.com>

NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.

This document describes the NPCM8XX SoC and an evaluation board
(NPCM 845 EVB).

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250219184609.1839281-18-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst | 27 ++++++++++++++++++++-------
 hw/arm/npcm8xx_boards.c     |  1 +
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index 05059378e55..e4827fb43a1 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -1,12 +1,13 @@
-Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj``)
-=====================================================================================================
+Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj``, ``npcm845-evb``)
+======================================================================================================================
 
-The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
+The `Nuvoton iBMC`_ chips are a family of Arm-based SoCs that are
 designed to be used as Baseboard Management Controllers (BMCs) in various
-servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an
-assortment of peripherals targeted for either Enterprise or Data Center /
-Hyperscale applications. The former is a superset of the latter, so NPCM750 has
-all the peripherals of NPCM730 and more.
+servers. Currently there are two families: NPCM7XX series and
+NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
+while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
+different assortment of peripherals targeted for either Enterprise or Data
+Center / Hyperscale applications.
 
 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
 
@@ -27,6 +28,11 @@ There are also two more SoCs, NPCM710 and NPCM705, which are single-core
 variants of NPCM750 and NPCM730, respectively. These are currently not
 supported by QEMU.
 
+The NPCM8xx SoC is the successor of the NPCM7xx SoC. It has 4 Cortex-A35 cores.
+The following machines are based on this chip :
+
+- ``npcm845-evb``       Nuvoton NPCM845 Evaluation board
+
 Supported devices
 -----------------
 
@@ -62,6 +68,8 @@ Missing devices
    * System Wake-up Control (SWC)
    * Shared memory (SHM)
    * eSPI slave interface
+   * Block-transfer interface (8XX only)
+   * Virtual UART (8XX only)
 
  * Ethernet controller (GMAC)
  * USB device (USBD)
@@ -76,6 +84,11 @@ Missing devices
  * Video capture
  * Encoding compression engine
  * Security features
+ * I3C buses (8XX only)
+ * Temperature sensor interface (8XX only)
+ * Virtual UART (8XX only)
+ * Flash monitor (8XX only)
+ * JTAG master (8XX only)
 
 Boot options
 ------------
diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
index 19610483f93..3fb8478e72e 100644
--- a/hw/arm/npcm8xx_boards.c
+++ b/hw/arm/npcm8xx_boards.c
@@ -17,6 +17,7 @@
 #include "qemu/osdep.h"
 
 #include "chardev/char.h"
+#include "hw/boards.h"
 #include "hw/arm/npcm8xx.h"
 #include "hw/core/cpu.h"
 #include "hw/loader.h"
-- 
2.43.0



  parent reply	other threads:[~2025-02-20 16:28 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
2025-02-20 16:20 ` [PULL 01/41] target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1 Peter Maydell
2025-02-20 16:20 ` [PULL 02/41] target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS Peter Maydell
2025-02-20 16:20 ` [PULL 03/41] target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3 Peter Maydell
2025-02-20 16:20 ` [PULL 04/41] target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0 Peter Maydell
2025-02-20 16:20 ` [PULL 05/41] target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps Peter Maydell
2025-02-20 16:20 ` [PULL 06/41] hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3 Peter Maydell
2025-02-20 16:20 ` [PULL 07/41] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes Peter Maydell
2025-02-20 16:20 ` [PULL 08/41] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64() Peter Maydell
2025-02-20 16:20 ` [PULL 09/41] target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult Peter Maydell
2025-02-20 16:20 ` [PULL 10/41] target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1 Peter Maydell
2025-02-20 16:20 ` [PULL 11/41] target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps Peter Maydell
2025-02-20 16:20 ` [PULL 12/41] target/arm: Remove CP_ACCESS_TRAP handling Peter Maydell
2025-02-20 16:20 ` [PULL 13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED Peter Maydell
2025-02-20 16:20 ` [PULL 14/41] target/arm: Correct errors in WFI/WFE trapping Peter Maydell
2025-02-20 16:20 ` [PULL 15/41] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Peter Maydell
2025-02-20 16:20 ` [PULL 16/41] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs Peter Maydell
2025-02-20 16:20 ` [PULL 17/41] hw/arm/realview: " Peter Maydell
2025-02-20 16:20 ` [PULL 18/41] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Peter Maydell
2025-02-20 16:21 ` [PULL 19/41] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs Peter Maydell
2025-02-20 16:21 ` [PULL 20/41] hw/arm/vexpress: " Peter Maydell
2025-02-20 16:21 ` [PULL 21/41] hw/arm/highbank: Specify explicitly the GIC has 128 " Peter Maydell
2025-02-20 16:21 ` [PULL 22/41] hw/cpu/arm_mpcore: Remove default values for GIC " Peter Maydell
2025-02-20 16:21 ` [PULL 23/41] Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX Peter Maydell
2025-02-20 16:21 ` [PULL 24/41] target/arm: Use uint32_t in t32_expandimm_imm() Peter Maydell
2025-02-20 16:21 ` [PULL 25/41] roms: Update vbootrom to 1287b6e Peter Maydell
2025-02-20 16:21 ` [PULL 26/41] pc-bios: Add NPCM8XX vBootrom Peter Maydell
2025-02-20 16:21 ` [PULL 27/41] hw/ssi: Make flash size a property in NPCM7XX FIU Peter Maydell
2025-02-20 16:21 ` [PULL 28/41] hw/misc: Rename npcm7xx_gcr to npcm_gcr Peter Maydell
2025-02-20 16:21 ` [PULL 29/41] hw/misc: Move NPCM7XX GCR to NPCM GCR Peter Maydell
2025-02-20 16:21 ` [PULL 30/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
2025-02-20 16:21 ` [PULL 31/41] hw/misc: Add support for NPCM8XX GCR Peter Maydell
2025-02-20 16:21 ` [PULL 32/41] hw/misc: Store DRAM size in NPCM8XX GCR Module Peter Maydell
2025-02-20 16:21 ` [PULL 33/41] hw/misc: Support 8-bytes memop in NPCM GCR module Peter Maydell
2025-02-20 16:21 ` [PULL 34/41] hw/misc: Rename npcm7xx_clk to npcm_clk Peter Maydell
2025-02-20 16:21 ` [PULL 35/41] hw/misc: Move NPCM7XX CLK to NPCM CLK Peter Maydell
2025-02-20 16:21 ` [PULL 36/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
2025-02-20 16:21 ` [PULL 37/41] hw/misc: Support NPCM8XX CLK Module Registers Peter Maydell
2025-02-20 16:21 ` [PULL 38/41] hw/net: Add NPCM8XX PCS Module Peter Maydell
2025-02-20 16:21 ` [PULL 39/41] hw/arm: Add NPCM8XX SoC Peter Maydell
2025-02-20 16:21 ` [PULL 40/41] hw/arm: Add NPCM845 Evaluation board Peter Maydell
2025-02-20 16:21 ` Peter Maydell [this message]
2025-02-21 21:02 ` [PULL 00/41] target-arm queue Stefan Hajnoczi

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