qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/41] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes
Date: Thu, 20 Feb 2025 16:20:48 +0000	[thread overview]
Message-ID: <20250220162123.626941-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20250220162123.626941-1-peter.maydell@linaro.org>

There are not many traps in AArch32 which should trap to Monitor
mode, but these trap bits should trap not just lower ELs to Monitor
mode but also the non-Monitor modes running at EL3 (i.e.  Secure
System, Secure Undef, etc).

We get this wrong because the relevant access functions implement the
AArch64-style logic of
   if (el < 3 && trap_bit_set) {
       return CP_ACCESS_TRAP_EL3;
   }
which won't trap the non-Monitor modes at EL3.

Correct this error by using arm_is_el3_or_mon() instead, which
returns true when the CPU is at AArch64 EL3 or AArch32 Monitor mode.
(Since the new callsites are compiled also for the linux-user mode,
we need to provide a dummy implementation for CONFIG_USER_ONLY.)

This affects only:
 * trapping of ERRIDR via SCR.TERR
 * trapping of the debug channel registers via SDCR.TDCC
 * trapping of GICv3 registers via SCR.IRQ and SCR.FIQ
   (which we already used arm_is_el3_or_mon() for)

This patch changes the handling of SCR.TERR and SDCR.TDCC. This
patch only changes guest-visible behaviour for "-cpu max" on
the qemu-system-arm binary, because SCR.TERR
and SDCR.TDCC (and indeed the entire SDCR register) only arrived
in Armv8, and the only guest CPU we support which has any v8
features and also starts in AArch32 EL3 is the 32-bit 'max'.

Other uses of CP_ACCESS_TRAP_EL3 don't need changing:

 * uses in code paths that can't happen when EL3 is AArch32:
   access_trap_aa32s_el1, cpacr_access, cptr_access, nsacr_access
 * uses which are in accessfns for AArch64-only registers:
   gt_stimer_access, gt_cntpoff_access, access_hxen, access_tpidr2,
   access_smpri, access_smprimap, access_lor_ns, access_pauth,
   access_mte, access_tfsr_el2, access_scxtnum, access_fgt
 * trap bits which exist only in the AArch64 version of the
   trap register, not the AArch32 one:
   access_tpm, pmreg_access, access_dbgvcr32, access_tdra,
   access_tda, access_tdosa (TPM, TDA and TDOSA exist only in
   MDCR_EL3, not in SDCR, and we enforce this in sdcr_write())

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250130182309.717346-8-peter.maydell@linaro.org
---
 target/arm/cpu.h          | 5 +++++
 target/arm/debug_helper.c | 3 ++-
 target/arm/helper.c       | 2 +-
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 83ceaa58c2c..215845c7e25 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2596,6 +2596,11 @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
     return false;
 }
 
+static inline bool arm_is_el3_or_mon(CPUARMState *env)
+{
+    return false;
+}
+
 static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
 {
     return ARMSS_NonSecure;
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 2212ef4a3b9..c3c1eb5f628 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -880,7 +880,8 @@ static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
     if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
         return CP_ACCESS_TRAP_EL2;
     }
-    if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
+    if (!arm_is_el3_or_mon(env) &&
+        ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
         return CP_ACCESS_TRAP_EL3;
     }
     return CP_ACCESS_OK;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2bf39a2051d..535870f69a6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6103,7 +6103,7 @@ static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
     if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
         return CP_ACCESS_TRAP_EL2;
     }
-    if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
+    if (!arm_is_el3_or_mon(env) && (env->cp15.scr_el3 & SCR_TERR)) {
         return CP_ACCESS_TRAP_EL3;
     }
     return CP_ACCESS_OK;
-- 
2.43.0



  parent reply	other threads:[~2025-02-20 16:24 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-20 16:20 [PULL 00/41] target-arm queue Peter Maydell
2025-02-20 16:20 ` [PULL 01/41] target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS EL1 Peter Maydell
2025-02-20 16:20 ` [PULL 02/41] target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS Peter Maydell
2025-02-20 16:20 ` [PULL 03/41] target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3 Peter Maydell
2025-02-20 16:20 ` [PULL 04/41] target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0 Peter Maydell
2025-02-20 16:20 ` [PULL 05/41] target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps Peter Maydell
2025-02-20 16:20 ` [PULL 06/41] hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3 Peter Maydell
2025-02-20 16:20 ` Peter Maydell [this message]
2025-02-20 16:20 ` [PULL 08/41] hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64() Peter Maydell
2025-02-20 16:20 ` [PULL 09/41] target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult Peter Maydell
2025-02-20 16:20 ` [PULL 10/41] target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1 Peter Maydell
2025-02-20 16:20 ` [PULL 11/41] target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps Peter Maydell
2025-02-20 16:20 ` [PULL 12/41] target/arm: Remove CP_ACCESS_TRAP handling Peter Maydell
2025-02-20 16:20 ` [PULL 13/41] target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED Peter Maydell
2025-02-20 16:20 ` [PULL 14/41] target/arm: Correct errors in WFI/WFE trapping Peter Maydell
2025-02-20 16:20 ` [PULL 15/41] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition Peter Maydell
2025-02-20 16:20 ` [PULL 16/41] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs Peter Maydell
2025-02-20 16:20 ` [PULL 17/41] hw/arm/realview: " Peter Maydell
2025-02-20 16:20 ` [PULL 18/41] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL Peter Maydell
2025-02-20 16:21 ` [PULL 19/41] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs Peter Maydell
2025-02-20 16:21 ` [PULL 20/41] hw/arm/vexpress: " Peter Maydell
2025-02-20 16:21 ` [PULL 21/41] hw/arm/highbank: Specify explicitly the GIC has 128 " Peter Maydell
2025-02-20 16:21 ` [PULL 22/41] hw/cpu/arm_mpcore: Remove default values for GIC " Peter Maydell
2025-02-20 16:21 ` [PULL 23/41] Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX Peter Maydell
2025-02-20 16:21 ` [PULL 24/41] target/arm: Use uint32_t in t32_expandimm_imm() Peter Maydell
2025-02-20 16:21 ` [PULL 25/41] roms: Update vbootrom to 1287b6e Peter Maydell
2025-02-20 16:21 ` [PULL 26/41] pc-bios: Add NPCM8XX vBootrom Peter Maydell
2025-02-20 16:21 ` [PULL 27/41] hw/ssi: Make flash size a property in NPCM7XX FIU Peter Maydell
2025-02-20 16:21 ` [PULL 28/41] hw/misc: Rename npcm7xx_gcr to npcm_gcr Peter Maydell
2025-02-20 16:21 ` [PULL 29/41] hw/misc: Move NPCM7XX GCR to NPCM GCR Peter Maydell
2025-02-20 16:21 ` [PULL 30/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
2025-02-20 16:21 ` [PULL 31/41] hw/misc: Add support for NPCM8XX GCR Peter Maydell
2025-02-20 16:21 ` [PULL 32/41] hw/misc: Store DRAM size in NPCM8XX GCR Module Peter Maydell
2025-02-20 16:21 ` [PULL 33/41] hw/misc: Support 8-bytes memop in NPCM GCR module Peter Maydell
2025-02-20 16:21 ` [PULL 34/41] hw/misc: Rename npcm7xx_clk to npcm_clk Peter Maydell
2025-02-20 16:21 ` [PULL 35/41] hw/misc: Move NPCM7XX CLK to NPCM CLK Peter Maydell
2025-02-20 16:21 ` [PULL 36/41] hw/misc: Add nr_regs and cold_reset_values " Peter Maydell
2025-02-20 16:21 ` [PULL 37/41] hw/misc: Support NPCM8XX CLK Module Registers Peter Maydell
2025-02-20 16:21 ` [PULL 38/41] hw/net: Add NPCM8XX PCS Module Peter Maydell
2025-02-20 16:21 ` [PULL 39/41] hw/arm: Add NPCM8XX SoC Peter Maydell
2025-02-20 16:21 ` [PULL 40/41] hw/arm: Add NPCM845 Evaluation board Peter Maydell
2025-02-20 16:21 ` [PULL 41/41] docs/system/arm: Add Description for NPCM8XX SoC Peter Maydell
2025-02-21 21:02 ` [PULL 00/41] target-arm queue Stefan Hajnoczi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250220162123.626941-8-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).