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Fri, 21 Feb 2025 00:45:37 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::766e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439b030be5esm10376675e9.30.2025.02.21.00.45.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 00:45:36 -0800 (PST) Date: Fri, 21 Feb 2025 09:45:35 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH 3/3] target/riscv/kvm: reset all available KVM CSRs in kvm_reset() Message-ID: <20250221-1fab8b0e1e23a31880880f11@orel> References: <20250220161313.127376-1-dbarboza@ventanamicro.com> <20250220161313.127376-4-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250220161313.127376-4-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Feb 20, 2025 at 01:13:13PM -0300, Daniel Henrique Barboza wrote: > Explictly reset env->mstatus and env->sie. mie was already getting set to zero, so that should have just been renamed in the last patch, but I still think we should drop the last patch. > Add a comment about env->mip > being read/written into KVM 'sip' CSR. > > We're also not read/writing 'scounteren' which is available in the KVM > UAPI. Add it in kvm_reset() and get/put_regs_csr(). > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/kvm/kvm-cpu.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index fea03f3657..ee7a9295b4 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -618,6 +618,7 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) > KVM_RISCV_GET_CSR(cs, env, stval, env->stval); > KVM_RISCV_GET_CSR(cs, env, sip, env->mip); > KVM_RISCV_GET_CSR(cs, env, satp, env->satp); > + KVM_RISCV_GET_CSR(cs, env, scounteren, env->scounteren); senvcfg is also missing. > > return 0; > } > @@ -635,6 +636,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) > KVM_RISCV_SET_CSR(cs, env, stval, env->stval); > KVM_RISCV_SET_CSR(cs, env, sip, env->mip); > KVM_RISCV_SET_CSR(cs, env, satp, env->satp); > + KVM_RISCV_SET_CSR(cs, env, scounteren, env->scounteren); > > return 0; > } > @@ -1609,6 +1611,10 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) > env->pc = cpu->env.kernel_addr; > env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ > env->gpr[11] = cpu->env.fdt_addr; /* a1 */ > + > + /* sstatus is read/written into mstatus */ How about just a single comment above this function stating that we reset all registers that we will s/r with csr get/put. Interested parties can go look at get or put to see the mappings. > + env->mstatus = 0; > + env->sie = 0; > env->satp = 0; > env->mie = 0; > env->stvec = 0; > @@ -1616,7 +1622,9 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) > env->sepc = 0; > env->scause = 0; > env->stval = 0; > + /* sip is read/written into mip */ > env->mip = 0; > + env->scounteren = 0; > } > > void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) > -- > 2.48.1 > > Thanks, drew