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From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  bmeng@tinylab.org,
	liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
	 palmer@rivosinc.com
Subject: Re: [PATCH 2/3] target/riscv/kvm: use env->sie to read/write 'sie' CSR
Date: Fri, 21 Feb 2025 09:37:32 +0100	[thread overview]
Message-ID: <20250221-770a4da9465046f4fae9dc20@orel> (raw)
In-Reply-To: <20250220161313.127376-3-dbarboza@ventanamicro.com>

On Thu, Feb 20, 2025 at 01:13:12PM -0300, Daniel Henrique Barboza wrote:
> Using env->sie is clearer than using env->mie.

Maybe? Just as sstatus is a subset of mstatus, sip and sie can be
subsets of mip and mie. However, the AIA can change sip/sie so they
no longer alias mip/mie, which is why we have 'mvip' an 'sie' members
in CPURISCVState. In the end, for KVM, it doesn't really matter since
this is just s/r storage. I'd probably just drop this patch and keep
using mie. Otherwise, what about mip?

Thanks,
drew

> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>  target/riscv/kvm/kvm-cpu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index 484b6afe7c..fea03f3657 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -610,7 +610,7 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
>      CPURISCVState *env = &RISCV_CPU(cs)->env;
>  
>      KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
> -    KVM_RISCV_GET_CSR(cs, env, sie, env->mie);
> +    KVM_RISCV_GET_CSR(cs, env, sie, env->sie);
>      KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec);
>      KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch);
>      KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc);
> @@ -627,7 +627,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs)
>      CPURISCVState *env = &RISCV_CPU(cs)->env;
>  
>      KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
> -    KVM_RISCV_SET_CSR(cs, env, sie, env->mie);
> +    KVM_RISCV_SET_CSR(cs, env, sie, env->sie);
>      KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec);
>      KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch);
>      KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc);
> -- 
> 2.48.1
> 
> 


  reply	other threads:[~2025-02-21  8:38 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-20 16:13 [PATCH 0/3] target/riscv/kvm: reset time changes Daniel Henrique Barboza
2025-02-20 16:13 ` [PATCH 1/3] target/riscv/cpu: ignore TCG init for KVM CPUs in reset_hold Daniel Henrique Barboza
2025-02-21  8:17   ` Andrew Jones
2025-02-24  2:03   ` Alistair Francis
2025-02-24  9:59   ` Peter Maydell
2025-02-24 11:29     ` Daniel Henrique Barboza
2025-02-24 11:47       ` Peter Maydell
2025-02-24 12:00         ` Daniel Henrique Barboza
2025-02-20 16:13 ` [PATCH 2/3] target/riscv/kvm: use env->sie to read/write 'sie' CSR Daniel Henrique Barboza
2025-02-21  8:37   ` Andrew Jones [this message]
2025-02-21  9:26     ` Daniel Henrique Barboza
2025-02-20 16:13 ` [PATCH 3/3] target/riscv/kvm: reset all available KVM CSRs in kvm_reset() Daniel Henrique Barboza
2025-02-21  8:45   ` Andrew Jones
2025-02-21  9:01     ` Andrew Jones

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