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Fri, 21 Feb 2025 00:17:07 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::766e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f259f85c2sm23463039f8f.91.2025.02.21.00.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2025 00:17:06 -0800 (PST) Date: Fri, 21 Feb 2025 09:17:05 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH 1/3] target/riscv/cpu: ignore TCG init for KVM CPUs in reset_hold Message-ID: <20250221-c821005cfd03e3fd07df4817@orel> References: <20250220161313.127376-1-dbarboza@ventanamicro.com> <20250220161313.127376-2-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250220161313.127376-2-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Feb 20, 2025 at 01:13:11PM -0300, Daniel Henrique Barboza wrote: > riscv_cpu_reset_hold() does a lot of TCG-related initializations that > aren't relevant for KVM, but nevertheless are impacting the reset state > of KVM vcpus. > > When running a KVM guest, kvm_riscv_reset_vcpu() is called at the end of > reset_hold(). At that point env->mstatus is initialized to a non-zero > value, and it will be use to write 'sstatus' in the vcpu > (kvm_arch_put_registers() then kvm_riscv_put_regs_csr()). > > Do an early exit in riscv_cpu_reset_hold() if we're running KVM. All the > KVM reset procedure will be centered in kvm_riscv_reset_vcpu(). > > While we're at it, remove the kvm_enabled() check in > kvm_riscv_reset_vcpu() since it's already being gated in > riscv_cpu_reset_hold(). > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 9 +++++---- > target/riscv/kvm/kvm-cpu.c | 3 --- > 2 files changed, 5 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 522d6584e4..8e6e629ec4 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1050,6 +1050,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) > mcc->parent_phases.hold(obj, type); > } > #ifndef CONFIG_USER_ONLY > + if (kvm_enabled()) { > + kvm_riscv_reset_vcpu(cpu); > + return; > + } > + > env->misa_mxl = mcc->misa_mxl_max; > env->priv = PRV_M; > env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); > @@ -1146,10 +1151,6 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) > env->rnmip = 0; > env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); > } > - > - if (kvm_enabled()) { > - kvm_riscv_reset_vcpu(cpu); > - } > #endif > } > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 23ce779359..484b6afe7c 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -1603,9 +1603,6 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) > CPURISCVState *env = &cpu->env; > int i; > > - if (!kvm_enabled()) { > - return; > - } > for (i = 0; i < 32; i++) { > env->gpr[i] = 0; > } > -- > 2.48.1 > > Reviewed-by: Andrew Jones