From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH 3/3] target/riscv/kvm: reset all available KVM CSRs in kvm_reset()
Date: Fri, 21 Feb 2025 10:01:57 +0100 [thread overview]
Message-ID: <20250221-d80c128acaf0210e80461d56@orel> (raw)
In-Reply-To: <20250221-1fab8b0e1e23a31880880f11@orel>
On Fri, Feb 21, 2025 at 09:45:35AM +0100, Andrew Jones wrote:
> On Thu, Feb 20, 2025 at 01:13:13PM -0300, Daniel Henrique Barboza wrote:
> > Explictly reset env->mstatus and env->sie.
>
> mie was already getting set to zero, so that should have just been renamed
> in the last patch, but I still think we should drop the last patch.
>
> > Add a comment about env->mip
> > being read/written into KVM 'sip' CSR.
> >
> > We're also not read/writing 'scounteren' which is available in the KVM
> > UAPI. Add it in kvm_reset() and get/put_regs_csr().
> >
> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> > ---
> > target/riscv/kvm/kvm-cpu.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> > index fea03f3657..ee7a9295b4 100644
> > --- a/target/riscv/kvm/kvm-cpu.c
> > +++ b/target/riscv/kvm/kvm-cpu.c
> > @@ -618,6 +618,7 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
> > KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
> > KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
> > KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
> > + KVM_RISCV_GET_CSR(cs, env, scounteren, env->scounteren);
>
> senvcfg is also missing.
>
> >
> > return 0;
> > }
> > @@ -635,6 +636,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs)
> > KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
> > KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
> > KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
> > + KVM_RISCV_SET_CSR(cs, env, scounteren, env->scounteren);
> >
> > return 0;
> > }
> > @@ -1609,6 +1611,10 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> > env->pc = cpu->env.kernel_addr;
> > env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */
> > env->gpr[11] = cpu->env.fdt_addr; /* a1 */
> > +
> > + /* sstatus is read/written into mstatus */
>
> How about just a single comment above this function stating that we
> reset all registers that we will s/r with csr get/put. Interested
> parties can go look at get or put to see the mappings.
>
> > + env->mstatus = 0;
> > + env->sie = 0;
> > env->satp = 0;
> > env->mie = 0;
> > env->stvec = 0;
> > @@ -1616,7 +1622,9 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> > env->sepc = 0;
> > env->scause = 0;
> > env->stval = 0;
> > + /* sip is read/written into mip */
> > env->mip = 0;
> > + env->scounteren = 0;
It'd be nice to put all the above register assignments in the order of
struct kvm_riscv_csr, like get/put do.
Thanks,
drew
> > }
> >
> > void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
> > --
> > 2.48.1
> >
> >
>
> Thanks,
> drew
prev parent reply other threads:[~2025-02-21 9:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-20 16:13 [PATCH 0/3] target/riscv/kvm: reset time changes Daniel Henrique Barboza
2025-02-20 16:13 ` [PATCH 1/3] target/riscv/cpu: ignore TCG init for KVM CPUs in reset_hold Daniel Henrique Barboza
2025-02-21 8:17 ` Andrew Jones
2025-02-24 2:03 ` Alistair Francis
2025-02-24 9:59 ` Peter Maydell
2025-02-24 11:29 ` Daniel Henrique Barboza
2025-02-24 11:47 ` Peter Maydell
2025-02-24 12:00 ` Daniel Henrique Barboza
2025-02-20 16:13 ` [PATCH 2/3] target/riscv/kvm: use env->sie to read/write 'sie' CSR Daniel Henrique Barboza
2025-02-21 8:37 ` Andrew Jones
2025-02-21 9:26 ` Daniel Henrique Barboza
2025-02-20 16:13 ` [PATCH 3/3] target/riscv/kvm: reset all available KVM CSRs in kvm_reset() Daniel Henrique Barboza
2025-02-21 8:45 ` Andrew Jones
2025-02-21 9:01 ` Andrew Jones [this message]
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