* [PATCH v2 1/3] hw/intc/imsic: refine the IMSIC realize
2025-02-24 2:57 [PATCH v2 0/3] riscv: AIA: refinement for KVM acceleration Yong-Xuan Wang
@ 2025-02-24 2:57 ` Yong-Xuan Wang
2025-02-26 11:35 ` Daniel Henrique Barboza
2025-02-24 2:57 ` [PATCH v2 2/3] hw/intc/aplic: refine the APLIC realize Yong-Xuan Wang
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Yong-Xuan Wang @ 2025-02-24 2:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: greentime.hu, vincent.chen, frank.chang, jim.shu, Yong-Xuan Wang,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
When the IMSIC is emulated in the kernel, the GPIO output lines to CPUs
and aia_ireg_rmw_fn setting can be remove. In this case the IMSIC
trigger CPU interrupts by KVM APIs, and the RMW of IREG is handled in
kernel.
This patch also move the code that claim the CPU interrupts to the
beginning of IMSIC realization. This can avoid the unnecessary resource
allocation before checking failed.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
---
hw/intc/riscv_imsic.c | 47 ++++++++++++++++++++++++-------------------
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index dc8162c0a7c9..241b12fef09f 100644
--- a/hw/intc/riscv_imsic.c
+++ b/hw/intc/riscv_imsic.c
@@ -349,7 +349,19 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
CPUState *cpu = cpu_by_arch_id(imsic->hartid);
CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
+ /* Claim the CPU interrupt to be triggered by this IMSIC */
+ if (riscv_cpu_claim_interrupts(rcpu,
+ (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
+ error_setg(errp, "%s already claimed",
+ (imsic->mmode) ? "MEIP" : "SEIP");
+ return;
+ }
+
if (!kvm_irqchip_in_kernel()) {
+ /* Create output IRQ lines */
+ imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);
+ qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);
+
imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
@@ -361,18 +373,6 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
IMSIC_MMIO_SIZE(imsic->num_pages));
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio);
- /* Claim the CPU interrupt to be triggered by this IMSIC */
- if (riscv_cpu_claim_interrupts(rcpu,
- (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
- error_setg(errp, "%s already claimed",
- (imsic->mmode) ? "MEIP" : "SEIP");
- return;
- }
-
- /* Create output IRQ lines */
- imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);
- qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);
-
/* Force select AIA feature and setup CSR read-modify-write callback */
if (env) {
if (!imsic->mmode) {
@@ -381,8 +381,11 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
} else {
rcpu->cfg.ext_smaia = true;
}
- riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
- riscv_imsic_rmw, imsic);
+
+ if (!kvm_irqchip_in_kernel()) {
+ riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
+ riscv_imsic_rmw, imsic);
+ }
}
msi_nonbroken = true;
@@ -464,15 +467,17 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
- for (i = 0; i < num_pages; i++) {
- if (!i) {
- qdev_connect_gpio_out_named(dev, NULL, i,
- qdev_get_gpio_in(DEVICE(cpu),
+ if (!kvm_irqchip_in_kernel()) {
+ for (i = 0; i < num_pages; i++) {
+ if (!i) {
+ qdev_connect_gpio_out_named(dev, NULL, i,
+ qdev_get_gpio_in(DEVICE(cpu),
(mmode) ? IRQ_M_EXT : IRQ_S_EXT));
- } else {
- qdev_connect_gpio_out_named(dev, NULL, i,
- qdev_get_gpio_in(DEVICE(cpu),
+ } else {
+ qdev_connect_gpio_out_named(dev, NULL, i,
+ qdev_get_gpio_in(DEVICE(cpu),
IRQ_LOCAL_MAX + i - 1));
+ }
}
}
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/3] hw/intc/imsic: refine the IMSIC realize
2025-02-24 2:57 ` [PATCH v2 1/3] hw/intc/imsic: refine the IMSIC realize Yong-Xuan Wang
@ 2025-02-26 11:35 ` Daniel Henrique Barboza
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Henrique Barboza @ 2025-02-26 11:35 UTC (permalink / raw)
To: Yong-Xuan Wang, qemu-devel, qemu-riscv
Cc: greentime.hu, vincent.chen, frank.chang, jim.shu, Palmer Dabbelt,
Alistair Francis, Weiwei Li, Liu Zhiwei
On 2/23/25 11:57 PM, Yong-Xuan Wang wrote:
> When the IMSIC is emulated in the kernel, the GPIO output lines to CPUs
> and aia_ireg_rmw_fn setting can be remove. In this case the IMSIC
> trigger CPU interrupts by KVM APIs, and the RMW of IREG is handled in
> kernel.
>
> This patch also move the code that claim the CPU interrupts to the
> beginning of IMSIC realization. This can avoid the unnecessary resource
> allocation before checking failed.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> hw/intc/riscv_imsic.c | 47 ++++++++++++++++++++++++-------------------
> 1 file changed, 26 insertions(+), 21 deletions(-)
>
> diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
> index dc8162c0a7c9..241b12fef09f 100644
> --- a/hw/intc/riscv_imsic.c
> +++ b/hw/intc/riscv_imsic.c
> @@ -349,7 +349,19 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
> CPUState *cpu = cpu_by_arch_id(imsic->hartid);
> CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;
>
> + /* Claim the CPU interrupt to be triggered by this IMSIC */
> + if (riscv_cpu_claim_interrupts(rcpu,
> + (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
> + error_setg(errp, "%s already claimed",
> + (imsic->mmode) ? "MEIP" : "SEIP");
> + return;
> + }
> +
> if (!kvm_irqchip_in_kernel()) {
> + /* Create output IRQ lines */
> + imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);
> + qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);
> +
> imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
> imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
> imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
> @@ -361,18 +373,6 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
> IMSIC_MMIO_SIZE(imsic->num_pages));
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio);
>
> - /* Claim the CPU interrupt to be triggered by this IMSIC */
> - if (riscv_cpu_claim_interrupts(rcpu,
> - (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
> - error_setg(errp, "%s already claimed",
> - (imsic->mmode) ? "MEIP" : "SEIP");
> - return;
> - }
> -
> - /* Create output IRQ lines */
> - imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);
> - qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);
> -
> /* Force select AIA feature and setup CSR read-modify-write callback */
> if (env) {
> if (!imsic->mmode) {
> @@ -381,8 +381,11 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
> } else {
> rcpu->cfg.ext_smaia = true;
> }
> - riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
> - riscv_imsic_rmw, imsic);
> +
> + if (!kvm_irqchip_in_kernel()) {
> + riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
> + riscv_imsic_rmw, imsic);
> + }
> }
>
> msi_nonbroken = true;
> @@ -464,15 +467,17 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
>
> - for (i = 0; i < num_pages; i++) {
> - if (!i) {
> - qdev_connect_gpio_out_named(dev, NULL, i,
> - qdev_get_gpio_in(DEVICE(cpu),
> + if (!kvm_irqchip_in_kernel()) {
> + for (i = 0; i < num_pages; i++) {
> + if (!i) {
> + qdev_connect_gpio_out_named(dev, NULL, i,
> + qdev_get_gpio_in(DEVICE(cpu),
> (mmode) ? IRQ_M_EXT : IRQ_S_EXT));
> - } else {
> - qdev_connect_gpio_out_named(dev, NULL, i,
> - qdev_get_gpio_in(DEVICE(cpu),
> + } else {
> + qdev_connect_gpio_out_named(dev, NULL, i,
> + qdev_get_gpio_in(DEVICE(cpu),
> IRQ_LOCAL_MAX + i - 1));
> + }
> }
> }
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] hw/intc/aplic: refine the APLIC realize
2025-02-24 2:57 [PATCH v2 0/3] riscv: AIA: refinement for KVM acceleration Yong-Xuan Wang
2025-02-24 2:57 ` [PATCH v2 1/3] hw/intc/imsic: refine the IMSIC realize Yong-Xuan Wang
@ 2025-02-24 2:57 ` Yong-Xuan Wang
2025-02-26 11:36 ` Daniel Henrique Barboza
2025-02-24 2:57 ` [PATCH v2 3/3] hw/intc/aplic: refine kvm_msicfgaddr Yong-Xuan Wang
2025-02-28 6:09 ` [PATCH v2 0/3] riscv: AIA: refinement for KVM acceleration Alistair Francis
3 siblings, 1 reply; 8+ messages in thread
From: Yong-Xuan Wang @ 2025-02-24 2:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: greentime.hu, vincent.chen, frank.chang, jim.shu, Yong-Xuan Wang,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
When the APLIC is emulated in the kernel, the GPIO output lines to CPUs
can be remove. In this case the APLIC trigger CPU interrupts by KVM APIs.
This patch also move the code that claim the CPU interrupts to the
beginning of APLIC realization. This can avoid the unnecessary resource
allocation before checking failed.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
---
hw/intc/riscv_aplic.c | 49 +++++++++++++++++++++++--------------------
1 file changed, 26 insertions(+), 23 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 0974c6a5db39..e5714267c096 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -893,6 +893,26 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
RISCVAPLICState *aplic = RISCV_APLIC(dev);
if (riscv_use_emulated_aplic(aplic->msimode)) {
+ /* Create output IRQ lines for non-MSI mode */
+ if (!aplic->msimode) {
+ /* Claim the CPU interrupt to be triggered by this APLIC */
+ for (i = 0; i < aplic->num_harts; i++) {
+ RISCVCPU *cpu;
+
+ cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
+ if (riscv_cpu_claim_interrupts(cpu,
+ (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
+ error_report("%s already claimed",
+ (aplic->mmode) ? "MEIP" : "SEIP");
+ exit(1);
+ }
+ }
+
+ aplic->external_irqs = g_malloc(sizeof(qemu_irq) *
+ aplic->num_harts);
+ qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts);
+ }
+
aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
aplic->state = g_new0(uint32_t, aplic->num_irqs);
@@ -927,23 +947,6 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
}
}
- /* Create output IRQ lines for non-MSI mode */
- if (!aplic->msimode) {
- aplic->external_irqs = g_malloc(sizeof(qemu_irq) * aplic->num_harts);
- qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts);
-
- /* Claim the CPU interrupt to be triggered by this APLIC */
- for (i = 0; i < aplic->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
- if (riscv_cpu_claim_interrupts(cpu,
- (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
- error_report("%s already claimed",
- (aplic->mmode) ? "MEIP" : "SEIP");
- exit(1);
- }
- }
- }
-
msi_nonbroken = true;
}
@@ -1067,15 +1070,15 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
if (riscv_use_emulated_aplic(msimode)) {
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
- }
- if (!msimode) {
- for (i = 0; i < num_harts; i++) {
- CPUState *cpu = cpu_by_arch_id(hartid_base + i);
+ if (!msimode) {
+ for (i = 0; i < num_harts; i++) {
+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);
- qdev_connect_gpio_out_named(dev, NULL, i,
- qdev_get_gpio_in(DEVICE(cpu),
+ qdev_connect_gpio_out_named(dev, NULL, i,
+ qdev_get_gpio_in(DEVICE(cpu),
(mmode) ? IRQ_M_EXT : IRQ_S_EXT));
+ }
}
}
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/3] hw/intc/aplic: refine the APLIC realize
2025-02-24 2:57 ` [PATCH v2 2/3] hw/intc/aplic: refine the APLIC realize Yong-Xuan Wang
@ 2025-02-26 11:36 ` Daniel Henrique Barboza
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Henrique Barboza @ 2025-02-26 11:36 UTC (permalink / raw)
To: Yong-Xuan Wang, qemu-devel, qemu-riscv
Cc: greentime.hu, vincent.chen, frank.chang, jim.shu, Palmer Dabbelt,
Alistair Francis, Weiwei Li, Liu Zhiwei
On 2/23/25 11:57 PM, Yong-Xuan Wang wrote:
> When the APLIC is emulated in the kernel, the GPIO output lines to CPUs
> can be remove. In this case the APLIC trigger CPU interrupts by KVM APIs.
>
> This patch also move the code that claim the CPU interrupts to the
> beginning of APLIC realization. This can avoid the unnecessary resource
> allocation before checking failed.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> hw/intc/riscv_aplic.c | 49 +++++++++++++++++++++++--------------------
> 1 file changed, 26 insertions(+), 23 deletions(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index 0974c6a5db39..e5714267c096 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -893,6 +893,26 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
> RISCVAPLICState *aplic = RISCV_APLIC(dev);
>
> if (riscv_use_emulated_aplic(aplic->msimode)) {
> + /* Create output IRQ lines for non-MSI mode */
> + if (!aplic->msimode) {
> + /* Claim the CPU interrupt to be triggered by this APLIC */
> + for (i = 0; i < aplic->num_harts; i++) {
> + RISCVCPU *cpu;
> +
> + cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
> + if (riscv_cpu_claim_interrupts(cpu,
> + (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
> + error_report("%s already claimed",
> + (aplic->mmode) ? "MEIP" : "SEIP");
> + exit(1);
> + }
> + }
> +
> + aplic->external_irqs = g_malloc(sizeof(qemu_irq) *
> + aplic->num_harts);
> + qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts);
> + }
> +
> aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
> aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
> aplic->state = g_new0(uint32_t, aplic->num_irqs);
> @@ -927,23 +947,6 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
> }
> }
>
> - /* Create output IRQ lines for non-MSI mode */
> - if (!aplic->msimode) {
> - aplic->external_irqs = g_malloc(sizeof(qemu_irq) * aplic->num_harts);
> - qdev_init_gpio_out(dev, aplic->external_irqs, aplic->num_harts);
> -
> - /* Claim the CPU interrupt to be triggered by this APLIC */
> - for (i = 0; i < aplic->num_harts; i++) {
> - RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
> - if (riscv_cpu_claim_interrupts(cpu,
> - (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
> - error_report("%s already claimed",
> - (aplic->mmode) ? "MEIP" : "SEIP");
> - exit(1);
> - }
> - }
> - }
> -
> msi_nonbroken = true;
> }
>
> @@ -1067,15 +1070,15 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
>
> if (riscv_use_emulated_aplic(msimode)) {
> sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
> - }
>
> - if (!msimode) {
> - for (i = 0; i < num_harts; i++) {
> - CPUState *cpu = cpu_by_arch_id(hartid_base + i);
> + if (!msimode) {
> + for (i = 0; i < num_harts; i++) {
> + CPUState *cpu = cpu_by_arch_id(hartid_base + i);
>
> - qdev_connect_gpio_out_named(dev, NULL, i,
> - qdev_get_gpio_in(DEVICE(cpu),
> + qdev_connect_gpio_out_named(dev, NULL, i,
> + qdev_get_gpio_in(DEVICE(cpu),
> (mmode) ? IRQ_M_EXT : IRQ_S_EXT));
> + }
> }
> }
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] hw/intc/aplic: refine kvm_msicfgaddr
2025-02-24 2:57 [PATCH v2 0/3] riscv: AIA: refinement for KVM acceleration Yong-Xuan Wang
2025-02-24 2:57 ` [PATCH v2 1/3] hw/intc/imsic: refine the IMSIC realize Yong-Xuan Wang
2025-02-24 2:57 ` [PATCH v2 2/3] hw/intc/aplic: refine the APLIC realize Yong-Xuan Wang
@ 2025-02-24 2:57 ` Yong-Xuan Wang
2025-02-26 11:48 ` Daniel Henrique Barboza
2025-02-28 6:09 ` [PATCH v2 0/3] riscv: AIA: refinement for KVM acceleration Alistair Francis
3 siblings, 1 reply; 8+ messages in thread
From: Yong-Xuan Wang @ 2025-02-24 2:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: greentime.hu, vincent.chen, frank.chang, jim.shu, Yong-Xuan Wang,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
Let kvm_msicfgaddr use the same format with mmsicfgaddr and smsicfgaddr.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
---
hw/intc/riscv_aplic.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index e5714267c096..5964cde7e09e 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -181,8 +181,10 @@ void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr)
{
#ifdef CONFIG_KVM
if (riscv_use_emulated_aplic(aplic->msimode)) {
+ addr >>= APLIC_xMSICFGADDR_PPN_SHIFT;
aplic->kvm_msicfgaddr = extract64(addr, 0, 32);
- aplic->kvm_msicfgaddrH = extract64(addr, 32, 32);
+ aplic->kvm_msicfgaddrH = extract64(addr, 32, 32) &
+ APLIC_xMSICFGADDRH_VALID_MASK;
}
#endif
}
@@ -403,12 +405,17 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
}
}
- if (aplic->mmode) {
- msicfgaddr = aplic_m->mmsicfgaddr;
- msicfgaddrH = aplic_m->mmsicfgaddrH;
+ if (aplic->kvm_splitmode) {
+ msicfgaddr = aplic->kvm_msicfgaddr;
+ msicfgaddrH = ((uint64_t)aplic->kvm_msicfgaddrH << 32);
} else {
- msicfgaddr = aplic_m->smsicfgaddr;
- msicfgaddrH = aplic_m->smsicfgaddrH;
+ if (aplic->mmode) {
+ msicfgaddr = aplic_m->mmsicfgaddr;
+ msicfgaddrH = aplic_m->mmsicfgaddrH;
+ } else {
+ msicfgaddr = aplic_m->smsicfgaddr;
+ msicfgaddrH = aplic_m->smsicfgaddrH;
+ }
}
lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) &
@@ -431,11 +438,6 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
addr <<= APLIC_xMSICFGADDR_PPN_SHIFT;
- if (aplic->kvm_splitmode) {
- addr |= aplic->kvm_msicfgaddr;
- addr |= ((uint64_t)aplic->kvm_msicfgaddrH << 32);
- }
-
address_space_stl_le(&address_space_memory, addr,
eiid, MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) {
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/3] hw/intc/aplic: refine kvm_msicfgaddr
2025-02-24 2:57 ` [PATCH v2 3/3] hw/intc/aplic: refine kvm_msicfgaddr Yong-Xuan Wang
@ 2025-02-26 11:48 ` Daniel Henrique Barboza
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Henrique Barboza @ 2025-02-26 11:48 UTC (permalink / raw)
To: Yong-Xuan Wang, qemu-devel, qemu-riscv
Cc: greentime.hu, vincent.chen, frank.chang, jim.shu, Palmer Dabbelt,
Alistair Francis, Weiwei Li, Liu Zhiwei
On 2/23/25 11:57 PM, Yong-Xuan Wang wrote:
> Let kvm_msicfgaddr use the same format with mmsicfgaddr and smsicfgaddr.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> hw/intc/riscv_aplic.c | 24 +++++++++++++-----------
> 1 file changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index e5714267c096..5964cde7e09e 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -181,8 +181,10 @@ void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr)
> {
> #ifdef CONFIG_KVM
> if (riscv_use_emulated_aplic(aplic->msimode)) {
> + addr >>= APLIC_xMSICFGADDR_PPN_SHIFT;
> aplic->kvm_msicfgaddr = extract64(addr, 0, 32);
> - aplic->kvm_msicfgaddrH = extract64(addr, 32, 32);
> + aplic->kvm_msicfgaddrH = extract64(addr, 32, 32) &
> + APLIC_xMSICFGADDRH_VALID_MASK;
> }
> #endif
> }
> @@ -403,12 +405,17 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
> }
> }
>
> - if (aplic->mmode) {
> - msicfgaddr = aplic_m->mmsicfgaddr;
> - msicfgaddrH = aplic_m->mmsicfgaddrH;
> + if (aplic->kvm_splitmode) {
> + msicfgaddr = aplic->kvm_msicfgaddr;
> + msicfgaddrH = ((uint64_t)aplic->kvm_msicfgaddrH << 32);
> } else {
> - msicfgaddr = aplic_m->smsicfgaddr;
> - msicfgaddrH = aplic_m->smsicfgaddrH;
> + if (aplic->mmode) {
> + msicfgaddr = aplic_m->mmsicfgaddr;
> + msicfgaddrH = aplic_m->mmsicfgaddrH;
> + } else {
> + msicfgaddr = aplic_m->smsicfgaddr;
> + msicfgaddrH = aplic_m->smsicfgaddrH;
> + }
> }
>
> lhxs = (msicfgaddrH >> APLIC_xMSICFGADDRH_LHXS_SHIFT) &
> @@ -431,11 +438,6 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
> addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
> addr <<= APLIC_xMSICFGADDR_PPN_SHIFT;
>
> - if (aplic->kvm_splitmode) {
> - addr |= aplic->kvm_msicfgaddr;
> - addr |= ((uint64_t)aplic->kvm_msicfgaddrH << 32);
> - }
> -
> address_space_stl_le(&address_space_memory, addr,
> eiid, MEMTXATTRS_UNSPECIFIED, &result);
> if (result != MEMTX_OK) {
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/3] riscv: AIA: refinement for KVM acceleration
2025-02-24 2:57 [PATCH v2 0/3] riscv: AIA: refinement for KVM acceleration Yong-Xuan Wang
` (2 preceding siblings ...)
2025-02-24 2:57 ` [PATCH v2 3/3] hw/intc/aplic: refine kvm_msicfgaddr Yong-Xuan Wang
@ 2025-02-28 6:09 ` Alistair Francis
3 siblings, 0 replies; 8+ messages in thread
From: Alistair Francis @ 2025-02-28 6:09 UTC (permalink / raw)
To: Yong-Xuan Wang
Cc: qemu-devel, qemu-riscv, greentime.hu, vincent.chen, frank.chang,
jim.shu
On Mon, Feb 24, 2025 at 12:58 PM Yong-Xuan Wang
<yongxuan.wang@sifive.com> wrote:
>
> Reorder the code to reduce the conditional checking and remove
> unnecessary resource setting when using in-kernl AIA irqchip.
>
> ---
> v2:
> - remove the code reordering of the riscv-virt machine since it can't
> work with NUMA setting. (Daniel)
>
> Yong-Xuan Wang (3):
> hw/intc/imsic: refine the IMSIC realize
> hw/intc/aplic: refine the APLIC realize
> hw/intc/aplic: refine kvm_msicfgaddr
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> hw/intc/riscv_aplic.c | 73 +++++++++++++++++++++++--------------------
> hw/intc/riscv_imsic.c | 47 +++++++++++++++-------------
> 2 files changed, 65 insertions(+), 55 deletions(-)
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread