Re: [PATCH 0/5] PCI: Implement basic PCI PM capability backing

[Alex Williamson <alex.williamson@redhat.com>]

On Mon, 24 Feb 2025 09:14:19 +0100
Cédric Le Goater <clg@redhat.com> wrote:

> > An aspect that needs attention here is whether this change in the
> > wmask and PMCSR bits becomes a problem for migration, and how we
> > might solve it.  For a guest migrating old->new, the device would
> > always be in the D0 power state, but the register becomes writable.
> > In the opposite direction, is it possible that a device could
> > migrate in a low power state and be stuck there since the bits are
> > read-only in old QEMU?  Do we need an option for this behavior and a
> > machine state bump, or are there alternatives?  
> 
> Should we introduce a migration blocker when a PCI device is in low
> power state  ?

Blocking relative to the power state of a device seems relatively
non-intuitive for a user to debug.  Logically there's also an
opportunity that any device could support migration while in D3 if it
indicates a soft reset is performed on D3->D0 transition, regardless of
underlying VMM support for the device to migrate.  So that doesn't
really feel like the right approach to me.

FWIW, the emulated igb device will enter D3 when idle and bound to
vfio-pci in the guest, so we should be able to test migration in
various states with purely emulated devices.  Thanks,

Alex