[PATCH v2 0/6] Improve Microchip Polarfire SoC customization

[PATCH v2 0/6] Improve Microchip Polarfire SoC customization

[Sebastian Huber]

Booting the microchip-icicle-kit machine using the latest PolarFire SoC
Hart Software Services (HSS) no longer works since Qemu lacks support
for several registers (clocks, DRAM controller). Also reading from the
SDCard does not work currently.

In order to allow tests runs for real-time kernels such as RTEMS and
Zephyr, improve the boot customization. This patch set enables a direct
run of kernel executables, for example:

qemu-system-riscv64 -no-reboot -nographic \
  -serial null -serial mon:stdio \
  -smp 2 \
  -bios none \
  -machine microchip-icicle-kit,clint-timebase-frequency=10000000 \
  -kernel rtos.elf

v2:

* Add documentation update.

* In patch 3, warn if no device tree is specified.

* In patch 4, use riscv_find_firmware() to locate the firmware shipped with Qemu.

Sebastian Huber (6):
  hw/misc: Add MPFS system reset support
  hw/riscv: More flexible FDT placement for MPFS
  hw/riscv: Make FDT optional for MPFS
  hw/riscv: Allow direct start of kernel for MPFS
  hw/riscv: Configurable MPFS CLINT timebase freq
  hw/riscv: microchip_pfsoc: Rework documentation

 docs/system/riscv/microchip-icicle-kit.rst | 124 ++++++-----------
 hw/misc/mchp_pfsoc_sysreg.c                |   7 +
 hw/riscv/microchip_pfsoc.c                 | 151 +++++++++++++++------
 include/hw/riscv/microchip_pfsoc.h         |   1 +
 4 files changed, 162 insertions(+), 121 deletions(-)

-- 
2.43.0

[PATCH v2 1/6] hw/misc: Add MPFS system reset support

[Sebastian Huber]

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
 hw/misc/mchp_pfsoc_sysreg.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
index 7876fe0c5b..08196525aa 100644
--- a/hw/misc/mchp_pfsoc_sysreg.c
+++ b/hw/misc/mchp_pfsoc_sysreg.c
@@ -27,7 +27,9 @@
 #include "hw/irq.h"
 #include "hw/sysbus.h"
 #include "hw/misc/mchp_pfsoc_sysreg.h"
+#include "system/runstate.h"
 
+#define MSS_RESET_CR    0x18
 #define ENVM_CR         0xb8
 #define MESSAGE_INT     0x118c
 
@@ -56,6 +58,11 @@ static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
 {
     MchpPfSoCSysregState *s = opaque;
     switch (offset) {
+    case MSS_RESET_CR:
+        if (value == 0xdead) {
+            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+        }
+        break;
     case MESSAGE_INT:
         qemu_irq_lower(s->irq);
         break;
-- 
2.43.0

[PATCH v2 2/6] hw/riscv: More flexible FDT placement for MPFS

[Sebastian Huber]

If the kernel entry is in the high DRAM area, place the FDT into this
area.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/microchip_pfsoc.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 9c846f9b5b..f477d2791e 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -626,8 +626,15 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
         kernel_entry = boot_info.image_low_addr;
 
         /* Compute the fdt load address in dram */
-        fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
-                                               memmap[MICROCHIP_PFSOC_DRAM_LO].size,
+        hwaddr kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
+        hwaddr kernel_ram_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
+
+        if (kernel_entry - kernel_ram_base >= kernel_ram_size) {
+            kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_HI].base;
+            kernel_ram_size = mem_high_size;
+        }
+
+        fdt_load_addr = riscv_compute_fdt_addr(kernel_ram_base, kernel_ram_size,
                                                machine, &boot_info);
         riscv_load_fdt(fdt_load_addr, machine->fdt);
 
-- 
2.43.0

[PATCH v2 3/6] hw/riscv: Make FDT optional for MPFS

[Sebastian Huber]

Real-time kernels such as RTEMS or Zephyr may use a static device tree
built into the kernel image.  Do not require to use the -dtb option if
-kernel is used for the microchip-icicle-kit machine.  Issue a warning
if no device tree is provided by the user since the machine does not
generate one.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
 hw/riscv/microchip_pfsoc.c | 56 +++++++++++++++++++-------------------
 1 file changed, 28 insertions(+), 28 deletions(-)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index f477d2791e..844dc0545c 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -516,7 +516,6 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     uint64_t mem_low_size, mem_high_size;
     hwaddr firmware_load_addr;
     const char *firmware_name;
-    bool kernel_as_payload = false;
     target_ulong firmware_end_addr, kernel_start_addr;
     uint64_t kernel_entry;
     uint64_t fdt_load_addr;
@@ -589,25 +588,12 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
      *
      * This ensures backwards compatibility with how we used to expose -bios
      * to users but allows them to run through direct kernel booting as well.
-     *
-     * When -kernel is used for direct boot, -dtb must be present to provide
-     * a valid device tree for the board, as we don't generate device tree.
      */
 
-    if (machine->kernel_filename && machine->dtb) {
-        int fdt_size;
-        machine->fdt = load_device_tree(machine->dtb, &fdt_size);
-        if (!machine->fdt) {
-            error_report("load_device_tree() failed");
-            exit(1);
-        }
-
+    if (machine->kernel_filename) {
         firmware_name = RISCV64_BIOS_BIN;
         firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
-        kernel_as_payload = true;
-    }
-
-    if (!kernel_as_payload) {
+    } else {
         firmware_name = BIOS_FILENAME;
         firmware_load_addr = RESET_VECTOR;
     }
@@ -617,7 +603,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
                                                      &firmware_load_addr, NULL);
 
     riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
-    if (kernel_as_payload) {
+    if (machine->kernel_filename) {
         kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
                                                          firmware_end_addr);
 
@@ -625,19 +611,33 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
                           true, NULL);
         kernel_entry = boot_info.image_low_addr;
 
-        /* Compute the fdt load address in dram */
-        hwaddr kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
-        hwaddr kernel_ram_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
-
-        if (kernel_entry - kernel_ram_base >= kernel_ram_size) {
-            kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_HI].base;
-            kernel_ram_size = mem_high_size;
+        if (machine->dtb) {
+            int fdt_size;
+            machine->fdt = load_device_tree(machine->dtb, &fdt_size);
+            if (!machine->fdt) {
+                error_report("load_device_tree() failed");
+                exit(1);
+            }
+
+            /* Compute the FDT load address in DRAM */
+            hwaddr kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
+            hwaddr kernel_ram_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
+
+            if (kernel_entry - kernel_ram_base >= kernel_ram_size) {
+                kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_HI].base;
+                kernel_ram_size = mem_high_size;
+            }
+
+            fdt_load_addr = riscv_compute_fdt_addr(kernel_ram_base, kernel_ram_size,
+                                                   machine, &boot_info);
+            riscv_load_fdt(fdt_load_addr, machine->fdt);
+        } else {
+            warn_report_once("The QEMU microchip-icicle-kit machine does not "
+                             "generate a device tree, so no device tree is "
+                             "being provided to the guest.");
+            fdt_load_addr = 0;
         }
 
-        fdt_load_addr = riscv_compute_fdt_addr(kernel_ram_base, kernel_ram_size,
-                                               machine, &boot_info);
-        riscv_load_fdt(fdt_load_addr, machine->fdt);
-
         /* Load the reset vector */
         riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
                                   memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
-- 
2.43.0

[PATCH v2 4/6] hw/riscv: Allow direct start of kernel for MPFS

[Sebastian Huber]

Further customize the -bios and -kernel options behaviour for the
microchip-icicle-kit machine.  If "-bios none -kernel filename" is
specified, then do not load a firmware and instead only load and start
the kernel image.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
 hw/riscv/microchip_pfsoc.c | 57 ++++++++++++++++++++++++++------------
 1 file changed, 40 insertions(+), 17 deletions(-)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 844dc0545c..df902c8667 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -578,29 +578,45 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     }
 
     /*
-     * We follow the following table to select which payload we execute.
+     * We follow the following table to select which firmware we use.
      *
-     *  -bios |    -kernel | payload
-     * -------+------------+--------
-     *      N |          N | HSS
-     *      Y | don't care | HSS
-     *      N |          Y | kernel
-     *
-     * This ensures backwards compatibility with how we used to expose -bios
-     * to users but allows them to run through direct kernel booting as well.
+     * -bios         | -kernel    | firmware
+     * --------------+------------+--------
+     * none          |          N | error
+     * none          |          Y | kernel
+     * NULL, default |          N | BIOS_FILENAME
+     * NULL, default |          Y | RISCV64_BIOS_BIN
+     * other         | don't care | other
      */
+    if (machine->firmware && !strcmp(machine->firmware, "none")) {
+        if (!machine->kernel_filename) {
+            error_report("for -bios none, a kernel is required");
+            exit(1);
+        }
 
-    if (machine->kernel_filename) {
-        firmware_name = RISCV64_BIOS_BIN;
-        firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
+        firmware_name = NULL;
+        firmware_load_addr = RESET_VECTOR;
+    } else if (!machine->firmware || !strcmp(machine->firmware, "default")) {
+        if (machine->kernel_filename) {
+            firmware_name = RISCV64_BIOS_BIN;
+            firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
+        } else {
+            firmware_name = BIOS_FILENAME;
+            firmware_load_addr = RESET_VECTOR;
+        }
     } else {
-        firmware_name = BIOS_FILENAME;
+        firmware_name = machine->firmware;
         firmware_load_addr = RESET_VECTOR;
     }
 
-    /* Load the firmware */
-    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
-                                                     &firmware_load_addr, NULL);
+    /* Load the firmware if necessary */
+    if (firmware_name) {
+        const char *filename = riscv_find_firmware(firmware_name, NULL);
+        firmware_end_addr = riscv_load_firmware(filename, &firmware_load_addr,
+                                                NULL);
+    } else {
+        firmware_end_addr = firmware_load_addr;
+    }
 
     riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
     if (machine->kernel_filename) {
@@ -638,8 +654,15 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
             fdt_load_addr = 0;
         }
 
+        hwaddr start_addr;
+        if (firmware_name) {
+            start_addr = firmware_load_addr;
+        } else {
+            start_addr = kernel_entry;
+        }
+
         /* Load the reset vector */
-        riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
+        riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, start_addr,
                                   memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
                                   memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
                                   kernel_entry, fdt_load_addr);
-- 
2.43.0

[PATCH v2 5/6] hw/riscv: Configurable MPFS CLINT timebase freq

[Sebastian Huber]

This property enables the setting of the CLINT timebase frequency
through the command line, for example:

  -machine microchip-icicle-kit,clint-timebase-frequency=10000000

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/riscv/microchip_pfsoc.c         | 49 +++++++++++++++++++++++++++---
 include/hw/riscv/microchip_pfsoc.h |  1 +
 2 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index df902c8667..9068eed780 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -39,6 +39,7 @@
 #include "qemu/units.h"
 #include "qemu/cutils.h"
 #include "qapi/error.h"
+#include "qapi/visitor.h"
 #include "hw/boards.h"
 #include "hw/loader.h"
 #include "hw/sysbus.h"
@@ -61,9 +62,6 @@
 #define BIOS_FILENAME   "hss.bin"
 #define RESET_VECTOR    0x20220000
 
-/* CLINT timebase frequency */
-#define CLINT_TIMEBASE_FREQ 1000000
-
 /* GEM version */
 #define GEM_REVISION    0x0107010c
 
@@ -193,6 +191,7 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
 {
     MachineState *ms = MACHINE(qdev_get_machine());
+    MicrochipIcicleKitState *iks = MICROCHIP_ICICLE_KIT_MACHINE(ms);
     MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
     const MemMapEntry *memmap = microchip_pfsoc_memmap;
     MemoryRegion *system_memory = get_system_memory();
@@ -253,7 +252,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE,
         RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
         RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
-        CLINT_TIMEBASE_FREQ, false);
+        iks->clint_timebase_freq, false);
 
     /* L2 cache controller */
     create_unimplemented_device("microchip.pfsoc.l2cc",
@@ -669,6 +668,40 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     }
 }
 
+static void microchip_icicle_kit_set_clint_timebase_freq(Object *obj,
+                                                         Visitor *v,
+                                                         const char *name,
+                                                         void *opaque,
+                                                         Error **errp)
+{
+    MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(obj);
+    uint32_t value;
+
+    if (!visit_type_uint32(v, name, &value, errp)) {
+        return;
+    }
+
+    s->clint_timebase_freq = value;
+}
+
+static void microchip_icicle_kit_get_clint_timebase_freq(Object *obj,
+                                                         Visitor *v,
+                                                         const char *name,
+                                                         void *opaque,
+                                                         Error **errp)
+{
+    MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(obj);
+    uint32_t value = s->clint_timebase_freq;
+
+    visit_type_uint32(v, name, &value, errp);
+}
+
+static void microchip_icicle_kit_machine_instance_init(Object *obj)
+{
+    MicrochipIcicleKitState *m = MICROCHIP_ICICLE_KIT_MACHINE(obj);
+    m->clint_timebase_freq = 1000000;
+}
+
 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -690,12 +723,20 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
      * See memory_tests() in mss_ddr.c in the HSS source code.
      */
     mc->default_ram_size = 1537 * MiB;
+
+    object_class_property_add(oc, "clint-timebase-frequency", "uint32_t",
+                              microchip_icicle_kit_get_clint_timebase_freq,
+                              microchip_icicle_kit_set_clint_timebase_freq,
+                              NULL, NULL);
+    object_class_property_set_description(oc, "clint-timebase-frequency",
+                                  "Set CLINT timebase frequency in Hz.");
 }
 
 static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
     .name       = MACHINE_TYPE_NAME("microchip-icicle-kit"),
     .parent     = TYPE_MACHINE,
     .class_init = microchip_icicle_kit_machine_class_init,
+    .instance_init = microchip_icicle_kit_machine_instance_init,
     .instance_size = sizeof(MicrochipIcicleKitState),
 };
 
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index daef086da6..7ca9b976c1 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -67,6 +67,7 @@ typedef struct MicrochipIcicleKitState {
     MachineState parent_obj;
 
     /*< public >*/
+    uint32_t clint_timebase_freq;
     MicrochipPFSoCState soc;
 } MicrochipIcicleKitState;
 
-- 
2.43.0

[PATCH v2 6/6] hw/riscv: microchip_pfsoc: Rework documentation

[Sebastian Huber]

Mention that running the HSS no longer works.  Document the changed boot
options.  Reorder documentation blocks.  Update URLs.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
---
 docs/system/riscv/microchip-icicle-kit.rst | 124 +++++++--------------
 1 file changed, 43 insertions(+), 81 deletions(-)

diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
index 40798b1aae..9809e94b84 100644
--- a/docs/system/riscv/microchip-icicle-kit.rst
+++ b/docs/system/riscv/microchip-icicle-kit.rst
@@ -5,10 +5,10 @@ Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
 SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
 
 For more details about Microchip PolarFire SoC, please see:
-https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
+https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpgas/polarfire-soc-fpgas
 
 The Icicle Kit board information can be found here:
-https://www.microsemi.com/existing-parts/parts/152514
+https://www.microchip.com/en-us/development-tool/mpfs-icicle-kit-es
 
 Supported devices
 -----------------
@@ -26,95 +26,48 @@ The ``microchip-icicle-kit`` machine supports the following devices:
 * 2 GEM Ethernet controllers
 * 1 SDHC storage controller
 
+The memory is set to 1537 MiB by default.  A sanity check on RAM size is
+performed in the machine init routine to prompt user to increase the RAM size
+to > 1537 MiB when less than 1537 MiB RAM is detected.
+
 Boot options
 ------------
 
-The ``microchip-icicle-kit`` machine can start using the standard -bios
-functionality for loading its BIOS image, aka Hart Software Services (HSS_).
-HSS loads the second stage bootloader U-Boot from an SD card. Then a kernel
-can be loaded from U-Boot. It also supports direct kernel booting via the
--kernel option along with the device tree blob via -dtb. When direct kernel
-boot is used, the OpenSBI fw_dynamic BIOS image is used to boot a payload
-like U-Boot or OS kernel directly.
-
-The user provided DTB should have the following requirements:
-
-* The /cpus node should contain at least one subnode for E51 and the number
-  of subnodes should match QEMU's ``-smp`` option
-* The /memory reg size should match QEMU’s selected ram_size via ``-m``
-* Should contain a node for the CLINT device with a compatible string
-  "riscv,clint0"
-
-QEMU follows below truth table to select which payload to execute:
-
-===== ========== ========== =======
--bios    -kernel       -dtb payload
-===== ========== ========== =======
-    N          N don't care     HSS
-    Y don't care don't care     HSS
-    N          Y          Y  kernel
-===== ========== ========== =======
-
-The memory is set to 1537 MiB by default which is the minimum required high
-memory size by HSS. A sanity check on ram size is performed in the machine
-init routine to prompt user to increase the RAM size to > 1537 MiB when less
-than 1537 MiB ram is detected.
-
-Running HSS
------------
-
-HSS 2020.12 release is tested at the time of writing. To build an HSS image
-that can be booted by the ``microchip-icicle-kit`` machine, type the following
-in the HSS source tree:
-
-.. code-block:: bash
-
-  $ export CROSS_COMPILE=riscv64-linux-
-  $ cp boards/mpfs-icicle-kit-es/def_config .config
-  $ make BOARD=mpfs-icicle-kit-es
-
-Download the official SD card image released by Microchip and prepare it for
-QEMU usage:
-
-.. code-block:: bash
-
-  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
-  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
-  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
-
-Then we can boot the machine by:
-
-.. code-block:: bash
-
-  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
-      -bios path/to/hss.bin -sd path/to/sdcard.img \
-      -nic user,model=cadence_gem \
-      -nic tap,ifname=tap,model=cadence_gem,script=no \
-      -display none -serial stdio \
-      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
-      -serial chardev:serial1
+The ``microchip-icicle-kit`` machine provides some options to run a firmware
+(BIOS) or a kernel image.  QEMU follows below truth table to select the
+firmware:
 
-With above command line, current terminal session will be used for the first
-serial port. Open another terminal window, and use ``minicom`` to connect the
-second serial port.
+============= =========== ======================================
+-bios          -kernel    firmware
+============= =========== ======================================
+none                    N this is an error
+none                    Y the kernel image
+NULL, default           N hss.bin
+NULL, default           Y opensbi-riscv64-generic-fw_dynamic.bin
+other          don't care the BIOS image
+============= =========== ======================================
 
-.. code-block:: bash
+Direct Kernel Boot
+------------------
 
-  $ minicom -D unix\#serial1.sock
+Use the ``-kernel`` option to directly run a kernel image.  When a direct
+kernel boot is requested, a device tree blob may be specified via the ``-dtb``
+option.  Unlike other QEMU machines, this machine does not generate a device
+tree for the kernel.  It shall be provided by the user.  The user provided DTB
+should meet the following requirements:
 
-HSS output is on the first serial port (stdio) and U-Boot outputs on the
-second serial port. U-Boot will automatically load the Linux kernel from
-the SD card image.
+* The ``/cpus`` node should contain at least one subnode for E51 and the number
+  of subnodes should match QEMU's ``-smp`` option.
 
-Direct Kernel Boot
-------------------
+* The ``/memory`` reg size should match QEMU’s selected RAM size via the ``-m``
+  option.
 
-Sometimes we just want to test booting a new kernel, and transforming the
-kernel image to the format required by the HSS bootflow is tedious. We can
-use '-kernel' for direct kernel booting just like other RISC-V machines do.
+* It should contain a node for the CLINT device with a compatible string
+  "riscv,clint0".
 
-In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is
-used to boot an S-mode payload like U-Boot or OS kernel directly.
+When ``-bios`` is not specified or set to ``default``, the OpenSBI
+``fw_dynamic`` BIOS image for the ``generic`` platform is used to boot an
+S-mode payload like U-Boot or OS kernel directly.
 
 For example, the following commands show building a U-Boot image from U-Boot
 mainline v2021.07 for the Microchip Icicle Kit board:
@@ -146,4 +99,13 @@ CAVEATS:
   ``u-boot.bin`` has to be used which does contain one. To use the ELF image,
   we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE.
 
+Running HSS
+-----------
+
+The machine ``microchip-icicle-kit`` used to run the Hart Software Services
+(HSS_), however, the HSS development progressed and the QEMU machine
+implementation lacks behind.  Currently, running the HSS no longer works.
+There is missing support in the clock and memory controller devices.  In
+particular, reading from the SD card does not work.
+
 .. _HSS: https://github.com/polarfire-soc/hart-software-services
-- 
2.43.0

Re: [PATCH v2 1/6] hw/misc: Add MPFS system reset support

[Alistair Francis]

On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
>
> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/misc/mchp_pfsoc_sysreg.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
> index 7876fe0c5b..08196525aa 100644
> --- a/hw/misc/mchp_pfsoc_sysreg.c
> +++ b/hw/misc/mchp_pfsoc_sysreg.c
> @@ -27,7 +27,9 @@
>  #include "hw/irq.h"
>  #include "hw/sysbus.h"
>  #include "hw/misc/mchp_pfsoc_sysreg.h"
> +#include "system/runstate.h"
>
> +#define MSS_RESET_CR    0x18
>  #define ENVM_CR         0xb8
>  #define MESSAGE_INT     0x118c
>
> @@ -56,6 +58,11 @@ static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
>  {
>      MchpPfSoCSysregState *s = opaque;
>      switch (offset) {
> +    case MSS_RESET_CR:
> +        if (value == 0xdead) {
> +            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> +        }
> +        break;
>      case MESSAGE_INT:
>          qemu_irq_lower(s->irq);
>          break;
> --
> 2.43.0
>

Re: [PATCH v2 3/6] hw/riscv: Make FDT optional for MPFS

[Alistair Francis]

On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
>
> Real-time kernels such as RTEMS or Zephyr may use a static device tree
> built into the kernel image.  Do not require to use the -dtb option if
> -kernel is used for the microchip-icicle-kit machine.  Issue a warning
> if no device tree is provided by the user since the machine does not
> generate one.
>
> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/microchip_pfsoc.c | 56 +++++++++++++++++++-------------------
>  1 file changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index f477d2791e..844dc0545c 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -516,7 +516,6 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>      uint64_t mem_low_size, mem_high_size;
>      hwaddr firmware_load_addr;
>      const char *firmware_name;
> -    bool kernel_as_payload = false;
>      target_ulong firmware_end_addr, kernel_start_addr;
>      uint64_t kernel_entry;
>      uint64_t fdt_load_addr;
> @@ -589,25 +588,12 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>       *
>       * This ensures backwards compatibility with how we used to expose -bios
>       * to users but allows them to run through direct kernel booting as well.
> -     *
> -     * When -kernel is used for direct boot, -dtb must be present to provide
> -     * a valid device tree for the board, as we don't generate device tree.
>       */
>
> -    if (machine->kernel_filename && machine->dtb) {
> -        int fdt_size;
> -        machine->fdt = load_device_tree(machine->dtb, &fdt_size);
> -        if (!machine->fdt) {
> -            error_report("load_device_tree() failed");
> -            exit(1);
> -        }
> -
> +    if (machine->kernel_filename) {
>          firmware_name = RISCV64_BIOS_BIN;
>          firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
> -        kernel_as_payload = true;
> -    }
> -
> -    if (!kernel_as_payload) {
> +    } else {
>          firmware_name = BIOS_FILENAME;
>          firmware_load_addr = RESET_VECTOR;
>      }
> @@ -617,7 +603,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>                                                       &firmware_load_addr, NULL);
>
>      riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
> -    if (kernel_as_payload) {
> +    if (machine->kernel_filename) {
>          kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
>                                                           firmware_end_addr);
>
> @@ -625,19 +611,33 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>                            true, NULL);
>          kernel_entry = boot_info.image_low_addr;
>
> -        /* Compute the fdt load address in dram */
> -        hwaddr kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
> -        hwaddr kernel_ram_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
> -
> -        if (kernel_entry - kernel_ram_base >= kernel_ram_size) {
> -            kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_HI].base;
> -            kernel_ram_size = mem_high_size;
> +        if (machine->dtb) {
> +            int fdt_size;
> +            machine->fdt = load_device_tree(machine->dtb, &fdt_size);
> +            if (!machine->fdt) {
> +                error_report("load_device_tree() failed");
> +                exit(1);
> +            }
> +
> +            /* Compute the FDT load address in DRAM */
> +            hwaddr kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
> +            hwaddr kernel_ram_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
> +
> +            if (kernel_entry - kernel_ram_base >= kernel_ram_size) {
> +                kernel_ram_base = memmap[MICROCHIP_PFSOC_DRAM_HI].base;
> +                kernel_ram_size = mem_high_size;
> +            }
> +
> +            fdt_load_addr = riscv_compute_fdt_addr(kernel_ram_base, kernel_ram_size,
> +                                                   machine, &boot_info);
> +            riscv_load_fdt(fdt_load_addr, machine->fdt);
> +        } else {
> +            warn_report_once("The QEMU microchip-icicle-kit machine does not "
> +                             "generate a device tree, so no device tree is "
> +                             "being provided to the guest.");
> +            fdt_load_addr = 0;
>          }
>
> -        fdt_load_addr = riscv_compute_fdt_addr(kernel_ram_base, kernel_ram_size,
> -                                               machine, &boot_info);
> -        riscv_load_fdt(fdt_load_addr, machine->fdt);
> -
>          /* Load the reset vector */
>          riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
>                                    memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
> --
> 2.43.0
>

Re: [PATCH v2 4/6] hw/riscv: Allow direct start of kernel for MPFS

[Alistair Francis]

On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
>
> Further customize the -bios and -kernel options behaviour for the
> microchip-icicle-kit machine.  If "-bios none -kernel filename" is
> specified, then do not load a firmware and instead only load and start
> the kernel image.
>
> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/microchip_pfsoc.c | 57 ++++++++++++++++++++++++++------------
>  1 file changed, 40 insertions(+), 17 deletions(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 844dc0545c..df902c8667 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -578,29 +578,45 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>      }
>
>      /*
> -     * We follow the following table to select which payload we execute.
> +     * We follow the following table to select which firmware we use.
>       *
> -     *  -bios |    -kernel | payload
> -     * -------+------------+--------
> -     *      N |          N | HSS
> -     *      Y | don't care | HSS
> -     *      N |          Y | kernel
> -     *
> -     * This ensures backwards compatibility with how we used to expose -bios
> -     * to users but allows them to run through direct kernel booting as well.
> +     * -bios         | -kernel    | firmware
> +     * --------------+------------+--------
> +     * none          |          N | error
> +     * none          |          Y | kernel
> +     * NULL, default |          N | BIOS_FILENAME
> +     * NULL, default |          Y | RISCV64_BIOS_BIN
> +     * other         | don't care | other
>       */
> +    if (machine->firmware && !strcmp(machine->firmware, "none")) {
> +        if (!machine->kernel_filename) {
> +            error_report("for -bios none, a kernel is required");
> +            exit(1);
> +        }
>
> -    if (machine->kernel_filename) {
> -        firmware_name = RISCV64_BIOS_BIN;
> -        firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
> +        firmware_name = NULL;
> +        firmware_load_addr = RESET_VECTOR;
> +    } else if (!machine->firmware || !strcmp(machine->firmware, "default")) {
> +        if (machine->kernel_filename) {
> +            firmware_name = RISCV64_BIOS_BIN;
> +            firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
> +        } else {
> +            firmware_name = BIOS_FILENAME;
> +            firmware_load_addr = RESET_VECTOR;
> +        }
>      } else {
> -        firmware_name = BIOS_FILENAME;
> +        firmware_name = machine->firmware;
>          firmware_load_addr = RESET_VECTOR;
>      }
>
> -    /* Load the firmware */
> -    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
> -                                                     &firmware_load_addr, NULL);
> +    /* Load the firmware if necessary */
> +    if (firmware_name) {
> +        const char *filename = riscv_find_firmware(firmware_name, NULL);
> +        firmware_end_addr = riscv_load_firmware(filename, &firmware_load_addr,
> +                                                NULL);
> +    } else {
> +        firmware_end_addr = firmware_load_addr;
> +    }
>
>      riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
>      if (machine->kernel_filename) {
> @@ -638,8 +654,15 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>              fdt_load_addr = 0;
>          }
>
> +        hwaddr start_addr;
> +        if (firmware_name) {
> +            start_addr = firmware_load_addr;
> +        } else {
> +            start_addr = kernel_entry;
> +        }
> +
>          /* Load the reset vector */
> -        riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
> +        riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, start_addr,
>                                    memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
>                                    memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
>                                    kernel_entry, fdt_load_addr);
> --
> 2.43.0
>

Re: [PATCH v2 5/6] hw/riscv: Configurable MPFS CLINT timebase freq

[Alistair Francis]

On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
>
> This property enables the setting of the CLINT timebase frequency
> through the command line, for example:
>
>   -machine microchip-icicle-kit,clint-timebase-frequency=10000000
>
> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/microchip_pfsoc.c         | 49 +++++++++++++++++++++++++++---
>  include/hw/riscv/microchip_pfsoc.h |  1 +
>  2 files changed, 46 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index df902c8667..9068eed780 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -39,6 +39,7 @@
>  #include "qemu/units.h"
>  #include "qemu/cutils.h"
>  #include "qapi/error.h"
> +#include "qapi/visitor.h"
>  #include "hw/boards.h"
>  #include "hw/loader.h"
>  #include "hw/sysbus.h"
> @@ -61,9 +62,6 @@
>  #define BIOS_FILENAME   "hss.bin"
>  #define RESET_VECTOR    0x20220000
>
> -/* CLINT timebase frequency */
> -#define CLINT_TIMEBASE_FREQ 1000000
> -
>  /* GEM version */
>  #define GEM_REVISION    0x0107010c
>
> @@ -193,6 +191,7 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
>  static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
>  {
>      MachineState *ms = MACHINE(qdev_get_machine());
> +    MicrochipIcicleKitState *iks = MICROCHIP_ICICLE_KIT_MACHINE(ms);
>      MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
>      const MemMapEntry *memmap = microchip_pfsoc_memmap;
>      MemoryRegion *system_memory = get_system_memory();
> @@ -253,7 +252,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
>          memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE,
>          RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
>          RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
> -        CLINT_TIMEBASE_FREQ, false);
> +        iks->clint_timebase_freq, false);
>
>      /* L2 cache controller */
>      create_unimplemented_device("microchip.pfsoc.l2cc",
> @@ -669,6 +668,40 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>      }
>  }
>
> +static void microchip_icicle_kit_set_clint_timebase_freq(Object *obj,
> +                                                         Visitor *v,
> +                                                         const char *name,
> +                                                         void *opaque,
> +                                                         Error **errp)
> +{
> +    MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(obj);
> +    uint32_t value;
> +
> +    if (!visit_type_uint32(v, name, &value, errp)) {
> +        return;
> +    }
> +
> +    s->clint_timebase_freq = value;
> +}
> +
> +static void microchip_icicle_kit_get_clint_timebase_freq(Object *obj,
> +                                                         Visitor *v,
> +                                                         const char *name,
> +                                                         void *opaque,
> +                                                         Error **errp)
> +{
> +    MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(obj);
> +    uint32_t value = s->clint_timebase_freq;
> +
> +    visit_type_uint32(v, name, &value, errp);
> +}
> +
> +static void microchip_icicle_kit_machine_instance_init(Object *obj)
> +{
> +    MicrochipIcicleKitState *m = MICROCHIP_ICICLE_KIT_MACHINE(obj);
> +    m->clint_timebase_freq = 1000000;
> +}
> +
>  static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
>  {
>      MachineClass *mc = MACHINE_CLASS(oc);
> @@ -690,12 +723,20 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
>       * See memory_tests() in mss_ddr.c in the HSS source code.
>       */
>      mc->default_ram_size = 1537 * MiB;
> +
> +    object_class_property_add(oc, "clint-timebase-frequency", "uint32_t",
> +                              microchip_icicle_kit_get_clint_timebase_freq,
> +                              microchip_icicle_kit_set_clint_timebase_freq,
> +                              NULL, NULL);
> +    object_class_property_set_description(oc, "clint-timebase-frequency",
> +                                  "Set CLINT timebase frequency in Hz.");
>  }
>
>  static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
>      .name       = MACHINE_TYPE_NAME("microchip-icicle-kit"),
>      .parent     = TYPE_MACHINE,
>      .class_init = microchip_icicle_kit_machine_class_init,
> +    .instance_init = microchip_icicle_kit_machine_instance_init,
>      .instance_size = sizeof(MicrochipIcicleKitState),
>  };
>
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index daef086da6..7ca9b976c1 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -67,6 +67,7 @@ typedef struct MicrochipIcicleKitState {
>      MachineState parent_obj;
>
>      /*< public >*/
> +    uint32_t clint_timebase_freq;
>      MicrochipPFSoCState soc;
>  } MicrochipIcicleKitState;
>
> --
> 2.43.0
>

Re: [PATCH v2 6/6] hw/riscv: microchip_pfsoc: Rework documentation

[Alistair Francis]

On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
>
> Mention that running the HSS no longer works.  Document the changed boot
> options.  Reorder documentation blocks.  Update URLs.
>
> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  docs/system/riscv/microchip-icicle-kit.rst | 124 +++++++--------------
>  1 file changed, 43 insertions(+), 81 deletions(-)
>
> diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
> index 40798b1aae..9809e94b84 100644
> --- a/docs/system/riscv/microchip-icicle-kit.rst
> +++ b/docs/system/riscv/microchip-icicle-kit.rst
> @@ -5,10 +5,10 @@ Microchip PolarFire SoC Icicle Kit integrates a PolarFire SoC, with one
>  SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
>
>  For more details about Microchip PolarFire SoC, please see:
> -https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
> +https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpgas/polarfire-soc-fpgas
>
>  The Icicle Kit board information can be found here:
> -https://www.microsemi.com/existing-parts/parts/152514
> +https://www.microchip.com/en-us/development-tool/mpfs-icicle-kit-es
>
>  Supported devices
>  -----------------
> @@ -26,95 +26,48 @@ The ``microchip-icicle-kit`` machine supports the following devices:
>  * 2 GEM Ethernet controllers
>  * 1 SDHC storage controller
>
> +The memory is set to 1537 MiB by default.  A sanity check on RAM size is
> +performed in the machine init routine to prompt user to increase the RAM size
> +to > 1537 MiB when less than 1537 MiB RAM is detected.
> +
>  Boot options
>  ------------
>
> -The ``microchip-icicle-kit`` machine can start using the standard -bios
> -functionality for loading its BIOS image, aka Hart Software Services (HSS_).
> -HSS loads the second stage bootloader U-Boot from an SD card. Then a kernel
> -can be loaded from U-Boot. It also supports direct kernel booting via the
> --kernel option along with the device tree blob via -dtb. When direct kernel
> -boot is used, the OpenSBI fw_dynamic BIOS image is used to boot a payload
> -like U-Boot or OS kernel directly.
> -
> -The user provided DTB should have the following requirements:
> -
> -* The /cpus node should contain at least one subnode for E51 and the number
> -  of subnodes should match QEMU's ``-smp`` option
> -* The /memory reg size should match QEMU’s selected ram_size via ``-m``
> -* Should contain a node for the CLINT device with a compatible string
> -  "riscv,clint0"
> -
> -QEMU follows below truth table to select which payload to execute:
> -
> -===== ========== ========== =======
> --bios    -kernel       -dtb payload
> -===== ========== ========== =======
> -    N          N don't care     HSS
> -    Y don't care don't care     HSS
> -    N          Y          Y  kernel
> -===== ========== ========== =======
> -
> -The memory is set to 1537 MiB by default which is the minimum required high
> -memory size by HSS. A sanity check on ram size is performed in the machine
> -init routine to prompt user to increase the RAM size to > 1537 MiB when less
> -than 1537 MiB ram is detected.
> -
> -Running HSS
> ------------
> -
> -HSS 2020.12 release is tested at the time of writing. To build an HSS image
> -that can be booted by the ``microchip-icicle-kit`` machine, type the following
> -in the HSS source tree:
> -
> -.. code-block:: bash
> -
> -  $ export CROSS_COMPILE=riscv64-linux-
> -  $ cp boards/mpfs-icicle-kit-es/def_config .config
> -  $ make BOARD=mpfs-icicle-kit-es
> -
> -Download the official SD card image released by Microchip and prepare it for
> -QEMU usage:
> -
> -.. code-block:: bash
> -
> -  $ wget ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
> -  $ gunzip core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
> -  $ qemu-img resize core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic 4G
> -
> -Then we can boot the machine by:
> -
> -.. code-block:: bash
> -
> -  $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
> -      -bios path/to/hss.bin -sd path/to/sdcard.img \
> -      -nic user,model=cadence_gem \
> -      -nic tap,ifname=tap,model=cadence_gem,script=no \
> -      -display none -serial stdio \
> -      -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \
> -      -serial chardev:serial1
> +The ``microchip-icicle-kit`` machine provides some options to run a firmware
> +(BIOS) or a kernel image.  QEMU follows below truth table to select the
> +firmware:
>
> -With above command line, current terminal session will be used for the first
> -serial port. Open another terminal window, and use ``minicom`` to connect the
> -second serial port.
> +============= =========== ======================================
> +-bios          -kernel    firmware
> +============= =========== ======================================
> +none                    N this is an error
> +none                    Y the kernel image
> +NULL, default           N hss.bin
> +NULL, default           Y opensbi-riscv64-generic-fw_dynamic.bin
> +other          don't care the BIOS image
> +============= =========== ======================================
>
> -.. code-block:: bash
> +Direct Kernel Boot
> +------------------
>
> -  $ minicom -D unix\#serial1.sock
> +Use the ``-kernel`` option to directly run a kernel image.  When a direct
> +kernel boot is requested, a device tree blob may be specified via the ``-dtb``
> +option.  Unlike other QEMU machines, this machine does not generate a device
> +tree for the kernel.  It shall be provided by the user.  The user provided DTB
> +should meet the following requirements:
>
> -HSS output is on the first serial port (stdio) and U-Boot outputs on the
> -second serial port. U-Boot will automatically load the Linux kernel from
> -the SD card image.
> +* The ``/cpus`` node should contain at least one subnode for E51 and the number
> +  of subnodes should match QEMU's ``-smp`` option.
>
> -Direct Kernel Boot
> -------------------
> +* The ``/memory`` reg size should match QEMU’s selected RAM size via the ``-m``
> +  option.
>
> -Sometimes we just want to test booting a new kernel, and transforming the
> -kernel image to the format required by the HSS bootflow is tedious. We can
> -use '-kernel' for direct kernel booting just like other RISC-V machines do.
> +* It should contain a node for the CLINT device with a compatible string
> +  "riscv,clint0".
>
> -In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is
> -used to boot an S-mode payload like U-Boot or OS kernel directly.
> +When ``-bios`` is not specified or set to ``default``, the OpenSBI
> +``fw_dynamic`` BIOS image for the ``generic`` platform is used to boot an
> +S-mode payload like U-Boot or OS kernel directly.
>
>  For example, the following commands show building a U-Boot image from U-Boot
>  mainline v2021.07 for the Microchip Icicle Kit board:
> @@ -146,4 +99,13 @@ CAVEATS:
>    ``u-boot.bin`` has to be used which does contain one. To use the ELF image,
>    we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE.
>
> +Running HSS
> +-----------
> +
> +The machine ``microchip-icicle-kit`` used to run the Hart Software Services
> +(HSS_), however, the HSS development progressed and the QEMU machine
> +implementation lacks behind.  Currently, running the HSS no longer works.
> +There is missing support in the clock and memory controller devices.  In
> +particular, reading from the SD card does not work.
> +
>  .. _HSS: https://github.com/polarfire-soc/hart-software-services
> --
> 2.43.0
>

Re: [PATCH v2 0/6] Improve Microchip Polarfire SoC customization

[Alistair Francis]

On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
>
> Booting the microchip-icicle-kit machine using the latest PolarFire SoC
> Hart Software Services (HSS) no longer works since Qemu lacks support
> for several registers (clocks, DRAM controller). Also reading from the
> SDCard does not work currently.
>
> In order to allow tests runs for real-time kernels such as RTEMS and
> Zephyr, improve the boot customization. This patch set enables a direct
> run of kernel executables, for example:
>
> qemu-system-riscv64 -no-reboot -nographic \
>   -serial null -serial mon:stdio \
>   -smp 2 \
>   -bios none \
>   -machine microchip-icicle-kit,clint-timebase-frequency=10000000 \
>   -kernel rtos.elf
>
> v2:
>
> * Add documentation update.
>
> * In patch 3, warn if no device tree is specified.
>
> * In patch 4, use riscv_find_firmware() to locate the firmware shipped with Qemu.
>
> Sebastian Huber (6):
>   hw/misc: Add MPFS system reset support
>   hw/riscv: More flexible FDT placement for MPFS
>   hw/riscv: Make FDT optional for MPFS
>   hw/riscv: Allow direct start of kernel for MPFS
>   hw/riscv: Configurable MPFS CLINT timebase freq
>   hw/riscv: microchip_pfsoc: Rework documentation

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  docs/system/riscv/microchip-icicle-kit.rst | 124 ++++++-----------
>  hw/misc/mchp_pfsoc_sysreg.c                |   7 +
>  hw/riscv/microchip_pfsoc.c                 | 151 +++++++++++++++------
>  include/hw/riscv/microchip_pfsoc.h         |   1 +
>  4 files changed, 162 insertions(+), 121 deletions(-)
>
> --
> 2.43.0
>

Re: [PATCH v2 4/6] hw/riscv: Allow direct start of kernel for MPFS

[Daniel Henrique Barboza]

Hi,

On 2/24/25 9:54 PM, Sebastian Huber wrote:
> Further customize the -bios and -kernel options behaviour for the
> microchip-icicle-kit machine.  If "-bios none -kernel filename" is
> specified, then do not load a firmware and instead only load and start
> the kernel image.
> 
> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
> ---
>   hw/riscv/microchip_pfsoc.c | 57 ++++++++++++++++++++++++++------------
>   1 file changed, 40 insertions(+), 17 deletions(-)
> 
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 844dc0545c..df902c8667 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -578,29 +578,45 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>       }
>   
>       /*
> -     * We follow the following table to select which payload we execute.
> +     * We follow the following table to select which firmware we use.
>        *
> -     *  -bios |    -kernel | payload
> -     * -------+------------+--------
> -     *      N |          N | HSS
> -     *      Y | don't care | HSS
> -     *      N |          Y | kernel
> -     *
> -     * This ensures backwards compatibility with how we used to expose -bios
> -     * to users but allows them to run through direct kernel booting as well.
> +     * -bios         | -kernel    | firmware
> +     * --------------+------------+--------
> +     * none          |          N | error
> +     * none          |          Y | kernel
> +     * NULL, default |          N | BIOS_FILENAME


This change is breaking the following test:

---------

$ QTEST_QEMU_BINARY=./build/qemu-system-riscv64 ./build/tests/qtest/qom-test
(...)
# slow test /riscv64/qom/amd-microblaze-v-generic executed in 2.28 secs
# starting QEMU: exec ./build/qemu-system-riscv64 -qtest unix:/tmp/qtest-1361875.sock -qtest-log /dev/null -chardev socket,path=/tmp/qtest-1361875.qmp,id=char0 -mon chardev=char0,mode=control -display none -audio none -machine microchip-icicle-kit -accel qtest
**
ERROR:../hw/riscv/boot.c:164:riscv_load_firmware: assertion failed: (firmware_filename != NULL)
Bail out! ERROR:../hw/riscv/boot.c:164:riscv_load_firmware: assertion failed: (firmware_filename != NULL)
Broken pipe

---------

The reason is that, with the default machine settings (no -bios and no -kernel
options), firmware_name is now defaulted to BIOS_FILENAME (hss.bin). But we're not
distributing 'hss.bin' in pc-bios:

$ ls pc-bios/ |  grep hss
$

Then, in the following code, 'filename' will be NULL and riscv_load_firmware() will
g_assert():


> +    if (firmware_name) {
> +        const char *filename = riscv_find_firmware(firmware_name, NULL);
> +        firmware_end_addr = riscv_load_firmware(filename, &firmware_load_addr,
> +                                                NULL);
> +    }


Possible solutions:

- package hss.bin in QEMU so it can be used as a default firmware;

- redo the logic to allow the board to run (even if inactive) with absent
-bios and -kernel to allow QEMU model tests to run.



Thanks,

Daniel

> +     * NULL, default |          Y | RISCV64_BIOS_BIN
> +     * other         | don't care | other
>        */
> +    if (machine->firmware && !strcmp(machine->firmware, "none")) {
> +        if (!machine->kernel_filename) {
> +            error_report("for -bios none, a kernel is required");
> +            exit(1);
> +        }
>   
> -    if (machine->kernel_filename) {
> -        firmware_name = RISCV64_BIOS_BIN;
> -        firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
> +        firmware_name = NULL;
> +        firmware_load_addr = RESET_VECTOR;
> +    } else if (!machine->firmware || !strcmp(machine->firmware, "default")) {
> +        if (machine->kernel_filename) {
> +            firmware_name = RISCV64_BIOS_BIN;
> +            firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
> +        } else {
> +            firmware_name = BIOS_FILENAME;
> +            firmware_load_addr = RESET_VECTOR;
> +        }
>       } else {
> -        firmware_name = BIOS_FILENAME;
> +        firmware_name = machine->firmware;
>           firmware_load_addr = RESET_VECTOR;
>       }
>   
> -    /* Load the firmware */
> -    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
> -                                                     &firmware_load_addr, NULL);
> +    /* Load the firmware if necessary */
> +    if (firmware_name) {
> +        const char *filename = riscv_find_firmware(firmware_name, NULL);
> +        firmware_end_addr = riscv_load_firmware(filename, &firmware_load_addr,
> +                                                NULL);
> +    } else {
> +        firmware_end_addr = firmware_load_addr;
> +    }
>   
>       riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
>       if (machine->kernel_filename) {
> @@ -638,8 +654,15 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
>               fdt_load_addr = 0;
>           }
>   
> +        hwaddr start_addr;
> +        if (firmware_name) {
> +            start_addr = firmware_load_addr;
> +        } else {
> +            start_addr = kernel_entry;
> +        }
> +
>           /* Load the reset vector */
> -        riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
> +        riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, start_addr,
>                                     memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
>                                     memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
>                                     kernel_entry, fdt_load_addr);