From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "jasowang@redhat.com" <jasowang@redhat.com>,
"zhenzhong.duan@intel.com" <zhenzhong.duan@intel.com>,
"kevin.tian@intel.com" <kevin.tian@intel.com>,
"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
"peterx@redhat.com" <peterx@redhat.com>,
"mst@redhat.com" <mst@redhat.com>,
"tjeznach@rivosinc.com" <tjeznach@rivosinc.com>,
"minwoo.im@samsung.com" <minwoo.im@samsung.com>,
CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
Subject: [PATCH v4 01/19] memory: Add permissions in IOMMUAccessFlags
Date: Thu, 27 Feb 2025 10:54:38 +0000 [thread overview]
Message-ID: <20250227105339.388598-2-clement.mathieu--drif@eviden.com> (raw)
In-Reply-To: <20250227105339.388598-1-clement.mathieu--drif@eviden.com>
From: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
This will be necessary for devices implementing ATS.
We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to
IOMMU_ACCESS_FLAG to support more access flags.
IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility.
Here are the flags added (defined by the PCIe 5 specification) :
- Execute Requested
- Privileged Mode Requested
- Global
- Untranslated Only
IOMMU_ACCESS_FLAG sets the additional flags to 0
Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
---
include/exec/memory.h | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 78c4e0aec8..29f5d31eef 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -110,15 +110,34 @@ struct MemoryRegionSection {
typedef struct IOMMUTLBEntry IOMMUTLBEntry;
-/* See address_space_translate: bit 0 is read, bit 1 is write. */
+/*
+ * See address_space_translate:
+ * - bit 0 : read
+ * - bit 1 : write
+ * - bit 2 : exec
+ * - bit 3 : priv
+ * - bit 4 : global
+ * - bit 5 : untranslated only
+ */
typedef enum {
IOMMU_NONE = 0,
IOMMU_RO = 1,
IOMMU_WO = 2,
IOMMU_RW = 3,
+ IOMMU_EXEC = 4,
+ IOMMU_PRIV = 8,
+ IOMMU_GLOBAL = 16,
+ IOMMU_UNTRANSLATED_ONLY = 32,
} IOMMUAccessFlags;
-#define IOMMU_ACCESS_FLAG(r, w) (((r) ? IOMMU_RO : 0) | ((w) ? IOMMU_WO : 0))
+#define IOMMU_ACCESS_FLAG(r, w) (((r) ? IOMMU_RO : 0) | \
+ ((w) ? IOMMU_WO : 0))
+#define IOMMU_ACCESS_FLAG_FULL(r, w, x, p, g, uo) \
+ (IOMMU_ACCESS_FLAG(r, w) | \
+ ((x) ? IOMMU_EXEC : 0) | \
+ ((p) ? IOMMU_PRIV : 0) | \
+ ((g) ? IOMMU_GLOBAL : 0) | \
+ ((uo) ? IOMMU_UNTRANSLATED_ONLY : 0))
struct IOMMUTLBEntry {
AddressSpace *target_as;
--
2.48.1
next prev parent reply other threads:[~2025-02-27 10:55 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 10:54 [PATCH v4 00/19] intel_iommu: Add ATS support CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` CLEMENT MATHIEU--DRIF [this message]
2025-02-27 10:54 ` [PATCH v4 02/19] intel_iommu: Declare supported PASID size CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 03/19] memory: Allow to store the PASID in IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 04/19] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 05/19] pcie: Add helper to declare PASID capability for a pcie device CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 07/19] pcie: Helper function to check if ATS is enabled CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 06/19] pcie: Helper functions to check if PASID " CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 08/19] pci: Cache the bus mastering status in the device CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 10/19] intel_iommu: Implement the get_memory_region_pasid iommu operation CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 09/19] pci: Add IOMMU operations to get memory regions with PASID CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 12/19] pci: Add a pci-level initialization function for iommu notifiers CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 11/19] memory: Store user data pointer in the IOMMU notifiers CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 13/19] atc: Generic ATC that can be used by PCIe devices that support SVM CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 15/19] memory: Add an API for ATS support CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 14/19] atc: Add unit tests CLEMENT MATHIEU--DRIF
2025-05-13 14:50 ` Michael S. Tsirkin
2025-05-14 7:36 ` Michael S. Tsirkin
2025-05-15 5:12 ` CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 16/19] pci: Add a pci-level API for ATS CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 17/19] intel_iommu: Set address mask when a translation fails and adjust W permission CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 18/19] intel_iommu: Return page walk level even when the translation fails CLEMENT MATHIEU--DRIF
2025-02-27 10:54 ` [PATCH v4 19/19] intel_iommu: Add support for ATS CLEMENT MATHIEU--DRIF
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