From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Wei Liu" <liuwe@linux.microsoft.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 14/34] target/i386/hvf: fix a typo in a type name
Date: Thu, 27 Feb 2025 15:19:32 +0100 [thread overview]
Message-ID: <20250227141952.811410-15-pbonzini@redhat.com> (raw)
In-Reply-To: <20250227141952.811410-1-pbonzini@redhat.com>
From: Wei Liu <liuwe@linux.microsoft.com>
The prefix x68 is wrong. Change it to x86.
Signed-off-by: Wei Liu <liuwe@linux.microsoft.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/1740126987-8483-2-git-send-email-liuwe@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/hvf/x86.h | 8 ++++----
target/i386/hvf/x86_descr.h | 6 +++---
target/i386/hvf/x86_task.h | 2 +-
target/i386/hvf/hvf.c | 2 +-
target/i386/hvf/x86.c | 4 ++--
target/i386/hvf/x86_descr.c | 8 ++++----
target/i386/hvf/x86_task.c | 22 +++++++++++-----------
7 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/target/i386/hvf/x86.h b/target/i386/hvf/x86.h
index 3570f29aa9d..063cd0b83ec 100644
--- a/target/i386/hvf/x86.h
+++ b/target/i386/hvf/x86.h
@@ -183,7 +183,7 @@ static inline uint32_t x86_call_gate_offset(x86_call_gate *gate)
#define GDT_SEL 0
#define LDT_SEL 1
-typedef struct x68_segment_selector {
+typedef struct x86_segment_selector {
union {
uint16_t sel;
struct {
@@ -192,7 +192,7 @@ typedef struct x68_segment_selector {
uint16_t index:13;
};
};
-} __attribute__ ((__packed__)) x68_segment_selector;
+} __attribute__ ((__packed__)) x86_segment_selector;
/* useful register access macros */
#define x86_reg(cpu, reg) ((x86_register *) &cpu->regs[reg])
@@ -250,10 +250,10 @@ typedef struct x68_segment_selector {
/* deal with GDT/LDT descriptors in memory */
bool x86_read_segment_descriptor(CPUState *cpu,
struct x86_segment_descriptor *desc,
- x68_segment_selector sel);
+ x86_segment_selector sel);
bool x86_write_segment_descriptor(CPUState *cpu,
struct x86_segment_descriptor *desc,
- x68_segment_selector sel);
+ x86_segment_selector sel);
bool x86_read_call_gate(CPUState *cpu, struct x86_call_gate *idt_desc,
int gate);
diff --git a/target/i386/hvf/x86_descr.h b/target/i386/hvf/x86_descr.h
index 9f06014b56a..ce5de983497 100644
--- a/target/i386/hvf/x86_descr.h
+++ b/target/i386/hvf/x86_descr.h
@@ -34,10 +34,10 @@ void vmx_read_segment_descriptor(CPUState *cpu,
void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc,
enum X86Seg seg);
-x68_segment_selector vmx_read_segment_selector(CPUState *cpu,
+x86_segment_selector vmx_read_segment_selector(CPUState *cpu,
enum X86Seg seg);
void vmx_write_segment_selector(CPUState *cpu,
- x68_segment_selector selector,
+ x86_segment_selector selector,
enum X86Seg seg);
uint64_t vmx_read_segment_base(CPUState *cpu, enum X86Seg seg);
@@ -45,7 +45,7 @@ void vmx_write_segment_base(CPUState *cpu, enum X86Seg seg,
uint64_t base);
void x86_segment_descriptor_to_vmx(CPUState *cpu,
- x68_segment_selector selector,
+ x86_segment_selector selector,
struct x86_segment_descriptor *desc,
struct vmx_segment *vmx_desc);
diff --git a/target/i386/hvf/x86_task.h b/target/i386/hvf/x86_task.h
index 4eaa61a7dee..b9afac6a47b 100644
--- a/target/i386/hvf/x86_task.h
+++ b/target/i386/hvf/x86_task.h
@@ -15,6 +15,6 @@
#ifndef HVF_X86_TASK_H
#define HVF_X86_TASK_H
-void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel,
+void vmx_handle_task_switch(CPUState *cpu, x86_segment_selector tss_sel,
int reason, bool gate_valid, uint8_t gate, uint64_t gate_type);
#endif
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index ca08f0753f0..353549fa779 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -674,7 +674,7 @@ int hvf_vcpu_exec(CPUState *cpu)
}
case EXIT_REASON_TASK_SWITCH: {
uint64_t vinfo = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_INFO);
- x68_segment_selector sel = {.sel = exit_qual & 0xffff};
+ x86_segment_selector sel = {.sel = exit_qual & 0xffff};
vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3,
vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo
& VMCS_INTR_T_MASK);
diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c
index 80e36136d04..a0ede138865 100644
--- a/target/i386/hvf/x86.c
+++ b/target/i386/hvf/x86.c
@@ -48,7 +48,7 @@
bool x86_read_segment_descriptor(CPUState *cpu,
struct x86_segment_descriptor *desc,
- x68_segment_selector sel)
+ x86_segment_selector sel)
{
target_ulong base;
uint32_t limit;
@@ -78,7 +78,7 @@ bool x86_read_segment_descriptor(CPUState *cpu,
bool x86_write_segment_descriptor(CPUState *cpu,
struct x86_segment_descriptor *desc,
- x68_segment_selector sel)
+ x86_segment_selector sel)
{
target_ulong base;
uint32_t limit;
diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c
index f33836d6cba..7b599c90377 100644
--- a/target/i386/hvf/x86_descr.c
+++ b/target/i386/hvf/x86_descr.c
@@ -60,14 +60,14 @@ uint64_t vmx_read_segment_base(CPUState *cpu, X86Seg seg)
return rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base);
}
-x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg)
+x86_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg)
{
- x68_segment_selector sel;
+ x86_segment_selector sel;
sel.sel = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector);
return sel;
}
-void vmx_write_segment_selector(CPUState *cpu, x68_segment_selector selector, X86Seg seg)
+void vmx_write_segment_selector(CPUState *cpu, x86_segment_selector selector, X86Seg seg)
{
wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel);
}
@@ -90,7 +90,7 @@ void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Se
wvmcs(cpu->accel->fd, sf->ar_bytes, desc->ar);
}
-void x86_segment_descriptor_to_vmx(CPUState *cpu, x68_segment_selector selector,
+void x86_segment_descriptor_to_vmx(CPUState *cpu, x86_segment_selector selector,
struct x86_segment_descriptor *desc,
struct vmx_segment *vmx_desc)
{
diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c
index bcd844cff60..287fe11cf70 100644
--- a/target/i386/hvf/x86_task.c
+++ b/target/i386/hvf/x86_task.c
@@ -76,16 +76,16 @@ static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
RSI(env) = tss->esi;
RDI(env) = tss->edi;
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, R_LDTR);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, R_ES);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, R_CS);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, R_SS);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, R_DS);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, R_FS);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, R_GS);
+ vmx_write_segment_selector(cpu, (x86_segment_selector){{tss->ldt}}, R_LDTR);
+ vmx_write_segment_selector(cpu, (x86_segment_selector){{tss->es}}, R_ES);
+ vmx_write_segment_selector(cpu, (x86_segment_selector){{tss->cs}}, R_CS);
+ vmx_write_segment_selector(cpu, (x86_segment_selector){{tss->ss}}, R_SS);
+ vmx_write_segment_selector(cpu, (x86_segment_selector){{tss->ds}}, R_DS);
+ vmx_write_segment_selector(cpu, (x86_segment_selector){{tss->fs}}, R_FS);
+ vmx_write_segment_selector(cpu, (x86_segment_selector){{tss->gs}}, R_GS);
}
-static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segment_selector old_tss_sel,
+static int task_switch_32(CPUState *cpu, x86_segment_selector tss_sel, x86_segment_selector old_tss_sel,
uint64_t old_tss_base, struct x86_segment_descriptor *new_desc)
{
struct x86_tss_segment32 tss_seg;
@@ -108,7 +108,7 @@ static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segme
return 0;
}
-void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
+void vmx_handle_task_switch(CPUState *cpu, x86_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
{
uint64_t rip = rreg(cpu->accel->fd, HV_X86_RIP);
if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION &&
@@ -122,7 +122,7 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int rea
load_regs(cpu);
struct x86_segment_descriptor curr_tss_desc, next_tss_desc;
- x68_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, R_TR);
+ x86_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, R_TR);
uint64_t old_tss_base = vmx_read_segment_base(cpu, R_TR);
uint32_t desc_limit;
struct x86_call_gate task_gate_desc;
@@ -140,7 +140,7 @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int rea
x86_read_call_gate(cpu, &task_gate_desc, gate);
dpl = task_gate_desc.dpl;
- x68_segment_selector cs = vmx_read_segment_selector(cpu, R_CS);
+ x86_segment_selector cs = vmx_read_segment_selector(cpu, R_CS);
if (tss_sel.rpl > dpl || cs.rpl > dpl)
;//DPRINTF("emulate_gp");
}
--
2.48.1
next prev parent reply other threads:[~2025-02-27 14:22 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 14:19 [PULL 00/34] i386, Rust, build system, QOM patches for 2025-02-27 Paolo Bonzini
2025-02-27 14:19 ` [PULL 01/34] qom: Use command line syntax for default values in help Paolo Bonzini
2025-02-27 14:19 ` [PULL 02/34] hpet: do not overwrite properties on post_load Paolo Bonzini
2025-02-27 14:19 ` [PULL 03/34] i386: Fix the missing Rust HPET configuration option Paolo Bonzini
2025-02-27 14:19 ` [PULL 04/34] rust: subprojects: add libc crate Paolo Bonzini
2025-02-27 14:19 ` [PULL 05/34] rust: add module to convert between success/-errno and io::Result Paolo Bonzini
2025-02-27 14:19 ` [PULL 06/34] rust: tests: do not import bindings::* Paolo Bonzini
2025-02-27 14:19 ` [PULL 07/34] rust: prefer importing std::ptr over core::ptr Paolo Bonzini
2025-02-27 14:19 ` [PULL 08/34] docs: rust: fix typos Paolo Bonzini
2025-02-27 14:19 ` [PULL 09/34] docs: rust: update description of crates Paolo Bonzini
2025-02-27 14:19 ` [PULL 10/34] stub: Remove monitor-fd.c Paolo Bonzini
2025-02-27 14:19 ` [PULL 11/34] physmem: replace assertion with error Paolo Bonzini
2025-02-27 14:19 ` [PULL 12/34] pvg: do not enable it on cross-architecture targets Paolo Bonzini
2025-02-27 14:19 ` [PULL 13/34] pvg: add option to configure it out Paolo Bonzini
2025-02-27 14:19 ` Paolo Bonzini [this message]
2025-02-27 14:19 ` [PULL 15/34] target/i386/hvf: fix the declaration of hvf_handle_io Paolo Bonzini
2025-02-27 14:19 ` [PULL 16/34] target/i386/hvf: use x86_segment in x86_decode.c Paolo Bonzini
2025-02-27 14:19 ` [PULL 17/34] target/i386/hvf: move and rename {load, store}_regs Paolo Bonzini
2025-02-27 14:19 ` [PULL 18/34] target/i386/hvf: move and rename simulate_{rdmsr, wrmsr} Paolo Bonzini
2025-02-27 14:19 ` [PULL 19/34] target/i386/hvf: drop some dead code Paolo Bonzini
2025-02-27 14:19 ` [PULL 20/34] rust: add IsA bounds to QOM implementation traits Paolo Bonzini
2025-02-27 14:19 ` [PULL 21/34] rust: add SysBusDeviceImpl Paolo Bonzini
2025-02-27 14:19 ` [PULL 22/34] rust: qom: add ObjectImpl::CLASS_INIT Paolo Bonzini
2025-02-27 14:19 ` [PULL 23/34] rust: pl011, qemu_api tests: do not use ClassInitImpl Paolo Bonzini
2025-02-27 14:19 ` [PULL 24/34] rust: qom: get rid of ClassInitImpl Paolo Bonzini
2025-02-27 14:19 ` [PULL 25/34] i386/cpu: Support module level cache topology Paolo Bonzini
2025-02-27 14:19 ` [PULL 26/34] i386/cpu: Update cache topology with machine's configuration Paolo Bonzini
2025-02-27 14:19 ` [PULL 27/34] i386/pc: Support cache topology in -machine for PC machine Paolo Bonzini
2025-02-27 14:19 ` [PULL 28/34] i386/cpu: add has_caches flag to check smp_cache configuration Paolo Bonzini
2025-02-27 14:19 ` [PULL 29/34] target/riscv: remove unused macro DEFINE_CPU Paolo Bonzini
2025-02-27 14:19 ` [PULL 30/34] target/riscv: move 128-bit check to TCG realize Paolo Bonzini
2025-02-27 14:19 ` [PULL 31/34] target/i386: Add support for Zhaoxin CPU vendor identification Paolo Bonzini
2025-02-27 14:19 ` [PULL 32/34] target/i386: Add CPUID leaf 0xC000_0001 EDX definitions Paolo Bonzini
2025-02-27 14:19 ` [PULL 33/34] target/i386: Introduce Zhaoxin Yongfeng CPU model Paolo Bonzini
2025-02-27 14:19 ` [PULL 34/34] target/i386: Mask CMPLegacy bit in CPUID[0x80000001].ECX for Zhaoxin CPUs Paolo Bonzini
2025-03-03 12:12 ` [PULL 00/34] i386, Rust, build system, QOM patches for 2025-02-27 Stefan Hajnoczi
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