From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Wei Liu <liuwe@linux.microsoft.com>
Subject: [PULL 17/34] target/i386/hvf: move and rename {load, store}_regs
Date: Thu, 27 Feb 2025 15:19:35 +0100 [thread overview]
Message-ID: <20250227141952.811410-18-pbonzini@redhat.com> (raw)
In-Reply-To: <20250227141952.811410-1-pbonzini@redhat.com>
From: Wei Liu <liuwe@linux.microsoft.com>
They contain HVF specific code. Move them to a better location and
add "hvf_" prefix. Fix up all the call sites.
No functional change.
Signed-off-by: Wei Liu <liuwe@linux.microsoft.com>
Link: https://lore.kernel.org/r/1740126987-8483-7-git-send-email-liuwe@linux.microsoft.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/hvf/x86_emu.h | 3 --
target/i386/hvf/x86hvf.h | 3 ++
target/i386/hvf/hvf.c | 71 +++++++++++++++++++++++++++++++-------
target/i386/hvf/x86_emu.c | 46 ------------------------
target/i386/hvf/x86_task.c | 4 +--
5 files changed, 64 insertions(+), 63 deletions(-)
diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h
index 8bd97608c42..cd953849c99 100644
--- a/target/i386/hvf/x86_emu.h
+++ b/target/i386/hvf/x86_emu.h
@@ -26,9 +26,6 @@
void init_emu(void);
bool exec_instruction(CPUX86State *env, struct x86_decode *ins);
-void load_regs(CPUState *cpu);
-void store_regs(CPUState *cpu);
-
void simulate_rdmsr(CPUX86State *env);
void simulate_wrmsr(CPUX86State *env);
diff --git a/target/i386/hvf/x86hvf.h b/target/i386/hvf/x86hvf.h
index 423a89b6ad3..8c46ce8ad02 100644
--- a/target/i386/hvf/x86hvf.h
+++ b/target/i386/hvf/x86hvf.h
@@ -31,4 +31,7 @@ void hvf_get_xsave(CPUState *cs);
void hvf_get_msrs(CPUState *cs);
void vmx_clear_int_window_exiting(CPUState *cs);
void vmx_update_tpr(CPUState *cs);
+
+void hvf_load_regs(CPUState *cpu);
+void hvf_store_regs(CPUState *cpu);
#endif
diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c
index 1ecb6993ba1..3ab3c0043db 100644
--- a/target/i386/hvf/hvf.c
+++ b/target/i386/hvf/hvf.c
@@ -61,6 +61,7 @@
#include "vmx.h"
#include "x86.h"
#include "x86_descr.h"
+#include "x86_flags.h"
#include "x86_mmu.h"
#include "x86_decode.h"
#include "x86_emu.h"
@@ -434,6 +435,52 @@ static void hvf_cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
}
}
+void hvf_load_regs(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ int i = 0;
+ RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
+ RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX);
+ RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX);
+ RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX);
+ RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI);
+ RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI);
+ RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP);
+ RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP);
+ for (i = 8; i < 16; i++) {
+ RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i);
+ }
+
+ env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
+ rflags_to_lflags(env);
+ env->eip = rreg(cs->accel->fd, HV_X86_RIP);
+}
+
+void hvf_store_regs(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ int i = 0;
+ wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
+ wreg(cs->accel->fd, HV_X86_RBX, RBX(env));
+ wreg(cs->accel->fd, HV_X86_RCX, RCX(env));
+ wreg(cs->accel->fd, HV_X86_RDX, RDX(env));
+ wreg(cs->accel->fd, HV_X86_RSI, RSI(env));
+ wreg(cs->accel->fd, HV_X86_RDI, RDI(env));
+ wreg(cs->accel->fd, HV_X86_RBP, RBP(env));
+ wreg(cs->accel->fd, HV_X86_RSP, RSP(env));
+ for (i = 8; i < 16; i++) {
+ wreg(cs->accel->fd, HV_X86_RAX + i, RRX(env, i));
+ }
+
+ lflags_to_rflags(env);
+ wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags);
+ macvm_set_rip(cs, env->eip);
+}
+
int hvf_vcpu_exec(CPUState *cpu)
{
X86CPU *x86_cpu = X86_CPU(cpu);
@@ -517,10 +564,10 @@ int hvf_vcpu_exec(CPUState *cpu)
if (ept_emulation_fault(slot, gpa, exit_qual)) {
struct x86_decode decode;
- load_regs(cpu);
+ hvf_load_regs(cpu);
decode_instruction(env, &decode);
exec_instruction(env, &decode);
- store_regs(cpu);
+ hvf_store_regs(cpu);
break;
}
break;
@@ -535,7 +582,7 @@ int hvf_vcpu_exec(CPUState *cpu)
if (!string && in) {
uint64_t val = 0;
- load_regs(cpu);
+ hvf_load_regs(cpu);
hvf_handle_io(env_cpu(env), port, &val, 0, size, 1);
if (size == 1) {
AL(env) = val;
@@ -547,7 +594,7 @@ int hvf_vcpu_exec(CPUState *cpu)
RAX(env) = (uint64_t)val;
}
env->eip += ins_len;
- store_regs(cpu);
+ hvf_store_regs(cpu);
break;
} else if (!string && !in) {
RAX(env) = rreg(cpu->accel->fd, HV_X86_RAX);
@@ -557,11 +604,11 @@ int hvf_vcpu_exec(CPUState *cpu)
}
struct x86_decode decode;
- load_regs(cpu);
+ hvf_load_regs(cpu);
decode_instruction(env, &decode);
assert(ins_len == decode.len);
exec_instruction(env, &decode);
- store_regs(cpu);
+ hvf_store_regs(cpu);
break;
}
@@ -614,21 +661,21 @@ int hvf_vcpu_exec(CPUState *cpu)
case EXIT_REASON_RDMSR:
case EXIT_REASON_WRMSR:
{
- load_regs(cpu);
+ hvf_load_regs(cpu);
if (exit_reason == EXIT_REASON_RDMSR) {
simulate_rdmsr(env);
} else {
simulate_wrmsr(env);
}
env->eip += ins_len;
- store_regs(cpu);
+ hvf_store_regs(cpu);
break;
}
case EXIT_REASON_CR_ACCESS: {
int cr;
int reg;
- load_regs(cpu);
+ hvf_load_regs(cpu);
cr = exit_qual & 15;
reg = (exit_qual >> 8) & 15;
@@ -656,16 +703,16 @@ int hvf_vcpu_exec(CPUState *cpu)
abort();
}
env->eip += ins_len;
- store_regs(cpu);
+ hvf_store_regs(cpu);
break;
}
case EXIT_REASON_APIC_ACCESS: { /* TODO */
struct x86_decode decode;
- load_regs(cpu);
+ hvf_load_regs(cpu);
decode_instruction(env, &decode);
exec_instruction(env, &decode);
- store_regs(cpu);
+ hvf_store_regs(cpu);
break;
}
case EXIT_REASON_TPR: {
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index 2c7da10c1d2..8b0d54d69a0 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -1452,52 +1452,6 @@ static void init_cmd_handler(void)
}
}
-void load_regs(CPUState *cs)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
-
- int i = 0;
- RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX);
- RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX);
- RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX);
- RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX);
- RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI);
- RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI);
- RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP);
- RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP);
- for (i = 8; i < 16; i++) {
- RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i);
- }
-
- env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS);
- rflags_to_lflags(env);
- env->eip = rreg(cs->accel->fd, HV_X86_RIP);
-}
-
-void store_regs(CPUState *cs)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
-
- int i = 0;
- wreg(cs->accel->fd, HV_X86_RAX, RAX(env));
- wreg(cs->accel->fd, HV_X86_RBX, RBX(env));
- wreg(cs->accel->fd, HV_X86_RCX, RCX(env));
- wreg(cs->accel->fd, HV_X86_RDX, RDX(env));
- wreg(cs->accel->fd, HV_X86_RSI, RSI(env));
- wreg(cs->accel->fd, HV_X86_RDI, RDI(env));
- wreg(cs->accel->fd, HV_X86_RBP, RBP(env));
- wreg(cs->accel->fd, HV_X86_RSP, RSP(env));
- for (i = 8; i < 16; i++) {
- wreg(cs->accel->fd, HV_X86_RAX + i, RRX(env, i));
- }
-
- lflags_to_rflags(env);
- wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags);
- macvm_set_rip(cs, env->eip);
-}
-
bool exec_instruction(CPUX86State *env, struct x86_decode *ins)
{
/*if (hvf_vcpu_id(cs))
diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c
index 287fe11cf70..161217991fc 100644
--- a/target/i386/hvf/x86_task.c
+++ b/target/i386/hvf/x86_task.c
@@ -119,7 +119,7 @@ void vmx_handle_task_switch(CPUState *cpu, x86_segment_selector tss_sel, int rea
return;
}
- load_regs(cpu);
+ hvf_load_regs(cpu);
struct x86_segment_descriptor curr_tss_desc, next_tss_desc;
x86_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, R_TR);
@@ -178,7 +178,7 @@ void vmx_handle_task_switch(CPUState *cpu, x86_segment_selector tss_sel, int rea
x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg);
vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR);
- store_regs(cpu);
+ hvf_store_regs(cpu);
hv_vcpu_invalidate_tlb(cpu->accel->fd);
}
--
2.48.1
next prev parent reply other threads:[~2025-02-27 14:27 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 14:19 [PULL 00/34] i386, Rust, build system, QOM patches for 2025-02-27 Paolo Bonzini
2025-02-27 14:19 ` [PULL 01/34] qom: Use command line syntax for default values in help Paolo Bonzini
2025-02-27 14:19 ` [PULL 02/34] hpet: do not overwrite properties on post_load Paolo Bonzini
2025-02-27 14:19 ` [PULL 03/34] i386: Fix the missing Rust HPET configuration option Paolo Bonzini
2025-02-27 14:19 ` [PULL 04/34] rust: subprojects: add libc crate Paolo Bonzini
2025-02-27 14:19 ` [PULL 05/34] rust: add module to convert between success/-errno and io::Result Paolo Bonzini
2025-02-27 14:19 ` [PULL 06/34] rust: tests: do not import bindings::* Paolo Bonzini
2025-02-27 14:19 ` [PULL 07/34] rust: prefer importing std::ptr over core::ptr Paolo Bonzini
2025-02-27 14:19 ` [PULL 08/34] docs: rust: fix typos Paolo Bonzini
2025-02-27 14:19 ` [PULL 09/34] docs: rust: update description of crates Paolo Bonzini
2025-02-27 14:19 ` [PULL 10/34] stub: Remove monitor-fd.c Paolo Bonzini
2025-02-27 14:19 ` [PULL 11/34] physmem: replace assertion with error Paolo Bonzini
2025-02-27 14:19 ` [PULL 12/34] pvg: do not enable it on cross-architecture targets Paolo Bonzini
2025-02-27 14:19 ` [PULL 13/34] pvg: add option to configure it out Paolo Bonzini
2025-02-27 14:19 ` [PULL 14/34] target/i386/hvf: fix a typo in a type name Paolo Bonzini
2025-02-27 14:19 ` [PULL 15/34] target/i386/hvf: fix the declaration of hvf_handle_io Paolo Bonzini
2025-02-27 14:19 ` [PULL 16/34] target/i386/hvf: use x86_segment in x86_decode.c Paolo Bonzini
2025-02-27 14:19 ` Paolo Bonzini [this message]
2025-02-27 14:19 ` [PULL 18/34] target/i386/hvf: move and rename simulate_{rdmsr, wrmsr} Paolo Bonzini
2025-02-27 14:19 ` [PULL 19/34] target/i386/hvf: drop some dead code Paolo Bonzini
2025-02-27 14:19 ` [PULL 20/34] rust: add IsA bounds to QOM implementation traits Paolo Bonzini
2025-02-27 14:19 ` [PULL 21/34] rust: add SysBusDeviceImpl Paolo Bonzini
2025-02-27 14:19 ` [PULL 22/34] rust: qom: add ObjectImpl::CLASS_INIT Paolo Bonzini
2025-02-27 14:19 ` [PULL 23/34] rust: pl011, qemu_api tests: do not use ClassInitImpl Paolo Bonzini
2025-02-27 14:19 ` [PULL 24/34] rust: qom: get rid of ClassInitImpl Paolo Bonzini
2025-02-27 14:19 ` [PULL 25/34] i386/cpu: Support module level cache topology Paolo Bonzini
2025-02-27 14:19 ` [PULL 26/34] i386/cpu: Update cache topology with machine's configuration Paolo Bonzini
2025-02-27 14:19 ` [PULL 27/34] i386/pc: Support cache topology in -machine for PC machine Paolo Bonzini
2025-02-27 14:19 ` [PULL 28/34] i386/cpu: add has_caches flag to check smp_cache configuration Paolo Bonzini
2025-02-27 14:19 ` [PULL 29/34] target/riscv: remove unused macro DEFINE_CPU Paolo Bonzini
2025-02-27 14:19 ` [PULL 30/34] target/riscv: move 128-bit check to TCG realize Paolo Bonzini
2025-02-27 14:19 ` [PULL 31/34] target/i386: Add support for Zhaoxin CPU vendor identification Paolo Bonzini
2025-02-27 14:19 ` [PULL 32/34] target/i386: Add CPUID leaf 0xC000_0001 EDX definitions Paolo Bonzini
2025-02-27 14:19 ` [PULL 33/34] target/i386: Introduce Zhaoxin Yongfeng CPU model Paolo Bonzini
2025-02-27 14:19 ` [PULL 34/34] target/i386: Mask CMPLegacy bit in CPUID[0x80000001].ECX for Zhaoxin CPUs Paolo Bonzini
2025-03-03 12:12 ` [PULL 00/34] i386, Rust, build system, QOM patches for 2025-02-27 Stefan Hajnoczi
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